i8254xGBe.hh revision 6217
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/* @file 32 * Device model for Intel's 8254x line of gigabit ethernet controllers. 33 */ 34 35#ifndef __DEV_I8254XGBE_HH__ 36#define __DEV_I8254XGBE_HH__ 37 38#include <deque> 39#include <string> 40 41#include "base/cp_annotate.hh" 42#include "base/inet.hh" 43#include "dev/etherdevice.hh" 44#include "dev/etherint.hh" 45#include "dev/etherpkt.hh" 46#include "dev/i8254xGBe_defs.hh" 47#include "dev/pcidev.hh" 48#include "dev/pktfifo.hh" 49#include "params/IGbE.hh" 50#include "sim/eventq.hh" 51 52class IGbEInt; 53 54class IGbE : public EtherDevice 55{ 56 private: 57 IGbEInt *etherInt; 58 CPA *cpa; 59 60 // device registers 61 iGbReg::Regs regs; 62 63 // eeprom data, status and control bits 64 int eeOpBits, eeAddrBits, eeDataBits; 65 uint8_t eeOpcode, eeAddr; 66 uint16_t flash[iGbReg::EEPROM_SIZE]; 67 68 // The drain event if we have one 69 Event *drainEvent; 70 71 // cached parameters from params struct 72 bool useFlowControl; 73 74 // packet fifos 75 PacketFifo rxFifo; 76 PacketFifo txFifo; 77 78 // Packet that we are currently putting into the txFifo 79 EthPacketPtr txPacket; 80 81 // Should to Rx/Tx State machine tick? 82 bool rxTick; 83 bool txTick; 84 bool txFifoTick; 85 86 bool rxDmaPacket; 87 88 // Number of bytes copied from current RX packet 89 int pktOffset; 90 91 // Delays in managaging descriptors 92 Tick fetchDelay, wbDelay; 93 Tick fetchCompDelay, wbCompDelay; 94 Tick rxWriteDelay, txReadDelay; 95 96 // Event and function to deal with RDTR timer expiring 97 void rdtrProcess() { 98 rxDescCache.writeback(0); 99 DPRINTF(EthernetIntr, 100 "Posting RXT interrupt because RDTR timer expired\n"); 101 postInterrupt(iGbReg::IT_RXT); 102 } 103 104 //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>; 105 EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent; 106 107 // Event and function to deal with RADV timer expiring 108 void radvProcess() { 109 rxDescCache.writeback(0); 110 DPRINTF(EthernetIntr, 111 "Posting RXT interrupt because RADV timer expired\n"); 112 postInterrupt(iGbReg::IT_RXT); 113 } 114 115 //friend class EventWrapper<IGbE, &IGbE::radvProcess>; 116 EventWrapper<IGbE, &IGbE::radvProcess> radvEvent; 117 118 // Event and function to deal with TADV timer expiring 119 void tadvProcess() { 120 txDescCache.writeback(0); 121 DPRINTF(EthernetIntr, 122 "Posting TXDW interrupt because TADV timer expired\n"); 123 postInterrupt(iGbReg::IT_TXDW); 124 } 125 126 //friend class EventWrapper<IGbE, &IGbE::tadvProcess>; 127 EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent; 128 129 // Event and function to deal with TIDV timer expiring 130 void tidvProcess() { 131 txDescCache.writeback(0); 132 DPRINTF(EthernetIntr, 133 "Posting TXDW interrupt because TIDV timer expired\n"); 134 postInterrupt(iGbReg::IT_TXDW); 135 } 136 //friend class EventWrapper<IGbE, &IGbE::tidvProcess>; 137 EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent; 138 139 // Main event to tick the device 140 void tick(); 141 //friend class EventWrapper<IGbE, &IGbE::tick>; 142 EventWrapper<IGbE, &IGbE::tick> tickEvent; 143 144 145 uint64_t macAddr; 146 147 void rxStateMachine(); 148 void txStateMachine(); 149 void txWire(); 150 151 /** Write an interrupt into the interrupt pending register and check mask 152 * and interrupt limit timer before sending interrupt to CPU 153 * @param t the type of interrupt we are posting 154 * @param now should we ignore the interrupt limiting timer 155 */ 156 void postInterrupt(iGbReg::IntTypes t, bool now = false); 157 158 /** Check and see if changes to the mask register have caused an interrupt 159 * to need to be sent or perhaps removed an interrupt cause. 160 */ 161 void chkInterrupt(); 162 163 /** Send an interrupt to the cpu 164 */ 165 void delayIntEvent(); 166 void cpuPostInt(); 167 // Event to moderate interrupts 168 EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent; 169 170 /** Clear the interupt line to the cpu 171 */ 172 void cpuClearInt(); 173 174 Tick intClock() { return Clock::Int::ns * 1024; } 175 176 /** This function is used to restart the clock so it can handle things like 177 * draining and resume in one place. */ 178 void restartClock(); 179 180 /** Check if all the draining things that need to occur have occured and 181 * handle the drain event if so. 182 */ 183 void checkDrain(); 184 185 void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) { 186 cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st); 187 } 188 189 void anQ(std::string sm, std::string q) { 190 cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 191 } 192 193 void anDq(std::string sm, std::string q) { 194 cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 195 } 196 197 void anPq(std::string sm, std::string q, int num = 1) { 198 cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 199 } 200 201 void anRq(std::string sm, std::string q, int num = 1) { 202 cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 203 } 204 205 void anWe(std::string sm, std::string q) { 206 cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 207 } 208 209 void anWf(std::string sm, std::string q) { 210 cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 211 } 212 213 214 template<class T> 215 class DescCache 216 { 217 protected: 218 virtual Addr descBase() const = 0; 219 virtual long descHead() const = 0; 220 virtual long descTail() const = 0; 221 virtual long descLen() const = 0; 222 virtual void updateHead(long h) = 0; 223 virtual void enableSm() = 0; 224 virtual void actionAfterWb() {} 225 virtual void fetchAfterWb() = 0; 226 227 std::deque<T*> usedCache; 228 std::deque<T*> unusedCache; 229 230 T *fetchBuf; 231 T *wbBuf; 232 233 // Pointer to the device we cache for 234 IGbE *igbe; 235 236 // Name of this descriptor cache 237 std::string _name; 238 239 // How far we've cached 240 int cachePnt; 241 242 // The size of the descriptor cache 243 int size; 244 245 // How many descriptors we are currently fetching 246 int curFetching; 247 248 // How many descriptors we are currently writing back 249 int wbOut; 250 251 // if the we wrote back to the end of the descriptor ring and are going 252 // to have to wrap and write more 253 bool moreToWb; 254 255 // What the alignment is of the next descriptor writeback 256 Addr wbAlignment; 257 258 /** The packet that is currently being dmad to memory if any */ 259 EthPacketPtr pktPtr; 260 261 /** Shortcut for DMA address translation */ 262 Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); } 263 264 public: 265 /** Annotate sm*/ 266 std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ, 267 annUsedDescQ, annUnusedCacheQ, annDescQ; 268 269 DescCache(IGbE *i, const std::string n, int s); 270 virtual ~DescCache(); 271 272 std::string name() { return _name; } 273 274 /** If the address/len/head change when we've got descriptors that are 275 * dirty that is very bad. This function checks that we don't and if we 276 * do panics. 277 */ 278 void areaChanged(); 279 280 void writeback(Addr aMask); 281 void writeback1(); 282 EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent; 283 284 /** Fetch a chunk of descriptors into the descriptor cache. 285 * Calls fetchComplete when the memory system returns the data 286 */ 287 void fetchDescriptors(); 288 void fetchDescriptors1(); 289 EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent; 290 291 /** Called by event when dma to read descriptors is completed 292 */ 293 void fetchComplete(); 294 EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent; 295 296 /** Called by event when dma to writeback descriptors is completed 297 */ 298 void wbComplete(); 299 EventWrapper<DescCache, &DescCache::wbComplete> wbEvent; 300 301 /* Return the number of descriptors left in the ring, so the device has 302 * a way to figure out if it needs to interrupt. 303 */ 304 int descLeft() const 305 { 306 int left = unusedCache.size(); 307 if (cachePnt > descTail()) 308 left += (descLen() - cachePnt + descTail()); 309 else 310 left += (descTail() - cachePnt); 311 312 return left; 313 } 314 315 /* Return the number of descriptors used and not written back. 316 */ 317 int descUsed() const { return usedCache.size(); } 318 319 /* Return the number of cache unused descriptors we have. */ 320 int descUnused() const {return unusedCache.size(); } 321 322 /* Get into a state where the descriptor address/head/etc colud be 323 * changed */ 324 void reset(); 325 326 virtual void serialize(std::ostream &os); 327 virtual void unserialize(Checkpoint *cp, const std::string §ion); 328 329 virtual bool hasOutstandingEvents() { 330 return wbEvent.scheduled() || fetchEvent.scheduled(); 331 } 332 333 }; 334 335 336 class RxDescCache : public DescCache<iGbReg::RxDesc> 337 { 338 protected: 339 virtual Addr descBase() const { return igbe->regs.rdba(); } 340 virtual long descHead() const { return igbe->regs.rdh(); } 341 virtual long descLen() const { return igbe->regs.rdlen() >> 4; } 342 virtual long descTail() const { return igbe->regs.rdt(); } 343 virtual void updateHead(long h) { igbe->regs.rdh(h); } 344 virtual void enableSm(); 345 virtual void fetchAfterWb() { 346 if (!igbe->rxTick && igbe->getState() == SimObject::Running) 347 fetchDescriptors(); 348 } 349 350 bool pktDone; 351 352 /** Variable to head with header/data completion events */ 353 int splitCount; 354 355 /** Bytes of packet that have been copied, so we know when to 356 set EOP */ 357 int bytesCopied; 358 359 public: 360 RxDescCache(IGbE *i, std::string n, int s); 361 362 /** Write the given packet into the buffer(s) pointed to by the 363 * descriptor and update the book keeping. Should only be called when 364 * there are no dma's pending. 365 * @param packet ethernet packet to write 366 * @param pkt_offset bytes already copied from the packet to memory 367 * @return pkt_offset + number of bytes copied during this call 368 */ 369 int writePacket(EthPacketPtr packet, int pkt_offset); 370 371 /** Called by event when dma to write packet is completed 372 */ 373 void pktComplete(); 374 375 /** Check if the dma on the packet has completed and RX state machine 376 * can continue 377 */ 378 bool packetDone(); 379 380 EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent; 381 382 // Event to handle issuing header and data write at the same time 383 // and only callking pktComplete() when both are completed 384 void pktSplitDone(); 385 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent; 386 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent; 387 388 virtual bool hasOutstandingEvents(); 389 390 virtual void serialize(std::ostream &os); 391 virtual void unserialize(Checkpoint *cp, const std::string §ion); 392 }; 393 friend class RxDescCache; 394 395 RxDescCache rxDescCache; 396 397 class TxDescCache : public DescCache<iGbReg::TxDesc> 398 { 399 protected: 400 virtual Addr descBase() const { return igbe->regs.tdba(); } 401 virtual long descHead() const { return igbe->regs.tdh(); } 402 virtual long descTail() const { return igbe->regs.tdt(); } 403 virtual long descLen() const { return igbe->regs.tdlen() >> 4; } 404 virtual void updateHead(long h) { igbe->regs.tdh(h); } 405 virtual void enableSm(); 406 virtual void actionAfterWb(); 407 virtual void fetchAfterWb() { 408 if (!igbe->txTick && igbe->getState() == SimObject::Running) 409 fetchDescriptors(); 410 } 411 412 413 414 bool pktDone; 415 bool isTcp; 416 bool pktWaiting; 417 bool pktMultiDesc; 418 Addr completionAddress; 419 bool completionEnabled; 420 uint32_t descEnd; 421 422 423 // tso variables 424 bool useTso; 425 Addr tsoHeaderLen; 426 Addr tsoMss; 427 Addr tsoTotalLen; 428 Addr tsoUsedLen; 429 Addr tsoPrevSeq;; 430 Addr tsoPktPayloadBytes; 431 bool tsoLoadedHeader; 432 bool tsoPktHasHeader; 433 uint8_t tsoHeader[256]; 434 Addr tsoDescBytesUsed; 435 Addr tsoCopyBytes; 436 int tsoPkts; 437 438 public: 439 TxDescCache(IGbE *i, std::string n, int s); 440 441 /** Tell the cache to DMA a packet from main memory into its buffer and 442 * return the size the of the packet to reserve space in tx fifo. 443 * @return size of the packet 444 */ 445 int getPacketSize(EthPacketPtr p); 446 void getPacketData(EthPacketPtr p); 447 void processContextDesc(); 448 449 /** Return the number of dsecriptors in a cache block for threshold 450 * operations. 451 */ 452 int descInBlock(int num_desc) { return num_desc / 453 igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc); } 454 /** Ask if the packet has been transfered so the state machine can give 455 * it to the fifo. 456 * @return packet available in descriptor cache 457 */ 458 bool packetAvailable(); 459 460 /** Ask if we are still waiting for the packet to be transfered. 461 * @return packet still in transit. 462 */ 463 bool packetWaiting() { return pktWaiting; } 464 465 /** Ask if this packet is composed of multiple descriptors 466 * so even if we've got data, we need to wait for more before 467 * we can send it out. 468 * @return packet can't be sent out because it's a multi-descriptor 469 * packet 470 */ 471 bool packetMultiDesc() { return pktMultiDesc;} 472 473 /** Called by event when dma to write packet is completed 474 */ 475 void pktComplete(); 476 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 477 478 void headerComplete(); 479 EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent; 480 481 482 void completionWriteback(Addr a, bool enabled) { 483 DPRINTF(EthernetDesc, 484 "Completion writeback Addr: %#x enabled: %d\n", 485 a, enabled); 486 completionAddress = a; 487 completionEnabled = enabled; 488 } 489 490 virtual bool hasOutstandingEvents(); 491 492 void nullCallback() { 493 DPRINTF(EthernetDesc, "Completion writeback complete\n"); 494 } 495 EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent; 496 497 virtual void serialize(std::ostream &os); 498 virtual void unserialize(Checkpoint *cp, const std::string §ion); 499 500 }; 501 friend class TxDescCache; 502 503 TxDescCache txDescCache; 504 505 public: 506 typedef IGbEParams Params; 507 const Params * 508 params() const { 509 return dynamic_cast<const Params *>(_params); 510 } 511 512 IGbE(const Params *params); 513 ~IGbE() {} 514 virtual void init(); 515 516 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 517 518 Tick clock; 519 Tick lastInterrupt; 520 inline Tick ticks(int numCycles) const { return numCycles * clock; } 521 522 virtual Tick read(PacketPtr pkt); 523 virtual Tick write(PacketPtr pkt); 524 525 virtual Tick writeConfig(PacketPtr pkt); 526 527 bool ethRxPkt(EthPacketPtr packet); 528 void ethTxDone(); 529 530 virtual void serialize(std::ostream &os); 531 virtual void unserialize(Checkpoint *cp, const std::string §ion); 532 virtual unsigned int drain(Event *de); 533 virtual void resume(); 534 535}; 536 537class IGbEInt : public EtherInt 538{ 539 private: 540 IGbE *dev; 541 542 public: 543 IGbEInt(const std::string &name, IGbE *d) 544 : EtherInt(name), dev(d) 545 { } 546 547 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); } 548 virtual void sendDone() { dev->ethTxDone(); } 549}; 550 551 552 553 554 555#endif //__DEV_I8254XGBE_HH__ 556 557