i8254xGBe.hh revision 5500
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/* @file 32 * Device model for Intel's 8254x line of gigabit ethernet controllers. 33 */ 34 35#ifndef __DEV_I8254XGBE_HH__ 36#define __DEV_I8254XGBE_HH__ 37 38#include <deque> 39#include <string> 40 41#include "base/inet.hh" 42#include "dev/etherdevice.hh" 43#include "dev/etherint.hh" 44#include "dev/etherpkt.hh" 45#include "dev/i8254xGBe_defs.hh" 46#include "dev/pcidev.hh" 47#include "dev/pktfifo.hh" 48#include "params/IGbE.hh" 49#include "sim/eventq.hh" 50 51class IGbEInt; 52 53class IGbE : public EtherDevice 54{ 55 private: 56 IGbEInt *etherInt; 57 58 // device registers 59 iGbReg::Regs regs; 60 61 // eeprom data, status and control bits 62 int eeOpBits, eeAddrBits, eeDataBits; 63 uint8_t eeOpcode, eeAddr; 64 uint16_t flash[iGbReg::EEPROM_SIZE]; 65 66 // The drain event if we have one 67 Event *drainEvent; 68 69 // cached parameters from params struct 70 bool useFlowControl; 71 72 // packet fifos 73 PacketFifo rxFifo; 74 PacketFifo txFifo; 75 76 // Packet that we are currently putting into the txFifo 77 EthPacketPtr txPacket; 78 79 // Should to Rx/Tx State machine tick? 80 bool rxTick; 81 bool txTick; 82 bool txFifoTick; 83 84 bool rxDmaPacket; 85 86 // Event and function to deal with RDTR timer expiring 87 void rdtrProcess() { 88 rxDescCache.writeback(0); 89 DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer expired\n"); 90 postInterrupt(iGbReg::IT_RXT, true); 91 } 92 93 //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>; 94 EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent; 95 96 // Event and function to deal with RADV timer expiring 97 void radvProcess() { 98 rxDescCache.writeback(0); 99 DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer expired\n"); 100 postInterrupt(iGbReg::IT_RXT, true); 101 } 102 103 //friend class EventWrapper<IGbE, &IGbE::radvProcess>; 104 EventWrapper<IGbE, &IGbE::radvProcess> radvEvent; 105 106 // Event and function to deal with TADV timer expiring 107 void tadvProcess() { 108 txDescCache.writeback(0); 109 DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer expired\n"); 110 postInterrupt(iGbReg::IT_TXDW, true); 111 } 112 113 //friend class EventWrapper<IGbE, &IGbE::tadvProcess>; 114 EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent; 115 116 // Event and function to deal with TIDV timer expiring 117 void tidvProcess() { 118 txDescCache.writeback(0); 119 DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer expired\n"); 120 postInterrupt(iGbReg::IT_TXDW, true); 121 } 122 //friend class EventWrapper<IGbE, &IGbE::tidvProcess>; 123 EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent; 124 125 // Main event to tick the device 126 void tick(); 127 //friend class EventWrapper<IGbE, &IGbE::tick>; 128 EventWrapper<IGbE, &IGbE::tick> tickEvent; 129 130 131 void rxStateMachine(); 132 void txStateMachine(); 133 void txWire(); 134 135 /** Write an interrupt into the interrupt pending register and check mask 136 * and interrupt limit timer before sending interrupt to CPU 137 * @param t the type of interrupt we are posting 138 * @param now should we ignore the interrupt limiting timer 139 */ 140 void postInterrupt(iGbReg::IntTypes t, bool now = false); 141 142 /** Check and see if changes to the mask register have caused an interrupt 143 * to need to be sent or perhaps removed an interrupt cause. 144 */ 145 void chkInterrupt(); 146 147 /** Send an interrupt to the cpu 148 */ 149 void delayIntEvent(); 150 void cpuPostInt(); 151 // Event to moderate interrupts 152 EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent; 153 154 /** Clear the interupt line to the cpu 155 */ 156 void cpuClearInt(); 157 158 Tick intClock() { return Clock::Int::ns * 1024; } 159 160 /** This function is used to restart the clock so it can handle things like 161 * draining and resume in one place. */ 162 void restartClock(); 163 164 /** Check if all the draining things that need to occur have occured and 165 * handle the drain event if so. 166 */ 167 void checkDrain(); 168 169 template<class T> 170 class DescCache 171 { 172 protected: 173 virtual Addr descBase() const = 0; 174 virtual long descHead() const = 0; 175 virtual long descTail() const = 0; 176 virtual long descLen() const = 0; 177 virtual void updateHead(long h) = 0; 178 virtual void enableSm() = 0; 179 virtual void intAfterWb() const {} 180 virtual void fetchAfterWb() = 0; 181 182 std::deque<T*> usedCache; 183 std::deque<T*> unusedCache; 184 185 T *fetchBuf; 186 T *wbBuf; 187 188 // Pointer to the device we cache for 189 IGbE *igbe; 190 191 // Name of this descriptor cache 192 std::string _name; 193 194 // How far we've cached 195 int cachePnt; 196 197 // The size of the descriptor cache 198 int size; 199 200 // How many descriptors we are currently fetching 201 int curFetching; 202 203 // How many descriptors we are currently writing back 204 int wbOut; 205 206 // if the we wrote back to the end of the descriptor ring and are going 207 // to have to wrap and write more 208 bool moreToWb; 209 210 // What the alignment is of the next descriptor writeback 211 Addr wbAlignment; 212 213 /** The packet that is currently being dmad to memory if any 214 */ 215 EthPacketPtr pktPtr; 216 217 public: 218 DescCache(IGbE *i, const std::string n, int s) 219 : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), wbOut(0), 220 pktPtr(NULL), fetchEvent(this), wbEvent(this) 221 { 222 fetchBuf = new T[size]; 223 wbBuf = new T[size]; 224 } 225 226 virtual ~DescCache() 227 { 228 reset(); 229 } 230 231 std::string name() { return _name; } 232 233 /** If the address/len/head change when we've got descriptors that are 234 * dirty that is very bad. This function checks that we don't and if we 235 * do panics. 236 */ 237 void areaChanged() 238 { 239 if (usedCache.size() > 0 || curFetching || wbOut) 240 panic("Descriptor Address, Length or Head changed. Bad\n"); 241 reset(); 242 243 } 244 245 void writeback(Addr aMask) 246 { 247 int curHead = descHead(); 248 int max_to_wb = usedCache.size(); 249 250 DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: " 251 "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n", 252 curHead, descTail(), descLen(), cachePnt, max_to_wb, 253 descLeft()); 254 255 // Check if this writeback is less restrictive that the previous 256 // and if so setup another one immediately following it 257 if (wbOut && (aMask < wbAlignment)) { 258 moreToWb = true; 259 wbAlignment = aMask; 260 DPRINTF(EthernetDesc, "Writing back already in process, returning\n"); 261 return; 262 } 263 264 265 moreToWb = false; 266 wbAlignment = aMask; 267 268 if (max_to_wb + curHead >= descLen()) { 269 max_to_wb = descLen() - curHead; 270 moreToWb = true; 271 // this is by definition aligned correctly 272 } else if (aMask != 0) { 273 // align the wb point to the mask 274 max_to_wb = max_to_wb & ~aMask; 275 } 276 277 DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb); 278 279 if (max_to_wb <= 0 || wbOut) 280 return; 281 282 wbOut = max_to_wb; 283 284 for (int x = 0; x < wbOut; x++) { 285 assert(usedCache.size()); 286 memcpy(&wbBuf[x], usedCache[0], sizeof(T)); 287 delete usedCache[0]; 288 usedCache.pop_front(); 289 } 290 291 292 assert(wbOut); 293 igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)), 294 wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf); 295 } 296 297 /** Fetch a chunk of descriptors into the descriptor cache. 298 * Calls fetchComplete when the memory system returns the data 299 */ 300 void fetchDescriptors() 301 { 302 size_t max_to_fetch; 303 304 if (curFetching) 305 return; 306 307 if (descTail() >= cachePnt) 308 max_to_fetch = descTail() - cachePnt; 309 else 310 max_to_fetch = descLen() - cachePnt; 311 312 size_t free_cache = size - usedCache.size() - unusedCache.size(); 313 314 max_to_fetch = std::min(max_to_fetch, free_cache); 315 316 DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: " 317 "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n", 318 descHead(), descTail(), descLen(), cachePnt, 319 max_to_fetch, descLeft()); 320 321 // Nothing to do 322 if (max_to_fetch == 0) 323 return; 324 325 // So we don't have two descriptor fetches going on at once 326 curFetching = max_to_fetch; 327 328 DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n", 329 descBase() + cachePnt * sizeof(T), 330 igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)), 331 curFetching * sizeof(T)); 332 assert(curFetching); 333 igbe->dmaRead(igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)), 334 curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf); 335 } 336 337 338 /** Called by event when dma to read descriptors is completed 339 */ 340 void fetchComplete() 341 { 342 T *newDesc; 343 for (int x = 0; x < curFetching; x++) { 344 newDesc = new T; 345 memcpy(newDesc, &fetchBuf[x], sizeof(T)); 346 unusedCache.push_back(newDesc); 347 } 348 349#ifndef NDEBUG 350 int oldCp = cachePnt; 351#endif 352 353 cachePnt += curFetching; 354 assert(cachePnt <= descLen()); 355 if (cachePnt == descLen()) 356 cachePnt = 0; 357 358 curFetching = 0; 359 360 DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n", 361 oldCp, cachePnt); 362 363 enableSm(); 364 igbe->checkDrain(); 365 } 366 367 EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent; 368 369 /** Called by event when dma to writeback descriptors is completed 370 */ 371 void wbComplete() 372 { 373 374 long curHead = descHead(); 375#ifndef NDEBUG 376 long oldHead = curHead; 377#endif 378 379 curHead += wbOut; 380 wbOut = 0; 381 382 if (curHead >= descLen()) 383 curHead -= descLen(); 384 385 // Update the head 386 updateHead(curHead); 387 388 DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n", 389 oldHead, curHead); 390 391 // If we still have more to wb, call wb now 392 intAfterWb(); 393 if (moreToWb) { 394 DPRINTF(EthernetDesc, "Writeback has more todo\n"); 395 writeback(wbAlignment); 396 } 397 398 if (!wbOut) { 399 igbe->checkDrain(); 400 } 401 fetchAfterWb(); 402 } 403 404 405 EventWrapper<DescCache, &DescCache::wbComplete> wbEvent; 406 407 /* Return the number of descriptors left in the ring, so the device has 408 * a way to figure out if it needs to interrupt. 409 */ 410 int descLeft() const 411 { 412 int left = unusedCache.size(); 413 if (cachePnt - descTail() >= 0) 414 left += (cachePnt - descTail()); 415 else 416 left += (descTail() - cachePnt); 417 418 return left; 419 } 420 421 /* Return the number of descriptors used and not written back. 422 */ 423 int descUsed() const { return usedCache.size(); } 424 425 /* Return the number of cache unused descriptors we have. */ 426 int descUnused() const {return unusedCache.size(); } 427 428 /* Get into a state where the descriptor address/head/etc colud be 429 * changed */ 430 void reset() 431 { 432 DPRINTF(EthernetDesc, "Reseting descriptor cache\n"); 433 for (int x = 0; x < usedCache.size(); x++) 434 delete usedCache[x]; 435 for (int x = 0; x < unusedCache.size(); x++) 436 delete unusedCache[x]; 437 438 usedCache.clear(); 439 unusedCache.clear(); 440 441 cachePnt = 0; 442 443 } 444 445 virtual void serialize(std::ostream &os) 446 { 447 SERIALIZE_SCALAR(cachePnt); 448 SERIALIZE_SCALAR(curFetching); 449 SERIALIZE_SCALAR(wbOut); 450 SERIALIZE_SCALAR(moreToWb); 451 SERIALIZE_SCALAR(wbAlignment); 452 453 int usedCacheSize = usedCache.size(); 454 SERIALIZE_SCALAR(usedCacheSize); 455 for(int x = 0; x < usedCacheSize; x++) { 456 arrayParamOut(os, csprintf("usedCache_%d", x), 457 (uint8_t*)usedCache[x],sizeof(T)); 458 } 459 460 int unusedCacheSize = unusedCache.size(); 461 SERIALIZE_SCALAR(unusedCacheSize); 462 for(int x = 0; x < unusedCacheSize; x++) { 463 arrayParamOut(os, csprintf("unusedCache_%d", x), 464 (uint8_t*)unusedCache[x],sizeof(T)); 465 } 466 } 467 468 virtual void unserialize(Checkpoint *cp, const std::string §ion) 469 { 470 UNSERIALIZE_SCALAR(cachePnt); 471 UNSERIALIZE_SCALAR(curFetching); 472 UNSERIALIZE_SCALAR(wbOut); 473 UNSERIALIZE_SCALAR(moreToWb); 474 UNSERIALIZE_SCALAR(wbAlignment); 475 476 int usedCacheSize; 477 UNSERIALIZE_SCALAR(usedCacheSize); 478 T *temp; 479 for(int x = 0; x < usedCacheSize; x++) { 480 temp = new T; 481 arrayParamIn(cp, section, csprintf("usedCache_%d", x), 482 (uint8_t*)temp,sizeof(T)); 483 usedCache.push_back(temp); 484 } 485 486 int unusedCacheSize; 487 UNSERIALIZE_SCALAR(unusedCacheSize); 488 for(int x = 0; x < unusedCacheSize; x++) { 489 temp = new T; 490 arrayParamIn(cp, section, csprintf("unusedCache_%d", x), 491 (uint8_t*)temp,sizeof(T)); 492 unusedCache.push_back(temp); 493 } 494 } 495 virtual bool hasOutstandingEvents() { 496 return wbEvent.scheduled() || fetchEvent.scheduled(); 497 } 498 499 }; 500 501 502 class RxDescCache : public DescCache<iGbReg::RxDesc> 503 { 504 protected: 505 virtual Addr descBase() const { return igbe->regs.rdba(); } 506 virtual long descHead() const { return igbe->regs.rdh(); } 507 virtual long descLen() const { return igbe->regs.rdlen() >> 4; } 508 virtual long descTail() const { return igbe->regs.rdt(); } 509 virtual void updateHead(long h) { igbe->regs.rdh(h); } 510 virtual void enableSm(); 511 virtual void fetchAfterWb() { 512 if (!igbe->rxTick && igbe->getState() == SimObject::Running) 513 fetchDescriptors(); 514 } 515 516 bool pktDone; 517 518 public: 519 RxDescCache(IGbE *i, std::string n, int s); 520 521 /** Write the given packet into the buffer(s) pointed to by the 522 * descriptor and update the book keeping. Should only be called when 523 * there are no dma's pending. 524 * @param packet ethernet packet to write 525 * @return if the packet could be written (there was a free descriptor) 526 */ 527 void writePacket(EthPacketPtr packet); 528 /** Called by event when dma to write packet is completed 529 */ 530 void pktComplete(); 531 532 /** Check if the dma on the packet has completed. 533 */ 534 535 bool packetDone(); 536 537 EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent; 538 539 virtual bool hasOutstandingEvents(); 540 541 virtual void serialize(std::ostream &os); 542 virtual void unserialize(Checkpoint *cp, const std::string §ion); 543 }; 544 friend class RxDescCache; 545 546 RxDescCache rxDescCache; 547 548 class TxDescCache : public DescCache<iGbReg::TxDesc> 549 { 550 protected: 551 virtual Addr descBase() const { return igbe->regs.tdba(); } 552 virtual long descHead() const { return igbe->regs.tdh(); } 553 virtual long descTail() const { return igbe->regs.tdt(); } 554 virtual long descLen() const { return igbe->regs.tdlen() >> 4; } 555 virtual void updateHead(long h) { igbe->regs.tdh(h); } 556 virtual void enableSm(); 557 virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW); } 558 virtual void fetchAfterWb() { 559 if (!igbe->txTick && igbe->getState() == SimObject::Running) 560 fetchDescriptors(); 561 } 562 563 bool pktDone; 564 bool isTcp; 565 bool pktWaiting; 566 bool pktMultiDesc; 567 568 public: 569 TxDescCache(IGbE *i, std::string n, int s); 570 571 /** Tell the cache to DMA a packet from main memory into its buffer and 572 * return the size the of the packet to reserve space in tx fifo. 573 * @return size of the packet 574 */ 575 int getPacketSize(); 576 void getPacketData(EthPacketPtr p); 577 578 /** Ask if the packet has been transfered so the state machine can give 579 * it to the fifo. 580 * @return packet available in descriptor cache 581 */ 582 bool packetAvailable(); 583 584 /** Ask if we are still waiting for the packet to be transfered. 585 * @return packet still in transit. 586 */ 587 bool packetWaiting() { return pktWaiting; } 588 589 /** Ask if this packet is composed of multiple descriptors 590 * so even if we've got data, we need to wait for more before 591 * we can send it out. 592 * @return packet can't be sent out because it's a multi-descriptor 593 * packet 594 */ 595 bool packetMultiDesc() { return pktMultiDesc;} 596 597 /** Called by event when dma to write packet is completed 598 */ 599 void pktComplete(); 600 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 601 602 virtual bool hasOutstandingEvents(); 603 604 virtual void serialize(std::ostream &os); 605 virtual void unserialize(Checkpoint *cp, const std::string §ion); 606 607 }; 608 friend class TxDescCache; 609 610 TxDescCache txDescCache; 611 612 public: 613 typedef IGbEParams Params; 614 const Params * 615 params() const 616 { 617 return dynamic_cast<const Params *>(_params); 618 } 619 IGbE(const Params *params); 620 ~IGbE() {} 621 622 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 623 624 Tick clock; 625 Tick lastInterrupt; 626 inline Tick ticks(int numCycles) const { return numCycles * clock; } 627 628 virtual Tick read(PacketPtr pkt); 629 virtual Tick write(PacketPtr pkt); 630 631 virtual Tick writeConfig(PacketPtr pkt); 632 633 bool ethRxPkt(EthPacketPtr packet); 634 void ethTxDone(); 635 636 virtual void serialize(std::ostream &os); 637 virtual void unserialize(Checkpoint *cp, const std::string §ion); 638 virtual unsigned int drain(Event *de); 639 virtual void resume(); 640 641}; 642 643class IGbEInt : public EtherInt 644{ 645 private: 646 IGbE *dev; 647 648 public: 649 IGbEInt(const std::string &name, IGbE *d) 650 : EtherInt(name), dev(d) 651 { } 652 653 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); } 654 virtual void sendDone() { dev->ethTxDone(); } 655}; 656 657 658 659 660 661#endif //__DEV_I8254XGBE_HH__ 662 663