i8254xGBe.hh revision 4987
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/* @file 32 * Device model for Intel's 8254x line of gigabit ethernet controllers. 33 */ 34 35#ifndef __DEV_I8254XGBE_HH__ 36#define __DEV_I8254XGBE_HH__ 37 38#include <deque> 39#include <string> 40 41#include "base/inet.hh" 42#include "base/statistics.hh" 43#include "dev/etherdevice.hh" 44#include "dev/etherint.hh" 45#include "dev/etherpkt.hh" 46#include "dev/i8254xGBe_defs.hh" 47#include "dev/pcidev.hh" 48#include "dev/pktfifo.hh" 49#include "params/IGbE.hh" 50#include "sim/eventq.hh" 51 52class IGbEInt; 53 54class IGbE : public EtherDevice 55{ 56 private: 57 IGbEInt *etherInt; 58 59 // device registers 60 iGbReg::Regs regs; 61 62 // eeprom data, status and control bits 63 int eeOpBits, eeAddrBits, eeDataBits; 64 uint8_t eeOpcode, eeAddr; 65 uint16_t flash[iGbReg::EEPROM_SIZE]; 66 67 // The drain event if we have one 68 Event *drainEvent; 69 70 // cached parameters from params struct 71 bool useFlowControl; 72 73 // packet fifos 74 PacketFifo rxFifo; 75 PacketFifo txFifo; 76 77 // Packet that we are currently putting into the txFifo 78 EthPacketPtr txPacket; 79 80 // Should to Rx/Tx State machine tick? 81 bool rxTick; 82 bool txTick; 83 bool txFifoTick; 84 85 bool rxDmaPacket; 86 87 // Event and function to deal with RDTR timer expiring 88 void rdtrProcess() { 89 rxDescCache.writeback(0); 90 DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer expired\n"); 91 postInterrupt(iGbReg::IT_RXT, true); 92 } 93 94 //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>; 95 EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent; 96 97 // Event and function to deal with RADV timer expiring 98 void radvProcess() { 99 rxDescCache.writeback(0); 100 DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer expired\n"); 101 postInterrupt(iGbReg::IT_RXT, true); 102 } 103 104 //friend class EventWrapper<IGbE, &IGbE::radvProcess>; 105 EventWrapper<IGbE, &IGbE::radvProcess> radvEvent; 106 107 // Event and function to deal with TADV timer expiring 108 void tadvProcess() { 109 txDescCache.writeback(0); 110 DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer expired\n"); 111 postInterrupt(iGbReg::IT_TXDW, true); 112 } 113 114 //friend class EventWrapper<IGbE, &IGbE::tadvProcess>; 115 EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent; 116 117 // Event and function to deal with TIDV timer expiring 118 void tidvProcess() { 119 txDescCache.writeback(0); 120 DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer expired\n"); 121 postInterrupt(iGbReg::IT_TXDW, true); 122 } 123 //friend class EventWrapper<IGbE, &IGbE::tidvProcess>; 124 EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent; 125 126 // Main event to tick the device 127 void tick(); 128 //friend class EventWrapper<IGbE, &IGbE::tick>; 129 EventWrapper<IGbE, &IGbE::tick> tickEvent; 130 131 132 void rxStateMachine(); 133 void txStateMachine(); 134 void txWire(); 135 136 /** Write an interrupt into the interrupt pending register and check mask 137 * and interrupt limit timer before sending interrupt to CPU 138 * @param t the type of interrupt we are posting 139 * @param now should we ignore the interrupt limiting timer 140 */ 141 void postInterrupt(iGbReg::IntTypes t, bool now = false); 142 143 /** Check and see if changes to the mask register have caused an interrupt 144 * to need to be sent or perhaps removed an interrupt cause. 145 */ 146 void chkInterrupt(); 147 148 /** Send an interrupt to the cpu 149 */ 150 void delayIntEvent(); 151 void cpuPostInt(); 152 // Event to moderate interrupts 153 EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent; 154 155 /** Clear the interupt line to the cpu 156 */ 157 void cpuClearInt(); 158 159 Tick intClock() { return Clock::Int::ns * 1024; } 160 161 /** This function is used to restart the clock so it can handle things like 162 * draining and resume in one place. */ 163 void restartClock(); 164 165 /** Check if all the draining things that need to occur have occured and 166 * handle the drain event if so. 167 */ 168 void checkDrain(); 169 170 template<class T> 171 class DescCache 172 { 173 protected: 174 virtual Addr descBase() const = 0; 175 virtual long descHead() const = 0; 176 virtual long descTail() const = 0; 177 virtual long descLen() const = 0; 178 virtual void updateHead(long h) = 0; 179 virtual void enableSm() = 0; 180 virtual void intAfterWb() const {} 181 virtual void fetchAfterWb() = 0; 182 183 std::deque<T*> usedCache; 184 std::deque<T*> unusedCache; 185 186 T *fetchBuf; 187 T *wbBuf; 188 189 // Pointer to the device we cache for 190 IGbE *igbe; 191 192 // Name of this descriptor cache 193 std::string _name; 194 195 // How far we've cached 196 int cachePnt; 197 198 // The size of the descriptor cache 199 int size; 200 201 // How many descriptors we are currently fetching 202 int curFetching; 203 204 // How many descriptors we are currently writing back 205 int wbOut; 206 207 // if the we wrote back to the end of the descriptor ring and are going 208 // to have to wrap and write more 209 bool moreToWb; 210 211 // What the alignment is of the next descriptor writeback 212 Addr wbAlignment; 213 214 /** The packet that is currently being dmad to memory if any 215 */ 216 EthPacketPtr pktPtr; 217 218 public: 219 DescCache(IGbE *i, const std::string n, int s) 220 : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), wbOut(0), 221 pktPtr(NULL), fetchEvent(this), wbEvent(this) 222 { 223 fetchBuf = new T[size]; 224 wbBuf = new T[size]; 225 } 226 227 virtual ~DescCache() 228 { 229 reset(); 230 } 231 232 std::string name() { return _name; } 233 234 /** If the address/len/head change when we've got descriptors that are 235 * dirty that is very bad. This function checks that we don't and if we 236 * do panics. 237 */ 238 void areaChanged() 239 { 240 if (usedCache.size() > 0 || curFetching || wbOut) 241 panic("Descriptor Address, Length or Head changed. Bad\n"); 242 reset(); 243 244 } 245 246 void writeback(Addr aMask) 247 { 248 int curHead = descHead(); 249 int max_to_wb = usedCache.size(); 250 251 DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: " 252 "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n", 253 curHead, descTail(), descLen(), cachePnt, max_to_wb, 254 descLeft()); 255 256 // Check if this writeback is less restrictive that the previous 257 // and if so setup another one immediately following it 258 if (wbOut && (aMask < wbAlignment)) { 259 moreToWb = true; 260 wbAlignment = aMask; 261 DPRINTF(EthernetDesc, "Writing back already in process, returning\n"); 262 return; 263 } 264 265 266 moreToWb = false; 267 wbAlignment = aMask; 268 269 if (max_to_wb + curHead >= descLen()) { 270 max_to_wb = descLen() - curHead; 271 moreToWb = true; 272 // this is by definition aligned correctly 273 } else if (aMask != 0) { 274 // align the wb point to the mask 275 max_to_wb = max_to_wb & ~aMask; 276 } 277 278 DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb); 279 280 if (max_to_wb <= 0 || wbOut) 281 return; 282 283 wbOut = max_to_wb; 284 285 for (int x = 0; x < wbOut; x++) 286 memcpy(&wbBuf[x], usedCache[x], sizeof(T)); 287 288 289 assert(wbOut); 290 igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)), 291 wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf); 292 } 293 294 /** Fetch a chunk of descriptors into the descriptor cache. 295 * Calls fetchComplete when the memory system returns the data 296 */ 297 void fetchDescriptors() 298 { 299 size_t max_to_fetch; 300 301 if (descTail() >= cachePnt) 302 max_to_fetch = descTail() - cachePnt; 303 else 304 max_to_fetch = descLen() - cachePnt; 305 306 max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() - 307 unusedCache.size())); 308 309 DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: " 310 "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n", 311 descHead(), descTail(), descLen(), cachePnt, 312 max_to_fetch, descLeft()); 313 314 // Nothing to do 315 if (max_to_fetch == 0 || curFetching) 316 return; 317 318 // So we don't have two descriptor fetches going on at once 319 curFetching = max_to_fetch; 320 321 DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n", 322 descBase() + cachePnt * sizeof(T), 323 igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)), 324 curFetching * sizeof(T)); 325 326 assert(curFetching); 327 igbe->dmaRead(igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)), 328 curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf); 329 } 330 331 332 /** Called by event when dma to read descriptors is completed 333 */ 334 void fetchComplete() 335 { 336 T *newDesc; 337 for (int x = 0; x < curFetching; x++) { 338 newDesc = new T; 339 memcpy(newDesc, &fetchBuf[x], sizeof(T)); 340 unusedCache.push_back(newDesc); 341 } 342 343#ifndef NDEBUG 344 int oldCp = cachePnt; 345#endif 346 347 cachePnt += curFetching; 348 assert(cachePnt <= descLen()); 349 if (cachePnt == descLen()) 350 cachePnt = 0; 351 352 curFetching = 0; 353 354 DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n", 355 oldCp, cachePnt); 356 357 enableSm(); 358 igbe->checkDrain(); 359 } 360 361 EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent; 362 363 /** Called by event when dma to writeback descriptors is completed 364 */ 365 void wbComplete() 366 { 367 368 long curHead = descHead(); 369#ifndef NDEBUG 370 long oldHead = curHead; 371#endif 372 for (int x = 0; x < wbOut; x++) { 373 assert(usedCache.size()); 374 delete usedCache[0]; 375 usedCache.pop_front(); 376 }; 377 378 curHead += wbOut; 379 wbOut = 0; 380 381 if (curHead >= descLen()) 382 curHead -= descLen(); 383 384 // Update the head 385 updateHead(curHead); 386 387 DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n", 388 oldHead, curHead); 389 390 // If we still have more to wb, call wb now 391 bool oldMoreToWb = moreToWb; 392 if (moreToWb) { 393 DPRINTF(EthernetDesc, "Writeback has more todo\n"); 394 writeback(wbAlignment); 395 } 396 397 intAfterWb(); 398 if (!oldMoreToWb) { 399 igbe->checkDrain(); 400 } 401 fetchAfterWb(); 402 } 403 404 405 EventWrapper<DescCache, &DescCache::wbComplete> wbEvent; 406 407 /* Return the number of descriptors left in the ring, so the device has 408 * a way to figure out if it needs to interrupt. 409 */ 410 int descLeft() const 411 { 412 int left = unusedCache.size(); 413 if (cachePnt - descTail() >= 0) 414 left += (cachePnt - descTail()); 415 else 416 left += (descTail() - cachePnt); 417 418 return left; 419 } 420 421 /* Return the number of descriptors used and not written back. 422 */ 423 int descUsed() const { return usedCache.size(); } 424 425 /* Return the number of cache unused descriptors we have. */ 426 int descUnused() const {return unusedCache.size(); } 427 428 /* Get into a state where the descriptor address/head/etc colud be 429 * changed */ 430 void reset() 431 { 432 DPRINTF(EthernetDesc, "Reseting descriptor cache\n"); 433 for (int x = 0; x < usedCache.size(); x++) 434 delete usedCache[x]; 435 for (int x = 0; x < unusedCache.size(); x++) 436 delete unusedCache[x]; 437 438 usedCache.clear(); 439 unusedCache.clear(); 440 441 cachePnt = 0; 442 443 } 444 445 virtual void serialize(std::ostream &os) 446 { 447 SERIALIZE_SCALAR(cachePnt); 448 SERIALIZE_SCALAR(curFetching); 449 SERIALIZE_SCALAR(wbOut); 450 SERIALIZE_SCALAR(moreToWb); 451 SERIALIZE_SCALAR(wbAlignment); 452 453 int usedCacheSize = usedCache.size(); 454 SERIALIZE_SCALAR(usedCacheSize); 455 for(int x = 0; x < usedCacheSize; x++) { 456 arrayParamOut(os, csprintf("usedCache_%d", x), 457 (uint8_t*)usedCache[x],sizeof(T)); 458 } 459 460 int unusedCacheSize = unusedCache.size(); 461 SERIALIZE_SCALAR(unusedCacheSize); 462 for(int x = 0; x < unusedCacheSize; x++) { 463 arrayParamOut(os, csprintf("unusedCache_%d", x), 464 (uint8_t*)unusedCache[x],sizeof(T)); 465 } 466 } 467 468 virtual void unserialize(Checkpoint *cp, const std::string §ion) 469 { 470 UNSERIALIZE_SCALAR(cachePnt); 471 UNSERIALIZE_SCALAR(curFetching); 472 UNSERIALIZE_SCALAR(wbOut); 473 UNSERIALIZE_SCALAR(moreToWb); 474 UNSERIALIZE_SCALAR(wbAlignment); 475 476 int usedCacheSize; 477 UNSERIALIZE_SCALAR(usedCacheSize); 478 T *temp; 479 for(int x = 0; x < usedCacheSize; x++) { 480 temp = new T; 481 arrayParamIn(cp, section, csprintf("usedCache_%d", x), 482 (uint8_t*)temp,sizeof(T)); 483 usedCache.push_back(temp); 484 } 485 486 int unusedCacheSize; 487 UNSERIALIZE_SCALAR(unusedCacheSize); 488 for(int x = 0; x < unusedCacheSize; x++) { 489 temp = new T; 490 arrayParamIn(cp, section, csprintf("unusedCache_%d", x), 491 (uint8_t*)temp,sizeof(T)); 492 unusedCache.push_back(temp); 493 } 494 } 495 virtual bool hasOutstandingEvents() { 496 return wbEvent.scheduled() || fetchEvent.scheduled(); 497 } 498 499 }; 500 501 502 class RxDescCache : public DescCache<iGbReg::RxDesc> 503 { 504 protected: 505 virtual Addr descBase() const { return igbe->regs.rdba(); } 506 virtual long descHead() const { return igbe->regs.rdh(); } 507 virtual long descLen() const { return igbe->regs.rdlen() >> 4; } 508 virtual long descTail() const { return igbe->regs.rdt(); } 509 virtual void updateHead(long h) { igbe->regs.rdh(h); } 510 virtual void enableSm(); 511 virtual void fetchAfterWb() { 512 if (!igbe->rxTick && igbe->getState() == SimObject::Running) 513 fetchDescriptors(); 514 } 515 516 bool pktDone; 517 518 public: 519 RxDescCache(IGbE *i, std::string n, int s); 520 521 /** Write the given packet into the buffer(s) pointed to by the 522 * descriptor and update the book keeping. Should only be called when 523 * there are no dma's pending. 524 * @param packet ethernet packet to write 525 * @return if the packet could be written (there was a free descriptor) 526 */ 527 bool writePacket(EthPacketPtr packet); 528 /** Called by event when dma to write packet is completed 529 */ 530 void pktComplete(); 531 532 /** Check if the dma on the packet has completed. 533 */ 534 535 bool packetDone(); 536 537 EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent; 538 539 virtual bool hasOutstandingEvents(); 540 541 virtual void serialize(std::ostream &os); 542 virtual void unserialize(Checkpoint *cp, const std::string §ion); 543 }; 544 friend class RxDescCache; 545 546 RxDescCache rxDescCache; 547 548 class TxDescCache : public DescCache<iGbReg::TxDesc> 549 { 550 protected: 551 virtual Addr descBase() const { return igbe->regs.tdba(); } 552 virtual long descHead() const { return igbe->regs.tdh(); } 553 virtual long descTail() const { return igbe->regs.tdt(); } 554 virtual long descLen() const { return igbe->regs.tdlen() >> 4; } 555 virtual void updateHead(long h) { igbe->regs.tdh(h); } 556 virtual void enableSm(); 557 virtual void intAfterWb() const { 558 igbe->postInterrupt(iGbReg::IT_TXDW); 559 } 560 virtual void fetchAfterWb() { 561 if (!igbe->txTick && igbe->getState() == SimObject::Running) 562 fetchDescriptors(); 563 } 564 565 bool pktDone; 566 bool isTcp; 567 bool pktWaiting; 568 569 public: 570 TxDescCache(IGbE *i, std::string n, int s); 571 572 /** Tell the cache to DMA a packet from main memory into its buffer and 573 * return the size the of the packet to reserve space in tx fifo. 574 * @return size of the packet 575 */ 576 int getPacketSize(); 577 void getPacketData(EthPacketPtr p); 578 579 /** Ask if the packet has been transfered so the state machine can give 580 * it to the fifo. 581 * @return packet available in descriptor cache 582 */ 583 bool packetAvailable(); 584 585 /** Ask if we are still waiting for the packet to be transfered. 586 * @return packet still in transit. 587 */ 588 bool packetWaiting() { return pktWaiting; } 589 590 /** Called by event when dma to write packet is completed 591 */ 592 void pktComplete(); 593 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 594 595 virtual bool hasOutstandingEvents(); 596 597 virtual void serialize(std::ostream &os); 598 virtual void unserialize(Checkpoint *cp, const std::string §ion); 599 600 }; 601 friend class TxDescCache; 602 603 TxDescCache txDescCache; 604 605 public: 606 typedef IGbEParams Params; 607 const Params * 608 params() const 609 { 610 return dynamic_cast<const Params *>(_params); 611 } 612 IGbE(const Params *params); 613 ~IGbE() {} 614 615 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 616 617 Tick clock; 618 inline Tick cycles(int numCycles) const { return numCycles * clock; } 619 620 virtual Tick read(PacketPtr pkt); 621 virtual Tick write(PacketPtr pkt); 622 623 virtual Tick writeConfig(PacketPtr pkt); 624 625 bool ethRxPkt(EthPacketPtr packet); 626 void ethTxDone(); 627 628 virtual void serialize(std::ostream &os); 629 virtual void unserialize(Checkpoint *cp, const std::string §ion); 630 virtual unsigned int drain(Event *de); 631 virtual void resume(); 632 633}; 634 635class IGbEInt : public EtherInt 636{ 637 private: 638 IGbE *dev; 639 640 public: 641 IGbEInt(const std::string &name, IGbE *d) 642 : EtherInt(name), dev(d) 643 { } 644 645 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); } 646 virtual void sendDone() { dev->ethTxDone(); } 647}; 648 649 650 651 652 653#endif //__DEV_I8254XGBE_HH__ 654 655