i8254xGBe.hh revision 3116 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 */
34
35#ifndef __DEV_I8254XGBE_HH__
36#define __DEV_I8254XGBE_HH__
37
38#include "base/inet.hh"
39#include "base/statistics.hh"
40#include "dev/etherint.hh"
41#include "dev/etherpkt.hh"
42#include "dev/pcidev.hh"
43#include "dev/pktfifo.hh"
44#include "sim/eventq.hh"
45
46class IGbEInt;
47
48class IGbE : public PciDev
49{
50  private:
51    IGbEInt *etherInt;
52
53  public:
54    struct Params : public PciDev::Params
55    {
56        ;
57    };
58
59    IGbE(Params *params);
60    ~IGbE() {;}
61
62    virtual Tick read(Packet *pkt);
63    virtual Tick write(Packet *pkt);
64
65    virtual Tick writeConfig(Packet *pkt);
66
67    bool ethRxPkt(EthPacketPtr packet);
68    void ethTxDone();
69
70    void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
71
72    const Params *params() const {return (const Params *)_params; }
73
74    virtual void serialize(std::ostream &os);
75    virtual void unserialize(Checkpoint *cp, const std::string &section);
76
77
78};
79
80class IGbEInt : public EtherInt
81{
82  private:
83    IGbE *dev;
84
85  public:
86    IGbEInt(const std::string &name, IGbE *d)
87        : EtherInt(name), dev(d)
88        { dev->setEthInt(this); }
89
90    virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
91    virtual void sendDone() { dev->ethTxDone(); }
92};
93
94
95
96
97
98#endif //__DEV_I8254XGBE_HH__
99
100