i8254xGBe.hh revision 10905 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 */
34
35#ifndef __DEV_I8254XGBE_HH__
36#define __DEV_I8254XGBE_HH__
37
38#include <deque>
39#include <string>
40
41#include "base/cp_annotate.hh"
42#include "base/inet.hh"
43#include "debug/EthernetDesc.hh"
44#include "debug/EthernetIntr.hh"
45#include "dev/etherdevice.hh"
46#include "dev/etherint.hh"
47#include "dev/etherpkt.hh"
48#include "dev/i8254xGBe_defs.hh"
49#include "dev/pcidev.hh"
50#include "dev/pktfifo.hh"
51#include "params/IGbE.hh"
52#include "sim/eventq.hh"
53
54class IGbEInt;
55
56class IGbE : public EtherDevice
57{
58  private:
59    IGbEInt *etherInt;
60    CPA *cpa;
61
62    // device registers
63    iGbReg::Regs regs;
64
65    // eeprom data, status and control bits
66    int eeOpBits, eeAddrBits, eeDataBits;
67    uint8_t eeOpcode, eeAddr;
68    uint16_t flash[iGbReg::EEPROM_SIZE];
69
70    // The drain event if we have one
71    DrainManager *drainManager;
72
73    // packet fifos
74    PacketFifo rxFifo;
75    PacketFifo txFifo;
76
77    // Packet that we are currently putting into the txFifo
78    EthPacketPtr txPacket;
79
80    // Should to Rx/Tx State machine tick?
81    bool rxTick;
82    bool txTick;
83    bool txFifoTick;
84
85    bool rxDmaPacket;
86
87    // Number of bytes copied from current RX packet
88    unsigned pktOffset;
89
90    // Delays in managaging descriptors
91    Tick fetchDelay, wbDelay;
92    Tick fetchCompDelay, wbCompDelay;
93    Tick rxWriteDelay, txReadDelay;
94
95    // Event and function to deal with RDTR timer expiring
96    void rdtrProcess() {
97        rxDescCache.writeback(0);
98        DPRINTF(EthernetIntr,
99                "Posting RXT interrupt because RDTR timer expired\n");
100        postInterrupt(iGbReg::IT_RXT);
101    }
102
103    //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
104    EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
105
106    // Event and function to deal with RADV timer expiring
107    void radvProcess() {
108        rxDescCache.writeback(0);
109        DPRINTF(EthernetIntr,
110                "Posting RXT interrupt because RADV timer expired\n");
111        postInterrupt(iGbReg::IT_RXT);
112    }
113
114    //friend class EventWrapper<IGbE, &IGbE::radvProcess>;
115    EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
116
117    // Event and function to deal with TADV timer expiring
118    void tadvProcess() {
119        txDescCache.writeback(0);
120        DPRINTF(EthernetIntr,
121                "Posting TXDW interrupt because TADV timer expired\n");
122        postInterrupt(iGbReg::IT_TXDW);
123    }
124
125    //friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
126    EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
127
128    // Event and function to deal with TIDV timer expiring
129    void tidvProcess() {
130        txDescCache.writeback(0);
131        DPRINTF(EthernetIntr,
132                "Posting TXDW interrupt because TIDV timer expired\n");
133        postInterrupt(iGbReg::IT_TXDW);
134    }
135    //friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
136    EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
137
138    // Main event to tick the device
139    void tick();
140    //friend class EventWrapper<IGbE, &IGbE::tick>;
141    EventWrapper<IGbE, &IGbE::tick> tickEvent;
142
143
144    uint64_t macAddr;
145
146    void rxStateMachine();
147    void txStateMachine();
148    void txWire();
149
150    /** Write an interrupt into the interrupt pending register and check mask
151     * and interrupt limit timer before sending interrupt to CPU
152     * @param t the type of interrupt we are posting
153     * @param now should we ignore the interrupt limiting timer
154     */
155    void postInterrupt(iGbReg::IntTypes t, bool now = false);
156
157    /** Check and see if changes to the mask register have caused an interrupt
158     * to need to be sent or perhaps removed an interrupt cause.
159     */
160    void chkInterrupt();
161
162    /** Send an interrupt to the cpu
163     */
164    void delayIntEvent();
165    void cpuPostInt();
166    // Event to moderate interrupts
167    EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
168
169    /** Clear the interupt line to the cpu
170     */
171    void cpuClearInt();
172
173    Tick intClock() { return SimClock::Int::ns * 1024; }
174
175    /** This function is used to restart the clock so it can handle things like
176     * draining and resume in one place. */
177    void restartClock();
178
179    /** Check if all the draining things that need to occur have occured and
180     * handle the drain event if so.
181     */
182    void checkDrain();
183
184    void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) {
185        if (cpa)
186            cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st);
187    }
188
189    void anQ(std::string sm, std::string q) {
190        if (cpa)
191            cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
192    }
193
194    void anDq(std::string sm, std::string q) {
195        if (cpa)
196            cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
197    }
198
199    void anPq(std::string sm, std::string q, int num = 1) {
200        if (cpa)
201            cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
202    }
203
204    void anRq(std::string sm, std::string q, int num = 1) {
205        if (cpa)
206            cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
207    }
208
209    void anWe(std::string sm, std::string q) {
210        if (cpa)
211            cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
212    }
213
214    void anWf(std::string sm, std::string q) {
215        if (cpa)
216            cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
217    }
218
219
220    template<class T>
221    class DescCache : public Serializable
222    {
223      protected:
224        virtual Addr descBase() const = 0;
225        virtual long descHead() const = 0;
226        virtual long descTail() const = 0;
227        virtual long descLen() const = 0;
228        virtual void updateHead(long h) = 0;
229        virtual void enableSm() = 0;
230        virtual void actionAfterWb() {}
231        virtual void fetchAfterWb() = 0;
232
233        typedef std::deque<T *> CacheType;
234        CacheType usedCache;
235        CacheType unusedCache;
236
237        T *fetchBuf;
238        T *wbBuf;
239
240        // Pointer to the device we cache for
241        IGbE *igbe;
242
243        // Name of this  descriptor cache
244        std::string _name;
245
246        // How far we've cached
247        int cachePnt;
248
249        // The size of the descriptor cache
250        int size;
251
252        // How many descriptors we are currently fetching
253        int curFetching;
254
255        // How many descriptors we are currently writing back
256        int wbOut;
257
258        // if the we wrote back to the end of the descriptor ring and are going
259        // to have to wrap and write more
260        bool moreToWb;
261
262        // What the alignment is of the next descriptor writeback
263        Addr wbAlignment;
264
265        /** The packet that is currently being dmad to memory if any */
266        EthPacketPtr pktPtr;
267
268        /** Shortcut for DMA address translation */
269        Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); }
270
271      public:
272        /** Annotate sm*/
273        std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ,
274            annUsedDescQ, annUnusedCacheQ, annDescQ;
275
276        DescCache(IGbE *i, const std::string n, int s);
277        virtual ~DescCache();
278
279        std::string name() { return _name; }
280
281        /** If the address/len/head change when we've got descriptors that are
282         * dirty that is very bad. This function checks that we don't and if we
283         * do panics.
284         */
285        void areaChanged();
286
287        void writeback(Addr aMask);
288        void writeback1();
289        EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
290
291        /** Fetch a chunk of descriptors into the descriptor cache.
292         * Calls fetchComplete when the memory system returns the data
293         */
294        void fetchDescriptors();
295        void fetchDescriptors1();
296        EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
297
298        /** Called by event when dma to read descriptors is completed
299         */
300        void fetchComplete();
301        EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
302
303        /** Called by event when dma to writeback descriptors is completed
304         */
305        void wbComplete();
306        EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
307
308        /* Return the number of descriptors left in the ring, so the device has
309         * a way to figure out if it needs to interrupt.
310         */
311        unsigned
312        descLeft() const
313        {
314            unsigned left = unusedCache.size();
315            if (cachePnt > descTail())
316                left += (descLen() - cachePnt + descTail());
317            else
318                left += (descTail() - cachePnt);
319
320            return left;
321        }
322
323        /* Return the number of descriptors used and not written back.
324         */
325        unsigned descUsed() const { return usedCache.size(); }
326
327        /* Return the number of cache unused descriptors we have. */
328        unsigned descUnused() const { return unusedCache.size(); }
329
330        /* Get into a state where the descriptor address/head/etc colud be
331         * changed */
332        void reset();
333
334
335        void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
336        void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
337
338        virtual bool hasOutstandingEvents() {
339            return wbEvent.scheduled() || fetchEvent.scheduled();
340        }
341
342    };
343
344
345    class RxDescCache : public DescCache<iGbReg::RxDesc>
346    {
347      protected:
348        virtual Addr descBase() const { return igbe->regs.rdba(); }
349        virtual long descHead() const { return igbe->regs.rdh(); }
350        virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
351        virtual long descTail() const { return igbe->regs.rdt(); }
352        virtual void updateHead(long h) { igbe->regs.rdh(h); }
353        virtual void enableSm();
354        virtual void fetchAfterWb() {
355            if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running)
356                fetchDescriptors();
357        }
358
359        bool pktDone;
360
361        /** Variable to head with header/data completion events */
362        int splitCount;
363
364        /** Bytes of packet that have been copied, so we know when to
365            set EOP */
366        unsigned bytesCopied;
367
368      public:
369        RxDescCache(IGbE *i, std::string n, int s);
370
371        /** Write the given packet into the buffer(s) pointed to by the
372         * descriptor and update the book keeping. Should only be called when
373         * there are no dma's pending.
374         * @param packet ethernet packet to write
375         * @param pkt_offset bytes already copied from the packet to memory
376         * @return pkt_offset + number of bytes copied during this call
377         */
378        int writePacket(EthPacketPtr packet, int pkt_offset);
379
380        /** Called by event when dma to write packet is completed
381         */
382        void pktComplete();
383
384        /** Check if the dma on the packet has completed and RX state machine
385         * can continue
386         */
387        bool packetDone();
388
389        EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
390
391        // Event to handle issuing header and data write at the same time
392        // and only callking pktComplete() when both are completed
393        void pktSplitDone();
394        EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
395        EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
396
397        virtual bool hasOutstandingEvents();
398
399        void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
400        void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
401    };
402    friend class RxDescCache;
403
404    RxDescCache rxDescCache;
405
406    class TxDescCache  : public DescCache<iGbReg::TxDesc>
407    {
408      protected:
409        virtual Addr descBase() const { return igbe->regs.tdba(); }
410        virtual long descHead() const { return igbe->regs.tdh(); }
411        virtual long descTail() const { return igbe->regs.tdt(); }
412        virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
413        virtual void updateHead(long h) { igbe->regs.tdh(h); }
414        virtual void enableSm();
415        virtual void actionAfterWb();
416        virtual void fetchAfterWb() {
417            if (!igbe->txTick && igbe->getDrainState() == Drainable::Running)
418                fetchDescriptors();
419        }
420
421
422
423        bool pktDone;
424        bool isTcp;
425        bool pktWaiting;
426        bool pktMultiDesc;
427        Addr completionAddress;
428        bool completionEnabled;
429        uint32_t descEnd;
430
431
432        // tso variables
433        bool useTso;
434        Addr tsoHeaderLen;
435        Addr tsoMss;
436        Addr tsoTotalLen;
437        Addr tsoUsedLen;
438        Addr tsoPrevSeq;
439        Addr tsoPktPayloadBytes;
440        bool tsoLoadedHeader;
441        bool tsoPktHasHeader;
442        uint8_t tsoHeader[256];
443        Addr tsoDescBytesUsed;
444        Addr tsoCopyBytes;
445        int tsoPkts;
446
447      public:
448        TxDescCache(IGbE *i, std::string n, int s);
449
450        /** Tell the cache to DMA a packet from main memory into its buffer and
451         * return the size the of the packet to reserve space in tx fifo.
452         * @return size of the packet
453         */
454        unsigned getPacketSize(EthPacketPtr p);
455        void getPacketData(EthPacketPtr p);
456        void processContextDesc();
457
458        /** Return the number of dsecriptors in a cache block for threshold
459         * operations.
460         */
461        unsigned
462        descInBlock(unsigned num_desc)
463        {
464            return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
465        }
466
467        /** Ask if the packet has been transfered so the state machine can give
468         * it to the fifo.
469         * @return packet available in descriptor cache
470         */
471        bool packetAvailable();
472
473        /** Ask if we are still waiting for the packet to be transfered.
474         * @return packet still in transit.
475         */
476        bool packetWaiting() { return pktWaiting; }
477
478        /** Ask if this packet is composed of multiple descriptors
479         * so even if we've got data, we need to wait for more before
480         * we can send it out.
481         * @return packet can't be sent out because it's a multi-descriptor
482         * packet
483         */
484        bool packetMultiDesc() { return pktMultiDesc;}
485
486        /** Called by event when dma to write packet is completed
487         */
488        void pktComplete();
489        EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
490
491        void headerComplete();
492        EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent;
493
494
495        void completionWriteback(Addr a, bool enabled) {
496            DPRINTF(EthernetDesc,
497                    "Completion writeback Addr: %#x enabled: %d\n",
498                    a, enabled);
499            completionAddress = a;
500            completionEnabled = enabled;
501        }
502
503        virtual bool hasOutstandingEvents();
504
505        void nullCallback() {
506            DPRINTF(EthernetDesc, "Completion writeback complete\n");
507        }
508        EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
509
510        void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
511        void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
512    };
513
514    friend class TxDescCache;
515
516    TxDescCache txDescCache;
517
518  public:
519    typedef IGbEParams Params;
520    const Params *
521    params() const {
522        return dynamic_cast<const Params *>(_params);
523    }
524
525    IGbE(const Params *params);
526    ~IGbE();
527    virtual void init();
528
529    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
530
531    Tick lastInterrupt;
532
533    virtual Tick read(PacketPtr pkt);
534    virtual Tick write(PacketPtr pkt);
535
536    virtual Tick writeConfig(PacketPtr pkt);
537
538    bool ethRxPkt(EthPacketPtr packet);
539    void ethTxDone();
540
541    void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
542    void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
543
544    unsigned int drain(DrainManager *dm);
545    void drainResume();
546
547};
548
549class IGbEInt : public EtherInt
550{
551  private:
552    IGbE *dev;
553
554  public:
555    IGbEInt(const std::string &name, IGbE *d)
556        : EtherInt(name), dev(d)
557    { }
558
559    virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
560    virtual void sendDone() { dev->ethTxDone(); }
561};
562
563#endif //__DEV_I8254XGBE_HH__
564