i8254xGBe.hh revision 10702
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/* @file 32 * Device model for Intel's 8254x line of gigabit ethernet controllers. 33 */ 34 35#ifndef __DEV_I8254XGBE_HH__ 36#define __DEV_I8254XGBE_HH__ 37 38#include <deque> 39#include <string> 40 41#include "base/cp_annotate.hh" 42#include "base/inet.hh" 43#include "debug/EthernetDesc.hh" 44#include "debug/EthernetIntr.hh" 45#include "dev/etherdevice.hh" 46#include "dev/etherint.hh" 47#include "dev/etherpkt.hh" 48#include "dev/i8254xGBe_defs.hh" 49#include "dev/pcidev.hh" 50#include "dev/pktfifo.hh" 51#include "params/IGbE.hh" 52#include "sim/eventq.hh" 53 54class IGbEInt; 55 56class IGbE : public EtherDevice 57{ 58 private: 59 IGbEInt *etherInt; 60 CPA *cpa; 61 62 // device registers 63 iGbReg::Regs regs; 64 65 // eeprom data, status and control bits 66 int eeOpBits, eeAddrBits, eeDataBits; 67 uint8_t eeOpcode, eeAddr; 68 uint16_t flash[iGbReg::EEPROM_SIZE]; 69 70 // The drain event if we have one 71 DrainManager *drainManager; 72 73 // packet fifos 74 PacketFifo rxFifo; 75 PacketFifo txFifo; 76 77 // Packet that we are currently putting into the txFifo 78 EthPacketPtr txPacket; 79 80 // Should to Rx/Tx State machine tick? 81 bool rxTick; 82 bool txTick; 83 bool txFifoTick; 84 85 bool rxDmaPacket; 86 87 // Number of bytes copied from current RX packet 88 unsigned pktOffset; 89 90 // Delays in managaging descriptors 91 Tick fetchDelay, wbDelay; 92 Tick fetchCompDelay, wbCompDelay; 93 Tick rxWriteDelay, txReadDelay; 94 95 // Event and function to deal with RDTR timer expiring 96 void rdtrProcess() { 97 rxDescCache.writeback(0); 98 DPRINTF(EthernetIntr, 99 "Posting RXT interrupt because RDTR timer expired\n"); 100 postInterrupt(iGbReg::IT_RXT); 101 } 102 103 //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>; 104 EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent; 105 106 // Event and function to deal with RADV timer expiring 107 void radvProcess() { 108 rxDescCache.writeback(0); 109 DPRINTF(EthernetIntr, 110 "Posting RXT interrupt because RADV timer expired\n"); 111 postInterrupt(iGbReg::IT_RXT); 112 } 113 114 //friend class EventWrapper<IGbE, &IGbE::radvProcess>; 115 EventWrapper<IGbE, &IGbE::radvProcess> radvEvent; 116 117 // Event and function to deal with TADV timer expiring 118 void tadvProcess() { 119 txDescCache.writeback(0); 120 DPRINTF(EthernetIntr, 121 "Posting TXDW interrupt because TADV timer expired\n"); 122 postInterrupt(iGbReg::IT_TXDW); 123 } 124 125 //friend class EventWrapper<IGbE, &IGbE::tadvProcess>; 126 EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent; 127 128 // Event and function to deal with TIDV timer expiring 129 void tidvProcess() { 130 txDescCache.writeback(0); 131 DPRINTF(EthernetIntr, 132 "Posting TXDW interrupt because TIDV timer expired\n"); 133 postInterrupt(iGbReg::IT_TXDW); 134 } 135 //friend class EventWrapper<IGbE, &IGbE::tidvProcess>; 136 EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent; 137 138 // Main event to tick the device 139 void tick(); 140 //friend class EventWrapper<IGbE, &IGbE::tick>; 141 EventWrapper<IGbE, &IGbE::tick> tickEvent; 142 143 144 uint64_t macAddr; 145 146 void rxStateMachine(); 147 void txStateMachine(); 148 void txWire(); 149 150 /** Write an interrupt into the interrupt pending register and check mask 151 * and interrupt limit timer before sending interrupt to CPU 152 * @param t the type of interrupt we are posting 153 * @param now should we ignore the interrupt limiting timer 154 */ 155 void postInterrupt(iGbReg::IntTypes t, bool now = false); 156 157 /** Check and see if changes to the mask register have caused an interrupt 158 * to need to be sent or perhaps removed an interrupt cause. 159 */ 160 void chkInterrupt(); 161 162 /** Send an interrupt to the cpu 163 */ 164 void delayIntEvent(); 165 void cpuPostInt(); 166 // Event to moderate interrupts 167 EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent; 168 169 /** Clear the interupt line to the cpu 170 */ 171 void cpuClearInt(); 172 173 Tick intClock() { return SimClock::Int::ns * 1024; } 174 175 /** This function is used to restart the clock so it can handle things like 176 * draining and resume in one place. */ 177 void restartClock(); 178 179 /** Check if all the draining things that need to occur have occured and 180 * handle the drain event if so. 181 */ 182 void checkDrain(); 183 184 void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) { 185 if (cpa) 186 cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st); 187 } 188 189 void anQ(std::string sm, std::string q) { 190 if (cpa) 191 cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 192 } 193 194 void anDq(std::string sm, std::string q) { 195 if (cpa) 196 cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 197 } 198 199 void anPq(std::string sm, std::string q, int num = 1) { 200 if (cpa) 201 cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 202 } 203 204 void anRq(std::string sm, std::string q, int num = 1) { 205 if (cpa) 206 cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 207 } 208 209 void anWe(std::string sm, std::string q) { 210 if (cpa) 211 cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 212 } 213 214 void anWf(std::string sm, std::string q) { 215 if (cpa) 216 cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 217 } 218 219 220 template<class T> 221 class DescCache 222 { 223 protected: 224 virtual Addr descBase() const = 0; 225 virtual long descHead() const = 0; 226 virtual long descTail() const = 0; 227 virtual long descLen() const = 0; 228 virtual void updateHead(long h) = 0; 229 virtual void enableSm() = 0; 230 virtual void actionAfterWb() {} 231 virtual void fetchAfterWb() = 0; 232 233 typedef std::deque<T *> CacheType; 234 CacheType usedCache; 235 CacheType unusedCache; 236 237 T *fetchBuf; 238 T *wbBuf; 239 240 // Pointer to the device we cache for 241 IGbE *igbe; 242 243 // Name of this descriptor cache 244 std::string _name; 245 246 // How far we've cached 247 int cachePnt; 248 249 // The size of the descriptor cache 250 int size; 251 252 // How many descriptors we are currently fetching 253 int curFetching; 254 255 // How many descriptors we are currently writing back 256 int wbOut; 257 258 // if the we wrote back to the end of the descriptor ring and are going 259 // to have to wrap and write more 260 bool moreToWb; 261 262 // What the alignment is of the next descriptor writeback 263 Addr wbAlignment; 264 265 /** The packet that is currently being dmad to memory if any */ 266 EthPacketPtr pktPtr; 267 268 /** Shortcut for DMA address translation */ 269 Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); } 270 271 public: 272 /** Annotate sm*/ 273 std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ, 274 annUsedDescQ, annUnusedCacheQ, annDescQ; 275 276 DescCache(IGbE *i, const std::string n, int s); 277 virtual ~DescCache(); 278 279 std::string name() { return _name; } 280 281 /** If the address/len/head change when we've got descriptors that are 282 * dirty that is very bad. This function checks that we don't and if we 283 * do panics. 284 */ 285 void areaChanged(); 286 287 void writeback(Addr aMask); 288 void writeback1(); 289 EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent; 290 291 /** Fetch a chunk of descriptors into the descriptor cache. 292 * Calls fetchComplete when the memory system returns the data 293 */ 294 void fetchDescriptors(); 295 void fetchDescriptors1(); 296 EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent; 297 298 /** Called by event when dma to read descriptors is completed 299 */ 300 void fetchComplete(); 301 EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent; 302 303 /** Called by event when dma to writeback descriptors is completed 304 */ 305 void wbComplete(); 306 EventWrapper<DescCache, &DescCache::wbComplete> wbEvent; 307 308 /* Return the number of descriptors left in the ring, so the device has 309 * a way to figure out if it needs to interrupt. 310 */ 311 unsigned 312 descLeft() const 313 { 314 unsigned left = unusedCache.size(); 315 if (cachePnt > descTail()) 316 left += (descLen() - cachePnt + descTail()); 317 else 318 left += (descTail() - cachePnt); 319 320 return left; 321 } 322 323 /* Return the number of descriptors used and not written back. 324 */ 325 unsigned descUsed() const { return usedCache.size(); } 326 327 /* Return the number of cache unused descriptors we have. */ 328 unsigned descUnused() const { return unusedCache.size(); } 329 330 /* Get into a state where the descriptor address/head/etc colud be 331 * changed */ 332 void reset(); 333 334 virtual void serialize(std::ostream &os); 335 virtual void unserialize(Checkpoint *cp, const std::string §ion); 336 337 virtual bool hasOutstandingEvents() { 338 return wbEvent.scheduled() || fetchEvent.scheduled(); 339 } 340 341 }; 342 343 344 class RxDescCache : public DescCache<iGbReg::RxDesc> 345 { 346 protected: 347 virtual Addr descBase() const { return igbe->regs.rdba(); } 348 virtual long descHead() const { return igbe->regs.rdh(); } 349 virtual long descLen() const { return igbe->regs.rdlen() >> 4; } 350 virtual long descTail() const { return igbe->regs.rdt(); } 351 virtual void updateHead(long h) { igbe->regs.rdh(h); } 352 virtual void enableSm(); 353 virtual void fetchAfterWb() { 354 if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running) 355 fetchDescriptors(); 356 } 357 358 bool pktDone; 359 360 /** Variable to head with header/data completion events */ 361 int splitCount; 362 363 /** Bytes of packet that have been copied, so we know when to 364 set EOP */ 365 unsigned bytesCopied; 366 367 public: 368 RxDescCache(IGbE *i, std::string n, int s); 369 370 /** Write the given packet into the buffer(s) pointed to by the 371 * descriptor and update the book keeping. Should only be called when 372 * there are no dma's pending. 373 * @param packet ethernet packet to write 374 * @param pkt_offset bytes already copied from the packet to memory 375 * @return pkt_offset + number of bytes copied during this call 376 */ 377 int writePacket(EthPacketPtr packet, int pkt_offset); 378 379 /** Called by event when dma to write packet is completed 380 */ 381 void pktComplete(); 382 383 /** Check if the dma on the packet has completed and RX state machine 384 * can continue 385 */ 386 bool packetDone(); 387 388 EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent; 389 390 // Event to handle issuing header and data write at the same time 391 // and only callking pktComplete() when both are completed 392 void pktSplitDone(); 393 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent; 394 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent; 395 396 virtual bool hasOutstandingEvents(); 397 398 virtual void serialize(std::ostream &os); 399 virtual void unserialize(Checkpoint *cp, const std::string §ion); 400 }; 401 friend class RxDescCache; 402 403 RxDescCache rxDescCache; 404 405 class TxDescCache : public DescCache<iGbReg::TxDesc> 406 { 407 protected: 408 virtual Addr descBase() const { return igbe->regs.tdba(); } 409 virtual long descHead() const { return igbe->regs.tdh(); } 410 virtual long descTail() const { return igbe->regs.tdt(); } 411 virtual long descLen() const { return igbe->regs.tdlen() >> 4; } 412 virtual void updateHead(long h) { igbe->regs.tdh(h); } 413 virtual void enableSm(); 414 virtual void actionAfterWb(); 415 virtual void fetchAfterWb() { 416 if (!igbe->txTick && igbe->getDrainState() == Drainable::Running) 417 fetchDescriptors(); 418 } 419 420 421 422 bool pktDone; 423 bool isTcp; 424 bool pktWaiting; 425 bool pktMultiDesc; 426 Addr completionAddress; 427 bool completionEnabled; 428 uint32_t descEnd; 429 430 431 // tso variables 432 bool useTso; 433 Addr tsoHeaderLen; 434 Addr tsoMss; 435 Addr tsoTotalLen; 436 Addr tsoUsedLen; 437 Addr tsoPrevSeq; 438 Addr tsoPktPayloadBytes; 439 bool tsoLoadedHeader; 440 bool tsoPktHasHeader; 441 uint8_t tsoHeader[256]; 442 Addr tsoDescBytesUsed; 443 Addr tsoCopyBytes; 444 int tsoPkts; 445 446 public: 447 TxDescCache(IGbE *i, std::string n, int s); 448 449 /** Tell the cache to DMA a packet from main memory into its buffer and 450 * return the size the of the packet to reserve space in tx fifo. 451 * @return size of the packet 452 */ 453 unsigned getPacketSize(EthPacketPtr p); 454 void getPacketData(EthPacketPtr p); 455 void processContextDesc(); 456 457 /** Return the number of dsecriptors in a cache block for threshold 458 * operations. 459 */ 460 unsigned 461 descInBlock(unsigned num_desc) 462 { 463 return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc); 464 } 465 466 /** Ask if the packet has been transfered so the state machine can give 467 * it to the fifo. 468 * @return packet available in descriptor cache 469 */ 470 bool packetAvailable(); 471 472 /** Ask if we are still waiting for the packet to be transfered. 473 * @return packet still in transit. 474 */ 475 bool packetWaiting() { return pktWaiting; } 476 477 /** Ask if this packet is composed of multiple descriptors 478 * so even if we've got data, we need to wait for more before 479 * we can send it out. 480 * @return packet can't be sent out because it's a multi-descriptor 481 * packet 482 */ 483 bool packetMultiDesc() { return pktMultiDesc;} 484 485 /** Called by event when dma to write packet is completed 486 */ 487 void pktComplete(); 488 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 489 490 void headerComplete(); 491 EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent; 492 493 494 void completionWriteback(Addr a, bool enabled) { 495 DPRINTF(EthernetDesc, 496 "Completion writeback Addr: %#x enabled: %d\n", 497 a, enabled); 498 completionAddress = a; 499 completionEnabled = enabled; 500 } 501 502 virtual bool hasOutstandingEvents(); 503 504 void nullCallback() { 505 DPRINTF(EthernetDesc, "Completion writeback complete\n"); 506 } 507 EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent; 508 509 virtual void serialize(std::ostream &os); 510 virtual void unserialize(Checkpoint *cp, const std::string §ion); 511 512 }; 513 friend class TxDescCache; 514 515 TxDescCache txDescCache; 516 517 public: 518 typedef IGbEParams Params; 519 const Params * 520 params() const { 521 return dynamic_cast<const Params *>(_params); 522 } 523 524 IGbE(const Params *params); 525 ~IGbE(); 526 virtual void init(); 527 528 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 529 530 Tick lastInterrupt; 531 532 virtual Tick read(PacketPtr pkt); 533 virtual Tick write(PacketPtr pkt); 534 535 virtual Tick writeConfig(PacketPtr pkt); 536 537 bool ethRxPkt(EthPacketPtr packet); 538 void ethTxDone(); 539 540 virtual void serialize(std::ostream &os); 541 virtual void unserialize(Checkpoint *cp, const std::string §ion); 542 543 unsigned int drain(DrainManager *dm); 544 void drainResume(); 545 546}; 547 548class IGbEInt : public EtherInt 549{ 550 private: 551 IGbE *dev; 552 553 public: 554 IGbEInt(const std::string &name, IGbE *d) 555 : EtherInt(name), dev(d) 556 { } 557 558 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); } 559 virtual void sendDone() { dev->ethTxDone(); } 560}; 561 562#endif //__DEV_I8254XGBE_HH__ 563