i8254xGBe.cc revision 9198
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/* @file 32 * Device model for Intel's 8254x line of gigabit ethernet controllers. 33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the 34 * fewest workarounds in the driver. It will probably work with most of the 35 * other MACs with slight modifications. 36 */ 37 38 39/* 40 * @todo really there are multiple dma engines.. we should implement them. 41 */ 42 43#include <algorithm> 44 45#include "base/inet.hh" 46#include "base/trace.hh" 47#include "debug/Drain.hh" 48#include "debug/EthernetAll.hh" 49#include "dev/i8254xGBe.hh" 50#include "mem/packet.hh" 51#include "mem/packet_access.hh" 52#include "params/IGbE.hh" 53#include "sim/stats.hh" 54#include "sim/system.hh" 55 56using namespace iGbReg; 57using namespace Net; 58 59IGbE::IGbE(const Params *p) 60 : EtherDevice(p), etherInt(NULL), drainEvent(NULL), 61 useFlowControl(p->use_flow_control), 62 rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false), 63 txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0), 64 fetchDelay(p->fetch_delay), wbDelay(p->wb_delay), 65 fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay), 66 rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay), 67 rdtrEvent(this), radvEvent(this), 68 tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this), 69 rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size), 70 txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), 71 lastInterrupt(0) 72{ 73 etherInt = new IGbEInt(name() + ".int", this); 74 75 // Initialized internal registers per Intel documentation 76 // All registers intialized to 0 by per register constructor 77 regs.ctrl.fd(1); 78 regs.ctrl.lrst(1); 79 regs.ctrl.speed(2); 80 regs.ctrl.frcspd(1); 81 regs.sts.speed(3); // Say we're 1000Mbps 82 regs.sts.fd(1); // full duplex 83 regs.sts.lu(1); // link up 84 regs.eecd.fwe(1); 85 regs.eecd.ee_type(1); 86 regs.imr = 0; 87 regs.iam = 0; 88 regs.rxdctl.gran(1); 89 regs.rxdctl.wthresh(1); 90 regs.fcrth(1); 91 regs.tdwba = 0; 92 regs.rlpml = 0; 93 regs.sw_fw_sync = 0; 94 95 regs.pba.rxa(0x30); 96 regs.pba.txa(0x10); 97 98 eeOpBits = 0; 99 eeAddrBits = 0; 100 eeDataBits = 0; 101 eeOpcode = 0; 102 103 // clear all 64 16 bit words of the eeprom 104 memset(&flash, 0, EEPROM_SIZE*2); 105 106 // Set the MAC address 107 memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN); 108 for (int x = 0; x < ETH_ADDR_LEN/2; x++) 109 flash[x] = htobe(flash[x]); 110 111 uint16_t csum = 0; 112 for (int x = 0; x < EEPROM_SIZE; x++) 113 csum += htobe(flash[x]); 114 115 116 // Magic happy checksum value 117 flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum)); 118 119 // Store the MAC address as queue ID 120 macAddr = p->hardware_address; 121 122 rxFifo.clear(); 123 txFifo.clear(); 124} 125 126IGbE::~IGbE() 127{ 128 delete etherInt; 129} 130 131void 132IGbE::init() 133{ 134 cpa = CPA::cpa(); 135 PciDev::init(); 136} 137 138EtherInt* 139IGbE::getEthPort(const std::string &if_name, int idx) 140{ 141 142 if (if_name == "interface") { 143 if (etherInt->getPeer()) 144 panic("Port already connected to\n"); 145 return etherInt; 146 } 147 return NULL; 148} 149 150Tick 151IGbE::writeConfig(PacketPtr pkt) 152{ 153 int offset = pkt->getAddr() & PCI_CONFIG_SIZE; 154 if (offset < PCI_DEVICE_SPECIFIC) 155 PciDev::writeConfig(pkt); 156 else 157 panic("Device specific PCI config space not implemented.\n"); 158 159 // 160 // Some work may need to be done here based for the pci COMMAND bits. 161 // 162 163 return configDelay; 164} 165 166// Handy macro for range-testing register access addresses 167#define IN_RANGE(val, base, len) (val >= base && val < (base + len)) 168 169Tick 170IGbE::read(PacketPtr pkt) 171{ 172 int bar; 173 Addr daddr; 174 175 if (!getBAR(pkt->getAddr(), bar, daddr)) 176 panic("Invalid PCI memory access to unmapped memory.\n"); 177 178 // Only Memory register BAR is allowed 179 assert(bar == 0); 180 181 // Only 32bit accesses allowed 182 assert(pkt->getSize() == 4); 183 184 DPRINTF(Ethernet, "Read device register %#X\n", daddr); 185 186 pkt->allocate(); 187 188 // 189 // Handle read of register here 190 // 191 192 193 switch (daddr) { 194 case REG_CTRL: 195 pkt->set<uint32_t>(regs.ctrl()); 196 break; 197 case REG_STATUS: 198 pkt->set<uint32_t>(regs.sts()); 199 break; 200 case REG_EECD: 201 pkt->set<uint32_t>(regs.eecd()); 202 break; 203 case REG_EERD: 204 pkt->set<uint32_t>(regs.eerd()); 205 break; 206 case REG_CTRL_EXT: 207 pkt->set<uint32_t>(regs.ctrl_ext()); 208 break; 209 case REG_MDIC: 210 pkt->set<uint32_t>(regs.mdic()); 211 break; 212 case REG_ICR: 213 DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", 214 regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame()); 215 pkt->set<uint32_t>(regs.icr()); 216 if (regs.icr.int_assert() || regs.imr == 0) { 217 regs.icr = regs.icr() & ~mask(30); 218 DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr()); 219 } 220 if (regs.ctrl_ext.iame() && regs.icr.int_assert()) 221 regs.imr &= ~regs.iam; 222 chkInterrupt(); 223 break; 224 case REG_EICR: 225 // This is only useful for MSI, but the driver reads it every time 226 // Just don't do anything 227 pkt->set<uint32_t>(0); 228 break; 229 case REG_ITR: 230 pkt->set<uint32_t>(regs.itr()); 231 break; 232 case REG_RCTL: 233 pkt->set<uint32_t>(regs.rctl()); 234 break; 235 case REG_FCTTV: 236 pkt->set<uint32_t>(regs.fcttv()); 237 break; 238 case REG_TCTL: 239 pkt->set<uint32_t>(regs.tctl()); 240 break; 241 case REG_PBA: 242 pkt->set<uint32_t>(regs.pba()); 243 break; 244 case REG_WUC: 245 case REG_LEDCTL: 246 pkt->set<uint32_t>(0); // We don't care, so just return 0 247 break; 248 case REG_FCRTL: 249 pkt->set<uint32_t>(regs.fcrtl()); 250 break; 251 case REG_FCRTH: 252 pkt->set<uint32_t>(regs.fcrth()); 253 break; 254 case REG_RDBAL: 255 pkt->set<uint32_t>(regs.rdba.rdbal()); 256 break; 257 case REG_RDBAH: 258 pkt->set<uint32_t>(regs.rdba.rdbah()); 259 break; 260 case REG_RDLEN: 261 pkt->set<uint32_t>(regs.rdlen()); 262 break; 263 case REG_SRRCTL: 264 pkt->set<uint32_t>(regs.srrctl()); 265 break; 266 case REG_RDH: 267 pkt->set<uint32_t>(regs.rdh()); 268 break; 269 case REG_RDT: 270 pkt->set<uint32_t>(regs.rdt()); 271 break; 272 case REG_RDTR: 273 pkt->set<uint32_t>(regs.rdtr()); 274 if (regs.rdtr.fpd()) { 275 rxDescCache.writeback(0); 276 DPRINTF(EthernetIntr, 277 "Posting interrupt because of RDTR.FPD write\n"); 278 postInterrupt(IT_RXT); 279 regs.rdtr.fpd(0); 280 } 281 break; 282 case REG_RXDCTL: 283 pkt->set<uint32_t>(regs.rxdctl()); 284 break; 285 case REG_RADV: 286 pkt->set<uint32_t>(regs.radv()); 287 break; 288 case REG_TDBAL: 289 pkt->set<uint32_t>(regs.tdba.tdbal()); 290 break; 291 case REG_TDBAH: 292 pkt->set<uint32_t>(regs.tdba.tdbah()); 293 break; 294 case REG_TDLEN: 295 pkt->set<uint32_t>(regs.tdlen()); 296 break; 297 case REG_TDH: 298 pkt->set<uint32_t>(regs.tdh()); 299 break; 300 case REG_TXDCA_CTL: 301 pkt->set<uint32_t>(regs.txdca_ctl()); 302 break; 303 case REG_TDT: 304 pkt->set<uint32_t>(regs.tdt()); 305 break; 306 case REG_TIDV: 307 pkt->set<uint32_t>(regs.tidv()); 308 break; 309 case REG_TXDCTL: 310 pkt->set<uint32_t>(regs.txdctl()); 311 break; 312 case REG_TADV: 313 pkt->set<uint32_t>(regs.tadv()); 314 break; 315 case REG_TDWBAL: 316 pkt->set<uint32_t>(regs.tdwba & mask(32)); 317 break; 318 case REG_TDWBAH: 319 pkt->set<uint32_t>(regs.tdwba >> 32); 320 break; 321 case REG_RXCSUM: 322 pkt->set<uint32_t>(regs.rxcsum()); 323 break; 324 case REG_RLPML: 325 pkt->set<uint32_t>(regs.rlpml); 326 break; 327 case REG_RFCTL: 328 pkt->set<uint32_t>(regs.rfctl()); 329 break; 330 case REG_MANC: 331 pkt->set<uint32_t>(regs.manc()); 332 break; 333 case REG_SWSM: 334 pkt->set<uint32_t>(regs.swsm()); 335 regs.swsm.smbi(1); 336 break; 337 case REG_FWSM: 338 pkt->set<uint32_t>(regs.fwsm()); 339 break; 340 case REG_SWFWSYNC: 341 pkt->set<uint32_t>(regs.sw_fw_sync); 342 break; 343 default: 344 if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) && 345 !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) && 346 !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4) && 347 !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE)) 348 panic("Read request to unknown register number: %#x\n", daddr); 349 else 350 pkt->set<uint32_t>(0); 351 }; 352 353 pkt->makeAtomicResponse(); 354 return pioDelay; 355} 356 357Tick 358IGbE::write(PacketPtr pkt) 359{ 360 int bar; 361 Addr daddr; 362 363 364 if (!getBAR(pkt->getAddr(), bar, daddr)) 365 panic("Invalid PCI memory access to unmapped memory.\n"); 366 367 // Only Memory register BAR is allowed 368 assert(bar == 0); 369 370 // Only 32bit accesses allowed 371 assert(pkt->getSize() == sizeof(uint32_t)); 372 373 DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", 374 daddr, pkt->get<uint32_t>()); 375 376 // 377 // Handle write of register here 378 // 379 uint32_t val = pkt->get<uint32_t>(); 380 381 Regs::RCTL oldrctl; 382 Regs::TCTL oldtctl; 383 384 switch (daddr) { 385 case REG_CTRL: 386 regs.ctrl = val; 387 if (regs.ctrl.tfce()) 388 warn("TX Flow control enabled, should implement\n"); 389 if (regs.ctrl.rfce()) 390 warn("RX Flow control enabled, should implement\n"); 391 break; 392 case REG_CTRL_EXT: 393 regs.ctrl_ext = val; 394 break; 395 case REG_STATUS: 396 regs.sts = val; 397 break; 398 case REG_EECD: 399 int oldClk; 400 oldClk = regs.eecd.sk(); 401 regs.eecd = val; 402 // See if this is a eeprom access and emulate accordingly 403 if (!oldClk && regs.eecd.sk()) { 404 if (eeOpBits < 8) { 405 eeOpcode = eeOpcode << 1 | regs.eecd.din(); 406 eeOpBits++; 407 } else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) { 408 eeAddr = eeAddr << 1 | regs.eecd.din(); 409 eeAddrBits++; 410 } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) { 411 assert(eeAddr>>1 < EEPROM_SIZE); 412 DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n", 413 flash[eeAddr>>1] >> eeDataBits & 0x1, 414 flash[eeAddr>>1]); 415 regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1); 416 eeDataBits++; 417 } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) { 418 regs.eecd.dout(0); 419 eeDataBits++; 420 } else 421 panic("What's going on with eeprom interface? opcode:" 422 " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode, 423 (uint32_t)eeOpBits, (uint32_t)eeAddr, 424 (uint32_t)eeAddrBits, (uint32_t)eeDataBits); 425 426 // Reset everything for the next command 427 if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) || 428 (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) { 429 eeOpBits = 0; 430 eeAddrBits = 0; 431 eeDataBits = 0; 432 eeOpcode = 0; 433 eeAddr = 0; 434 } 435 436 DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n", 437 (uint32_t)eeOpcode, (uint32_t) eeOpBits, 438 (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits); 439 if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI || 440 eeOpcode == EEPROM_RDSR_OPCODE_SPI )) 441 panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode, 442 (uint32_t)eeOpBits); 443 444 445 } 446 // If driver requests eeprom access, immediately give it to it 447 regs.eecd.ee_gnt(regs.eecd.ee_req()); 448 break; 449 case REG_EERD: 450 regs.eerd = val; 451 if (regs.eerd.start()) { 452 regs.eerd.done(1); 453 assert(regs.eerd.addr() < EEPROM_SIZE); 454 regs.eerd.data(flash[regs.eerd.addr()]); 455 regs.eerd.start(0); 456 DPRINTF(EthernetEEPROM, "EEPROM: read addr: %#X data %#x\n", 457 regs.eerd.addr(), regs.eerd.data()); 458 } 459 break; 460 case REG_MDIC: 461 regs.mdic = val; 462 if (regs.mdic.i()) 463 panic("No support for interrupt on mdic complete\n"); 464 if (regs.mdic.phyadd() != 1) 465 panic("No support for reading anything but phy\n"); 466 DPRINTF(Ethernet, "%s phy address %x\n", 467 regs.mdic.op() == 1 ? "Writing" : "Reading", 468 regs.mdic.regadd()); 469 switch (regs.mdic.regadd()) { 470 case PHY_PSTATUS: 471 regs.mdic.data(0x796D); // link up 472 break; 473 case PHY_PID: 474 regs.mdic.data(params()->phy_pid); 475 break; 476 case PHY_EPID: 477 regs.mdic.data(params()->phy_epid); 478 break; 479 case PHY_GSTATUS: 480 regs.mdic.data(0x7C00); 481 break; 482 case PHY_EPSTATUS: 483 regs.mdic.data(0x3000); 484 break; 485 case PHY_AGC: 486 regs.mdic.data(0x180); // some random length 487 break; 488 default: 489 regs.mdic.data(0); 490 } 491 regs.mdic.r(1); 492 break; 493 case REG_ICR: 494 DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", 495 regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame()); 496 if (regs.ctrl_ext.iame()) 497 regs.imr &= ~regs.iam; 498 regs.icr = ~bits(val,30,0) & regs.icr(); 499 chkInterrupt(); 500 break; 501 case REG_ITR: 502 regs.itr = val; 503 break; 504 case REG_ICS: 505 DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n"); 506 postInterrupt((IntTypes)val); 507 break; 508 case REG_IMS: 509 regs.imr |= val; 510 chkInterrupt(); 511 break; 512 case REG_IMC: 513 regs.imr &= ~val; 514 chkInterrupt(); 515 break; 516 case REG_IAM: 517 regs.iam = val; 518 break; 519 case REG_RCTL: 520 oldrctl = regs.rctl; 521 regs.rctl = val; 522 if (regs.rctl.rst()) { 523 rxDescCache.reset(); 524 DPRINTF(EthernetSM, "RXS: Got RESET!\n"); 525 rxFifo.clear(); 526 regs.rctl.rst(0); 527 } 528 if (regs.rctl.en()) 529 rxTick = true; 530 restartClock(); 531 break; 532 case REG_FCTTV: 533 regs.fcttv = val; 534 break; 535 case REG_TCTL: 536 regs.tctl = val; 537 oldtctl = regs.tctl; 538 regs.tctl = val; 539 if (regs.tctl.en()) 540 txTick = true; 541 restartClock(); 542 if (regs.tctl.en() && !oldtctl.en()) { 543 txDescCache.reset(); 544 } 545 break; 546 case REG_PBA: 547 regs.pba.rxa(val); 548 regs.pba.txa(64 - regs.pba.rxa()); 549 break; 550 case REG_WUC: 551 case REG_LEDCTL: 552 case REG_FCAL: 553 case REG_FCAH: 554 case REG_FCT: 555 case REG_VET: 556 case REG_AIFS: 557 case REG_TIPG: 558 ; // We don't care, so don't store anything 559 break; 560 case REG_IVAR0: 561 warn("Writing to IVAR0, ignoring...\n"); 562 break; 563 case REG_FCRTL: 564 regs.fcrtl = val; 565 break; 566 case REG_FCRTH: 567 regs.fcrth = val; 568 break; 569 case REG_RDBAL: 570 regs.rdba.rdbal( val & ~mask(4)); 571 rxDescCache.areaChanged(); 572 break; 573 case REG_RDBAH: 574 regs.rdba.rdbah(val); 575 rxDescCache.areaChanged(); 576 break; 577 case REG_RDLEN: 578 regs.rdlen = val & ~mask(7); 579 rxDescCache.areaChanged(); 580 break; 581 case REG_SRRCTL: 582 regs.srrctl = val; 583 break; 584 case REG_RDH: 585 regs.rdh = val; 586 rxDescCache.areaChanged(); 587 break; 588 case REG_RDT: 589 regs.rdt = val; 590 DPRINTF(EthernetSM, "RXS: RDT Updated.\n"); 591 if (getState() == SimObject::Running) { 592 DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n"); 593 rxDescCache.fetchDescriptors(); 594 } else { 595 DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n"); 596 } 597 break; 598 case REG_RDTR: 599 regs.rdtr = val; 600 break; 601 case REG_RADV: 602 regs.radv = val; 603 break; 604 case REG_RXDCTL: 605 regs.rxdctl = val; 606 break; 607 case REG_TDBAL: 608 regs.tdba.tdbal( val & ~mask(4)); 609 txDescCache.areaChanged(); 610 break; 611 case REG_TDBAH: 612 regs.tdba.tdbah(val); 613 txDescCache.areaChanged(); 614 break; 615 case REG_TDLEN: 616 regs.tdlen = val & ~mask(7); 617 txDescCache.areaChanged(); 618 break; 619 case REG_TDH: 620 regs.tdh = val; 621 txDescCache.areaChanged(); 622 break; 623 case REG_TXDCA_CTL: 624 regs.txdca_ctl = val; 625 if (regs.txdca_ctl.enabled()) 626 panic("No support for DCA\n"); 627 break; 628 case REG_TDT: 629 regs.tdt = val; 630 DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n"); 631 if (getState() == SimObject::Running) { 632 DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n"); 633 txDescCache.fetchDescriptors(); 634 } else { 635 DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n"); 636 } 637 break; 638 case REG_TIDV: 639 regs.tidv = val; 640 break; 641 case REG_TXDCTL: 642 regs.txdctl = val; 643 break; 644 case REG_TADV: 645 regs.tadv = val; 646 break; 647 case REG_TDWBAL: 648 regs.tdwba &= ~mask(32); 649 regs.tdwba |= val; 650 txDescCache.completionWriteback(regs.tdwba & ~mask(1), 651 regs.tdwba & mask(1)); 652 break; 653 case REG_TDWBAH: 654 regs.tdwba &= mask(32); 655 regs.tdwba |= (uint64_t)val << 32; 656 txDescCache.completionWriteback(regs.tdwba & ~mask(1), 657 regs.tdwba & mask(1)); 658 break; 659 case REG_RXCSUM: 660 regs.rxcsum = val; 661 break; 662 case REG_RLPML: 663 regs.rlpml = val; 664 break; 665 case REG_RFCTL: 666 regs.rfctl = val; 667 if (regs.rfctl.exsten()) 668 panic("Extended RX descriptors not implemented\n"); 669 break; 670 case REG_MANC: 671 regs.manc = val; 672 break; 673 case REG_SWSM: 674 regs.swsm = val; 675 if (regs.fwsm.eep_fw_semaphore()) 676 regs.swsm.swesmbi(0); 677 break; 678 case REG_SWFWSYNC: 679 regs.sw_fw_sync = val; 680 break; 681 default: 682 if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) && 683 !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) && 684 !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4)) 685 panic("Write request to unknown register number: %#x\n", daddr); 686 }; 687 688 pkt->makeAtomicResponse(); 689 return pioDelay; 690} 691 692void 693IGbE::postInterrupt(IntTypes t, bool now) 694{ 695 assert(t); 696 697 // Interrupt is already pending 698 if (t & regs.icr() && !now) 699 return; 700 701 regs.icr = regs.icr() | t; 702 703 Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval(); 704 DPRINTF(EthernetIntr, 705 "EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n", 706 curTick(), regs.itr.interval(), itr_interval); 707 708 if (regs.itr.interval() == 0 || now || 709 lastInterrupt + itr_interval <= curTick()) { 710 if (interEvent.scheduled()) { 711 deschedule(interEvent); 712 } 713 cpuPostInt(); 714 } else { 715 Tick int_time = lastInterrupt + itr_interval; 716 assert(int_time > 0); 717 DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n", 718 int_time); 719 if (!interEvent.scheduled()) { 720 schedule(interEvent, int_time); 721 } 722 } 723} 724 725void 726IGbE::delayIntEvent() 727{ 728 cpuPostInt(); 729} 730 731 732void 733IGbE::cpuPostInt() 734{ 735 736 postedInterrupts++; 737 738 if (!(regs.icr() & regs.imr)) { 739 DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n"); 740 return; 741 } 742 743 DPRINTF(Ethernet, "Posting Interrupt\n"); 744 745 746 if (interEvent.scheduled()) { 747 deschedule(interEvent); 748 } 749 750 if (rdtrEvent.scheduled()) { 751 regs.icr.rxt0(1); 752 deschedule(rdtrEvent); 753 } 754 if (radvEvent.scheduled()) { 755 regs.icr.rxt0(1); 756 deschedule(radvEvent); 757 } 758 if (tadvEvent.scheduled()) { 759 regs.icr.txdw(1); 760 deschedule(tadvEvent); 761 } 762 if (tidvEvent.scheduled()) { 763 regs.icr.txdw(1); 764 deschedule(tidvEvent); 765 } 766 767 regs.icr.int_assert(1); 768 DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n", 769 regs.icr()); 770 771 intrPost(); 772 773 lastInterrupt = curTick(); 774} 775 776void 777IGbE::cpuClearInt() 778{ 779 if (regs.icr.int_assert()) { 780 regs.icr.int_assert(0); 781 DPRINTF(EthernetIntr, 782 "EINT: Clearing interrupt to CPU now. Vector %#x\n", 783 regs.icr()); 784 intrClear(); 785 } 786} 787 788void 789IGbE::chkInterrupt() 790{ 791 DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(), 792 regs.imr); 793 // Check if we need to clear the cpu interrupt 794 if (!(regs.icr() & regs.imr)) { 795 DPRINTF(Ethernet, "Mask cleaned all interrupts\n"); 796 if (interEvent.scheduled()) 797 deschedule(interEvent); 798 if (regs.icr.int_assert()) 799 cpuClearInt(); 800 } 801 DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", 802 regs.itr(), regs.itr.interval()); 803 804 if (regs.icr() & regs.imr) { 805 if (regs.itr.interval() == 0) { 806 cpuPostInt(); 807 } else { 808 DPRINTF(Ethernet, 809 "Possibly scheduling interrupt because of imr write\n"); 810 if (!interEvent.scheduled()) { 811 Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval(); 812 DPRINTF(Ethernet, "Scheduling for %d\n", t); 813 schedule(interEvent, t); 814 } 815 } 816 } 817} 818 819 820///////////////////////////// IGbE::DescCache ////////////////////////////// 821 822template<class T> 823IGbE::DescCache<T>::DescCache(IGbE *i, const std::string n, int s) 824 : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), 825 wbOut(0), pktPtr(NULL), wbDelayEvent(this), 826 fetchDelayEvent(this), fetchEvent(this), wbEvent(this) 827{ 828 fetchBuf = new T[size]; 829 wbBuf = new T[size]; 830} 831 832template<class T> 833IGbE::DescCache<T>::~DescCache() 834{ 835 reset(); 836 delete[] fetchBuf; 837 delete[] wbBuf; 838} 839 840template<class T> 841void 842IGbE::DescCache<T>::areaChanged() 843{ 844 if (usedCache.size() > 0 || curFetching || wbOut) 845 panic("Descriptor Address, Length or Head changed. Bad\n"); 846 reset(); 847 848} 849 850template<class T> 851void 852IGbE::DescCache<T>::writeback(Addr aMask) 853{ 854 int curHead = descHead(); 855 int max_to_wb = usedCache.size(); 856 857 // Check if this writeback is less restrictive that the previous 858 // and if so setup another one immediately following it 859 if (wbOut) { 860 if (aMask < wbAlignment) { 861 moreToWb = true; 862 wbAlignment = aMask; 863 } 864 DPRINTF(EthernetDesc, 865 "Writing back already in process, returning\n"); 866 return; 867 } 868 869 moreToWb = false; 870 wbAlignment = aMask; 871 872 873 DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: " 874 "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n", 875 curHead, descTail(), descLen(), cachePnt, max_to_wb, 876 descLeft()); 877 878 if (max_to_wb + curHead >= descLen()) { 879 max_to_wb = descLen() - curHead; 880 moreToWb = true; 881 // this is by definition aligned correctly 882 } else if (wbAlignment != 0) { 883 // align the wb point to the mask 884 max_to_wb = max_to_wb & ~wbAlignment; 885 } 886 887 DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb); 888 889 if (max_to_wb <= 0) { 890 if (usedCache.size()) 891 igbe->anBegin(annSmWb, "Wait Alignment", CPA::FL_WAIT); 892 else 893 igbe->anWe(annSmWb, annUsedCacheQ); 894 return; 895 } 896 897 wbOut = max_to_wb; 898 899 assert(!wbDelayEvent.scheduled()); 900 igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay); 901 igbe->anBegin(annSmWb, "Prepare Writeback Desc"); 902} 903 904template<class T> 905void 906IGbE::DescCache<T>::writeback1() 907{ 908 // If we're draining delay issuing this DMA 909 if (igbe->getState() != SimObject::Running) { 910 igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay); 911 return; 912 } 913 914 DPRINTF(EthernetDesc, "Begining DMA of %d descriptors\n", wbOut); 915 916 for (int x = 0; x < wbOut; x++) { 917 assert(usedCache.size()); 918 memcpy(&wbBuf[x], usedCache[x], sizeof(T)); 919 igbe->anPq(annSmWb, annUsedCacheQ); 920 igbe->anPq(annSmWb, annDescQ); 921 igbe->anQ(annSmWb, annUsedDescQ); 922 } 923 924 925 igbe->anBegin(annSmWb, "Writeback Desc DMA"); 926 927 assert(wbOut); 928 igbe->dmaWrite(pciToDma(descBase() + descHead() * sizeof(T)), 929 wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf, 930 igbe->wbCompDelay); 931} 932 933template<class T> 934void 935IGbE::DescCache<T>::fetchDescriptors() 936{ 937 size_t max_to_fetch; 938 939 if (curFetching) { 940 DPRINTF(EthernetDesc, 941 "Currently fetching %d descriptors, returning\n", 942 curFetching); 943 return; 944 } 945 946 if (descTail() >= cachePnt) 947 max_to_fetch = descTail() - cachePnt; 948 else 949 max_to_fetch = descLen() - cachePnt; 950 951 size_t free_cache = size - usedCache.size() - unusedCache.size(); 952 953 if (!max_to_fetch) 954 igbe->anWe(annSmFetch, annUnusedDescQ); 955 else 956 igbe->anPq(annSmFetch, annUnusedDescQ, max_to_fetch); 957 958 if (max_to_fetch) { 959 if (!free_cache) 960 igbe->anWf(annSmFetch, annDescQ); 961 else 962 igbe->anRq(annSmFetch, annDescQ, free_cache); 963 } 964 965 max_to_fetch = std::min(max_to_fetch, free_cache); 966 967 968 DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: " 969 "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n", 970 descHead(), descTail(), descLen(), cachePnt, 971 max_to_fetch, descLeft()); 972 973 // Nothing to do 974 if (max_to_fetch == 0) 975 return; 976 977 // So we don't have two descriptor fetches going on at once 978 curFetching = max_to_fetch; 979 980 assert(!fetchDelayEvent.scheduled()); 981 igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay); 982 igbe->anBegin(annSmFetch, "Prepare Fetch Desc"); 983} 984 985template<class T> 986void 987IGbE::DescCache<T>::fetchDescriptors1() 988{ 989 // If we're draining delay issuing this DMA 990 if (igbe->getState() != SimObject::Running) { 991 igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay); 992 return; 993 } 994 995 igbe->anBegin(annSmFetch, "Fetch Desc"); 996 997 DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n", 998 descBase() + cachePnt * sizeof(T), 999 pciToDma(descBase() + cachePnt * sizeof(T)), 1000 curFetching * sizeof(T)); 1001 assert(curFetching); 1002 igbe->dmaRead(pciToDma(descBase() + cachePnt * sizeof(T)), 1003 curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf, 1004 igbe->fetchCompDelay); 1005} 1006 1007template<class T> 1008void 1009IGbE::DescCache<T>::fetchComplete() 1010{ 1011 T *newDesc; 1012 igbe->anBegin(annSmFetch, "Fetch Complete"); 1013 for (int x = 0; x < curFetching; x++) { 1014 newDesc = new T; 1015 memcpy(newDesc, &fetchBuf[x], sizeof(T)); 1016 unusedCache.push_back(newDesc); 1017 igbe->anDq(annSmFetch, annUnusedDescQ); 1018 igbe->anQ(annSmFetch, annUnusedCacheQ); 1019 igbe->anQ(annSmFetch, annDescQ); 1020 } 1021 1022 1023#ifndef NDEBUG 1024 int oldCp = cachePnt; 1025#endif 1026 1027 cachePnt += curFetching; 1028 assert(cachePnt <= descLen()); 1029 if (cachePnt == descLen()) 1030 cachePnt = 0; 1031 1032 curFetching = 0; 1033 1034 DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n", 1035 oldCp, cachePnt); 1036 1037 if ((descTail() >= cachePnt ? (descTail() - cachePnt) : (descLen() - 1038 cachePnt)) == 0) 1039 { 1040 igbe->anWe(annSmFetch, annUnusedDescQ); 1041 } else if (!(size - usedCache.size() - unusedCache.size())) { 1042 igbe->anWf(annSmFetch, annDescQ); 1043 } else { 1044 igbe->anBegin(annSmFetch, "Wait", CPA::FL_WAIT); 1045 } 1046 1047 enableSm(); 1048 igbe->checkDrain(); 1049} 1050 1051template<class T> 1052void 1053IGbE::DescCache<T>::wbComplete() 1054{ 1055 1056 igbe->anBegin(annSmWb, "Finish Writeback"); 1057 1058 long curHead = descHead(); 1059#ifndef NDEBUG 1060 long oldHead = curHead; 1061#endif 1062 1063 for (int x = 0; x < wbOut; x++) { 1064 assert(usedCache.size()); 1065 delete usedCache[0]; 1066 usedCache.pop_front(); 1067 1068 igbe->anDq(annSmWb, annUsedCacheQ); 1069 igbe->anDq(annSmWb, annDescQ); 1070 } 1071 1072 curHead += wbOut; 1073 wbOut = 0; 1074 1075 if (curHead >= descLen()) 1076 curHead -= descLen(); 1077 1078 // Update the head 1079 updateHead(curHead); 1080 1081 DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n", 1082 oldHead, curHead); 1083 1084 // If we still have more to wb, call wb now 1085 actionAfterWb(); 1086 if (moreToWb) { 1087 moreToWb = false; 1088 DPRINTF(EthernetDesc, "Writeback has more todo\n"); 1089 writeback(wbAlignment); 1090 } 1091 1092 if (!wbOut) { 1093 igbe->checkDrain(); 1094 if (usedCache.size()) 1095 igbe->anBegin(annSmWb, "Wait", CPA::FL_WAIT); 1096 else 1097 igbe->anWe(annSmWb, annUsedCacheQ); 1098 } 1099 fetchAfterWb(); 1100} 1101 1102template<class T> 1103void 1104IGbE::DescCache<T>::reset() 1105{ 1106 DPRINTF(EthernetDesc, "Reseting descriptor cache\n"); 1107 for (typename CacheType::size_type x = 0; x < usedCache.size(); x++) 1108 delete usedCache[x]; 1109 for (typename CacheType::size_type x = 0; x < unusedCache.size(); x++) 1110 delete unusedCache[x]; 1111 1112 usedCache.clear(); 1113 unusedCache.clear(); 1114 1115 cachePnt = 0; 1116 1117} 1118 1119template<class T> 1120void 1121IGbE::DescCache<T>::serialize(std::ostream &os) 1122{ 1123 SERIALIZE_SCALAR(cachePnt); 1124 SERIALIZE_SCALAR(curFetching); 1125 SERIALIZE_SCALAR(wbOut); 1126 SERIALIZE_SCALAR(moreToWb); 1127 SERIALIZE_SCALAR(wbAlignment); 1128 1129 typename CacheType::size_type usedCacheSize = usedCache.size(); 1130 SERIALIZE_SCALAR(usedCacheSize); 1131 for (typename CacheType::size_type x = 0; x < usedCacheSize; x++) { 1132 arrayParamOut(os, csprintf("usedCache_%d", x), 1133 (uint8_t*)usedCache[x],sizeof(T)); 1134 } 1135 1136 typename CacheType::size_type unusedCacheSize = unusedCache.size(); 1137 SERIALIZE_SCALAR(unusedCacheSize); 1138 for (typename CacheType::size_type x = 0; x < unusedCacheSize; x++) { 1139 arrayParamOut(os, csprintf("unusedCache_%d", x), 1140 (uint8_t*)unusedCache[x],sizeof(T)); 1141 } 1142 1143 Tick fetch_delay = 0, wb_delay = 0; 1144 if (fetchDelayEvent.scheduled()) 1145 fetch_delay = fetchDelayEvent.when(); 1146 SERIALIZE_SCALAR(fetch_delay); 1147 if (wbDelayEvent.scheduled()) 1148 wb_delay = wbDelayEvent.when(); 1149 SERIALIZE_SCALAR(wb_delay); 1150 1151 1152} 1153 1154template<class T> 1155void 1156IGbE::DescCache<T>::unserialize(Checkpoint *cp, const std::string §ion) 1157{ 1158 UNSERIALIZE_SCALAR(cachePnt); 1159 UNSERIALIZE_SCALAR(curFetching); 1160 UNSERIALIZE_SCALAR(wbOut); 1161 UNSERIALIZE_SCALAR(moreToWb); 1162 UNSERIALIZE_SCALAR(wbAlignment); 1163 1164 typename CacheType::size_type usedCacheSize; 1165 UNSERIALIZE_SCALAR(usedCacheSize); 1166 T *temp; 1167 for (typename CacheType::size_type x = 0; x < usedCacheSize; x++) { 1168 temp = new T; 1169 arrayParamIn(cp, section, csprintf("usedCache_%d", x), 1170 (uint8_t*)temp,sizeof(T)); 1171 usedCache.push_back(temp); 1172 } 1173 1174 typename CacheType::size_type unusedCacheSize; 1175 UNSERIALIZE_SCALAR(unusedCacheSize); 1176 for (typename CacheType::size_type x = 0; x < unusedCacheSize; x++) { 1177 temp = new T; 1178 arrayParamIn(cp, section, csprintf("unusedCache_%d", x), 1179 (uint8_t*)temp,sizeof(T)); 1180 unusedCache.push_back(temp); 1181 } 1182 Tick fetch_delay = 0, wb_delay = 0; 1183 UNSERIALIZE_SCALAR(fetch_delay); 1184 UNSERIALIZE_SCALAR(wb_delay); 1185 if (fetch_delay) 1186 igbe->schedule(fetchDelayEvent, fetch_delay); 1187 if (wb_delay) 1188 igbe->schedule(wbDelayEvent, wb_delay); 1189 1190 1191} 1192 1193///////////////////////////// IGbE::RxDescCache ////////////////////////////// 1194 1195IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s) 1196 : DescCache<RxDesc>(i, n, s), pktDone(false), splitCount(0), 1197 pktEvent(this), pktHdrEvent(this), pktDataEvent(this) 1198 1199{ 1200 annSmFetch = "RX Desc Fetch"; 1201 annSmWb = "RX Desc Writeback"; 1202 annUnusedDescQ = "RX Unused Descriptors"; 1203 annUnusedCacheQ = "RX Unused Descriptor Cache"; 1204 annUsedCacheQ = "RX Used Descriptor Cache"; 1205 annUsedDescQ = "RX Used Descriptors"; 1206 annDescQ = "RX Descriptors"; 1207} 1208 1209void 1210IGbE::RxDescCache::pktSplitDone() 1211{ 1212 splitCount++; 1213 DPRINTF(EthernetDesc, 1214 "Part of split packet done: splitcount now %d\n", splitCount); 1215 assert(splitCount <= 2); 1216 if (splitCount != 2) 1217 return; 1218 splitCount = 0; 1219 DPRINTF(EthernetDesc, 1220 "Part of split packet done: calling pktComplete()\n"); 1221 pktComplete(); 1222} 1223 1224int 1225IGbE::RxDescCache::writePacket(EthPacketPtr packet, int pkt_offset) 1226{ 1227 assert(unusedCache.size()); 1228 //if (!unusedCache.size()) 1229 // return false; 1230 1231 pktPtr = packet; 1232 pktDone = false; 1233 unsigned buf_len, hdr_len; 1234 1235 RxDesc *desc = unusedCache.front(); 1236 switch (igbe->regs.srrctl.desctype()) { 1237 case RXDT_LEGACY: 1238 assert(pkt_offset == 0); 1239 bytesCopied = packet->length; 1240 DPRINTF(EthernetDesc, "Packet Length: %d Desc Size: %d\n", 1241 packet->length, igbe->regs.rctl.descSize()); 1242 assert(packet->length < igbe->regs.rctl.descSize()); 1243 igbe->dmaWrite(pciToDma(desc->legacy.buf), 1244 packet->length, &pktEvent, packet->data, 1245 igbe->rxWriteDelay); 1246 break; 1247 case RXDT_ADV_ONEBUF: 1248 assert(pkt_offset == 0); 1249 bytesCopied = packet->length; 1250 buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() : 1251 igbe->regs.rctl.descSize(); 1252 DPRINTF(EthernetDesc, "Packet Length: %d srrctl: %#x Desc Size: %d\n", 1253 packet->length, igbe->regs.srrctl(), buf_len); 1254 assert(packet->length < buf_len); 1255 igbe->dmaWrite(pciToDma(desc->adv_read.pkt), 1256 packet->length, &pktEvent, packet->data, 1257 igbe->rxWriteDelay); 1258 desc->adv_wb.header_len = htole(0); 1259 desc->adv_wb.sph = htole(0); 1260 desc->adv_wb.pkt_len = htole((uint16_t)(pktPtr->length)); 1261 break; 1262 case RXDT_ADV_SPLIT_A: 1263 int split_point; 1264 1265 buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() : 1266 igbe->regs.rctl.descSize(); 1267 hdr_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.hdrLen() : 0; 1268 DPRINTF(EthernetDesc, 1269 "lpe: %d Packet Length: %d offset: %d srrctl: %#x " 1270 "hdr addr: %#x Hdr Size: %d desc addr: %#x Desc Size: %d\n", 1271 igbe->regs.rctl.lpe(), packet->length, pkt_offset, 1272 igbe->regs.srrctl(), desc->adv_read.hdr, hdr_len, 1273 desc->adv_read.pkt, buf_len); 1274 1275 split_point = hsplit(pktPtr); 1276 1277 if (packet->length <= hdr_len) { 1278 bytesCopied = packet->length; 1279 assert(pkt_offset == 0); 1280 DPRINTF(EthernetDesc, "Hdr split: Entire packet in header\n"); 1281 igbe->dmaWrite(pciToDma(desc->adv_read.hdr), 1282 packet->length, &pktEvent, packet->data, 1283 igbe->rxWriteDelay); 1284 desc->adv_wb.header_len = htole((uint16_t)packet->length); 1285 desc->adv_wb.sph = htole(0); 1286 desc->adv_wb.pkt_len = htole(0); 1287 } else if (split_point) { 1288 if (pkt_offset) { 1289 // we are only copying some data, header/data has already been 1290 // copied 1291 int max_to_copy = 1292 std::min(packet->length - pkt_offset, buf_len); 1293 bytesCopied += max_to_copy; 1294 DPRINTF(EthernetDesc, 1295 "Hdr split: Continuing data buffer copy\n"); 1296 igbe->dmaWrite(pciToDma(desc->adv_read.pkt), 1297 max_to_copy, &pktEvent, 1298 packet->data + pkt_offset, igbe->rxWriteDelay); 1299 desc->adv_wb.header_len = htole(0); 1300 desc->adv_wb.pkt_len = htole((uint16_t)max_to_copy); 1301 desc->adv_wb.sph = htole(0); 1302 } else { 1303 int max_to_copy = 1304 std::min(packet->length - split_point, buf_len); 1305 bytesCopied += max_to_copy + split_point; 1306 1307 DPRINTF(EthernetDesc, "Hdr split: splitting at %d\n", 1308 split_point); 1309 igbe->dmaWrite(pciToDma(desc->adv_read.hdr), 1310 split_point, &pktHdrEvent, 1311 packet->data, igbe->rxWriteDelay); 1312 igbe->dmaWrite(pciToDma(desc->adv_read.pkt), 1313 max_to_copy, &pktDataEvent, 1314 packet->data + split_point, igbe->rxWriteDelay); 1315 desc->adv_wb.header_len = htole(split_point); 1316 desc->adv_wb.sph = 1; 1317 desc->adv_wb.pkt_len = htole((uint16_t)(max_to_copy)); 1318 } 1319 } else { 1320 panic("Header split not fitting within header buffer or " 1321 "undecodable packet not fitting in header unsupported\n"); 1322 } 1323 break; 1324 default: 1325 panic("Unimplemnted RX receive buffer type: %d\n", 1326 igbe->regs.srrctl.desctype()); 1327 } 1328 return bytesCopied; 1329 1330} 1331 1332void 1333IGbE::RxDescCache::pktComplete() 1334{ 1335 assert(unusedCache.size()); 1336 RxDesc *desc; 1337 desc = unusedCache.front(); 1338 1339 igbe->anBegin("RXS", "Update Desc"); 1340 1341 uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ; 1342 DPRINTF(EthernetDesc, "pktPtr->length: %d bytesCopied: %d " 1343 "stripcrc offset: %d value written: %d %d\n", 1344 pktPtr->length, bytesCopied, crcfixup, 1345 htole((uint16_t)(pktPtr->length + crcfixup)), 1346 (uint16_t)(pktPtr->length + crcfixup)); 1347 1348 // no support for anything but starting at 0 1349 assert(igbe->regs.rxcsum.pcss() == 0); 1350 1351 DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n"); 1352 1353 uint16_t status = RXDS_DD; 1354 uint8_t err = 0; 1355 uint16_t ext_err = 0; 1356 uint16_t csum = 0; 1357 uint16_t ptype = 0; 1358 uint16_t ip_id = 0; 1359 1360 assert(bytesCopied <= pktPtr->length); 1361 if (bytesCopied == pktPtr->length) 1362 status |= RXDS_EOP; 1363 1364 IpPtr ip(pktPtr); 1365 1366 if (ip) { 1367 DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id()); 1368 ptype |= RXDP_IPV4; 1369 ip_id = ip->id(); 1370 1371 if (igbe->regs.rxcsum.ipofld()) { 1372 DPRINTF(EthernetDesc, "Checking IP checksum\n"); 1373 status |= RXDS_IPCS; 1374 csum = htole(cksum(ip)); 1375 igbe->rxIpChecksums++; 1376 if (cksum(ip) != 0) { 1377 err |= RXDE_IPE; 1378 ext_err |= RXDEE_IPE; 1379 DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 1380 } 1381 } 1382 TcpPtr tcp(ip); 1383 if (tcp && igbe->regs.rxcsum.tuofld()) { 1384 DPRINTF(EthernetDesc, "Checking TCP checksum\n"); 1385 status |= RXDS_TCPCS; 1386 ptype |= RXDP_TCP; 1387 csum = htole(cksum(tcp)); 1388 igbe->rxTcpChecksums++; 1389 if (cksum(tcp) != 0) { 1390 DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 1391 err |= RXDE_TCPE; 1392 ext_err |= RXDEE_TCPE; 1393 } 1394 } 1395 1396 UdpPtr udp(ip); 1397 if (udp && igbe->regs.rxcsum.tuofld()) { 1398 DPRINTF(EthernetDesc, "Checking UDP checksum\n"); 1399 status |= RXDS_UDPCS; 1400 ptype |= RXDP_UDP; 1401 csum = htole(cksum(udp)); 1402 igbe->rxUdpChecksums++; 1403 if (cksum(udp) != 0) { 1404 DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 1405 ext_err |= RXDEE_TCPE; 1406 err |= RXDE_TCPE; 1407 } 1408 } 1409 } else { // if ip 1410 DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); 1411 } 1412 1413 switch (igbe->regs.srrctl.desctype()) { 1414 case RXDT_LEGACY: 1415 desc->legacy.len = htole((uint16_t)(pktPtr->length + crcfixup)); 1416 desc->legacy.status = htole(status); 1417 desc->legacy.errors = htole(err); 1418 // No vlan support at this point... just set it to 0 1419 desc->legacy.vlan = 0; 1420 break; 1421 case RXDT_ADV_SPLIT_A: 1422 case RXDT_ADV_ONEBUF: 1423 desc->adv_wb.rss_type = htole(0); 1424 desc->adv_wb.pkt_type = htole(ptype); 1425 if (igbe->regs.rxcsum.pcsd()) { 1426 // no rss support right now 1427 desc->adv_wb.rss_hash = htole(0); 1428 } else { 1429 desc->adv_wb.id = htole(ip_id); 1430 desc->adv_wb.csum = htole(csum); 1431 } 1432 desc->adv_wb.status = htole(status); 1433 desc->adv_wb.errors = htole(ext_err); 1434 // no vlan support 1435 desc->adv_wb.vlan_tag = htole(0); 1436 break; 1437 default: 1438 panic("Unimplemnted RX receive buffer type %d\n", 1439 igbe->regs.srrctl.desctype()); 1440 } 1441 1442 DPRINTF(EthernetDesc, "Descriptor complete w0: %#x w1: %#x\n", 1443 desc->adv_read.pkt, desc->adv_read.hdr); 1444 1445 if (bytesCopied == pktPtr->length) { 1446 DPRINTF(EthernetDesc, 1447 "Packet completely written to descriptor buffers\n"); 1448 // Deal with the rx timer interrupts 1449 if (igbe->regs.rdtr.delay()) { 1450 Tick delay = igbe->regs.rdtr.delay() * igbe->intClock(); 1451 DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", delay); 1452 igbe->reschedule(igbe->rdtrEvent, curTick() + delay); 1453 } 1454 1455 if (igbe->regs.radv.idv()) { 1456 Tick delay = igbe->regs.radv.idv() * igbe->intClock(); 1457 DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", delay); 1458 if (!igbe->radvEvent.scheduled()) { 1459 igbe->schedule(igbe->radvEvent, curTick() + delay); 1460 } 1461 } 1462 1463 // if neither radv or rdtr, maybe itr is set... 1464 if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) { 1465 DPRINTF(EthernetSM, 1466 "RXS: Receive interrupt delay disabled, posting IT_RXT\n"); 1467 igbe->postInterrupt(IT_RXT); 1468 } 1469 1470 // If the packet is small enough, interrupt appropriately 1471 // I wonder if this is delayed or not?! 1472 if (pktPtr->length <= igbe->regs.rsrpd.idv()) { 1473 DPRINTF(EthernetSM, 1474 "RXS: Posting IT_SRPD beacuse small packet received\n"); 1475 igbe->postInterrupt(IT_SRPD); 1476 } 1477 bytesCopied = 0; 1478 } 1479 1480 pktPtr = NULL; 1481 igbe->checkDrain(); 1482 enableSm(); 1483 pktDone = true; 1484 1485 igbe->anBegin("RXS", "Done Updating Desc"); 1486 DPRINTF(EthernetDesc, "Processing of this descriptor complete\n"); 1487 igbe->anDq("RXS", annUnusedCacheQ); 1488 unusedCache.pop_front(); 1489 igbe->anQ("RXS", annUsedCacheQ); 1490 usedCache.push_back(desc); 1491} 1492 1493void 1494IGbE::RxDescCache::enableSm() 1495{ 1496 if (!igbe->drainEvent) { 1497 igbe->rxTick = true; 1498 igbe->restartClock(); 1499 } 1500} 1501 1502bool 1503IGbE::RxDescCache::packetDone() 1504{ 1505 if (pktDone) { 1506 pktDone = false; 1507 return true; 1508 } 1509 return false; 1510} 1511 1512bool 1513IGbE::RxDescCache::hasOutstandingEvents() 1514{ 1515 return pktEvent.scheduled() || wbEvent.scheduled() || 1516 fetchEvent.scheduled() || pktHdrEvent.scheduled() || 1517 pktDataEvent.scheduled(); 1518 1519} 1520 1521void 1522IGbE::RxDescCache::serialize(std::ostream &os) 1523{ 1524 DescCache<RxDesc>::serialize(os); 1525 SERIALIZE_SCALAR(pktDone); 1526 SERIALIZE_SCALAR(splitCount); 1527 SERIALIZE_SCALAR(bytesCopied); 1528} 1529 1530void 1531IGbE::RxDescCache::unserialize(Checkpoint *cp, const std::string §ion) 1532{ 1533 DescCache<RxDesc>::unserialize(cp, section); 1534 UNSERIALIZE_SCALAR(pktDone); 1535 UNSERIALIZE_SCALAR(splitCount); 1536 UNSERIALIZE_SCALAR(bytesCopied); 1537} 1538 1539 1540///////////////////////////// IGbE::TxDescCache ////////////////////////////// 1541 1542IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s) 1543 : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), 1544 pktWaiting(false), completionAddress(0), completionEnabled(false), 1545 useTso(false), tsoHeaderLen(0), tsoMss(0), tsoTotalLen(0), tsoUsedLen(0), 1546 tsoPrevSeq(0), tsoPktPayloadBytes(0), tsoLoadedHeader(false), 1547 tsoPktHasHeader(false), tsoDescBytesUsed(0), tsoCopyBytes(0), tsoPkts(0), 1548 pktEvent(this), headerEvent(this), nullEvent(this) 1549{ 1550 annSmFetch = "TX Desc Fetch"; 1551 annSmWb = "TX Desc Writeback"; 1552 annUnusedDescQ = "TX Unused Descriptors"; 1553 annUnusedCacheQ = "TX Unused Descriptor Cache"; 1554 annUsedCacheQ = "TX Used Descriptor Cache"; 1555 annUsedDescQ = "TX Used Descriptors"; 1556 annDescQ = "TX Descriptors"; 1557} 1558 1559void 1560IGbE::TxDescCache::processContextDesc() 1561{ 1562 assert(unusedCache.size()); 1563 TxDesc *desc; 1564 1565 DPRINTF(EthernetDesc, "Checking and processing context descriptors\n"); 1566 1567 while (!useTso && unusedCache.size() && 1568 TxdOp::isContext(unusedCache.front())) { 1569 DPRINTF(EthernetDesc, "Got context descriptor type...\n"); 1570 1571 desc = unusedCache.front(); 1572 DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", 1573 desc->d1, desc->d2); 1574 1575 1576 // is this going to be a tcp or udp packet? 1577 isTcp = TxdOp::tcp(desc) ? true : false; 1578 1579 // setup all the TSO variables, they'll be ignored if we don't use 1580 // tso for this connection 1581 tsoHeaderLen = TxdOp::hdrlen(desc); 1582 tsoMss = TxdOp::mss(desc); 1583 1584 if (TxdOp::isType(desc, TxdOp::TXD_CNXT) && TxdOp::tse(desc)) { 1585 DPRINTF(EthernetDesc, "TCP offload enabled for packet hdrlen: " 1586 "%d mss: %d paylen %d\n", TxdOp::hdrlen(desc), 1587 TxdOp::mss(desc), TxdOp::getLen(desc)); 1588 useTso = true; 1589 tsoTotalLen = TxdOp::getLen(desc); 1590 tsoLoadedHeader = false; 1591 tsoDescBytesUsed = 0; 1592 tsoUsedLen = 0; 1593 tsoPrevSeq = 0; 1594 tsoPktHasHeader = false; 1595 tsoPkts = 0; 1596 tsoCopyBytes = 0; 1597 } 1598 1599 TxdOp::setDd(desc); 1600 unusedCache.pop_front(); 1601 igbe->anDq("TXS", annUnusedCacheQ); 1602 usedCache.push_back(desc); 1603 igbe->anQ("TXS", annUsedCacheQ); 1604 } 1605 1606 if (!unusedCache.size()) 1607 return; 1608 1609 desc = unusedCache.front(); 1610 if (!useTso && TxdOp::isType(desc, TxdOp::TXD_ADVDATA) && 1611 TxdOp::tse(desc)) { 1612 DPRINTF(EthernetDesc, "TCP offload(adv) enabled for packet " 1613 "hdrlen: %d mss: %d paylen %d\n", 1614 tsoHeaderLen, tsoMss, TxdOp::getTsoLen(desc)); 1615 useTso = true; 1616 tsoTotalLen = TxdOp::getTsoLen(desc); 1617 tsoLoadedHeader = false; 1618 tsoDescBytesUsed = 0; 1619 tsoUsedLen = 0; 1620 tsoPrevSeq = 0; 1621 tsoPktHasHeader = false; 1622 tsoPkts = 0; 1623 } 1624 1625 if (useTso && !tsoLoadedHeader) { 1626 // we need to fetch a header 1627 DPRINTF(EthernetDesc, "Starting DMA of TSO header\n"); 1628 assert(TxdOp::isData(desc) && TxdOp::getLen(desc) >= tsoHeaderLen); 1629 pktWaiting = true; 1630 assert(tsoHeaderLen <= 256); 1631 igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)), 1632 tsoHeaderLen, &headerEvent, tsoHeader, 0); 1633 } 1634} 1635 1636void 1637IGbE::TxDescCache::headerComplete() 1638{ 1639 DPRINTF(EthernetDesc, "TSO: Fetching TSO header complete\n"); 1640 pktWaiting = false; 1641 1642 assert(unusedCache.size()); 1643 TxDesc *desc = unusedCache.front(); 1644 DPRINTF(EthernetDesc, "TSO: len: %d tsoHeaderLen: %d\n", 1645 TxdOp::getLen(desc), tsoHeaderLen); 1646 1647 if (TxdOp::getLen(desc) == tsoHeaderLen) { 1648 tsoDescBytesUsed = 0; 1649 tsoLoadedHeader = true; 1650 unusedCache.pop_front(); 1651 usedCache.push_back(desc); 1652 } else { 1653 DPRINTF(EthernetDesc, "TSO: header part of larger payload\n"); 1654 tsoDescBytesUsed = tsoHeaderLen; 1655 tsoLoadedHeader = true; 1656 } 1657 enableSm(); 1658 igbe->checkDrain(); 1659} 1660 1661unsigned 1662IGbE::TxDescCache::getPacketSize(EthPacketPtr p) 1663{ 1664 if (!unusedCache.size()) 1665 return 0; 1666 1667 DPRINTF(EthernetDesc, "Starting processing of descriptor\n"); 1668 1669 assert(!useTso || tsoLoadedHeader); 1670 TxDesc *desc = unusedCache.front(); 1671 1672 if (useTso) { 1673 DPRINTF(EthernetDesc, "getPacket(): TxDescriptor data " 1674 "d1: %#llx d2: %#llx\n", desc->d1, desc->d2); 1675 DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d " 1676 "used: %d loaded hdr: %d\n", useTso, tsoHeaderLen, tsoMss, 1677 tsoTotalLen, tsoUsedLen, tsoLoadedHeader); 1678 1679 if (tsoPktHasHeader) 1680 tsoCopyBytes = std::min((tsoMss + tsoHeaderLen) - p->length, 1681 TxdOp::getLen(desc) - tsoDescBytesUsed); 1682 else 1683 tsoCopyBytes = std::min(tsoMss, 1684 TxdOp::getLen(desc) - tsoDescBytesUsed); 1685 unsigned pkt_size = 1686 tsoCopyBytes + (tsoPktHasHeader ? 0 : tsoHeaderLen); 1687 1688 DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d " 1689 "this descLen: %d\n", 1690 tsoDescBytesUsed, tsoCopyBytes, TxdOp::getLen(desc)); 1691 DPRINTF(EthernetDesc, "TSO: pktHasHeader: %d\n", tsoPktHasHeader); 1692 DPRINTF(EthernetDesc, "TSO: Next packet is %d bytes\n", pkt_size); 1693 return pkt_size; 1694 } 1695 1696 DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n", 1697 TxdOp::getLen(unusedCache.front())); 1698 return TxdOp::getLen(desc); 1699} 1700 1701void 1702IGbE::TxDescCache::getPacketData(EthPacketPtr p) 1703{ 1704 assert(unusedCache.size()); 1705 1706 TxDesc *desc; 1707 desc = unusedCache.front(); 1708 1709 DPRINTF(EthernetDesc, "getPacketData(): TxDescriptor data " 1710 "d1: %#llx d2: %#llx\n", desc->d1, desc->d2); 1711 assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && 1712 TxdOp::getLen(desc)); 1713 1714 pktPtr = p; 1715 1716 pktWaiting = true; 1717 1718 DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length); 1719 1720 if (useTso) { 1721 assert(tsoLoadedHeader); 1722 if (!tsoPktHasHeader) { 1723 DPRINTF(EthernetDesc, 1724 "Loading TSO header (%d bytes) into start of packet\n", 1725 tsoHeaderLen); 1726 memcpy(p->data, &tsoHeader,tsoHeaderLen); 1727 p->length +=tsoHeaderLen; 1728 tsoPktHasHeader = true; 1729 } 1730 } 1731 1732 if (useTso) { 1733 DPRINTF(EthernetDesc, 1734 "Starting DMA of packet at offset %d length: %d\n", 1735 p->length, tsoCopyBytes); 1736 igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)) 1737 + tsoDescBytesUsed, 1738 tsoCopyBytes, &pktEvent, p->data + p->length, 1739 igbe->txReadDelay); 1740 tsoDescBytesUsed += tsoCopyBytes; 1741 assert(tsoDescBytesUsed <= TxdOp::getLen(desc)); 1742 } else { 1743 igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)), 1744 TxdOp::getLen(desc), &pktEvent, p->data + p->length, 1745 igbe->txReadDelay); 1746 } 1747} 1748 1749void 1750IGbE::TxDescCache::pktComplete() 1751{ 1752 1753 TxDesc *desc; 1754 assert(unusedCache.size()); 1755 assert(pktPtr); 1756 1757 igbe->anBegin("TXS", "Update Desc"); 1758 1759 DPRINTF(EthernetDesc, "DMA of packet complete\n"); 1760 1761 1762 desc = unusedCache.front(); 1763 assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && 1764 TxdOp::getLen(desc)); 1765 1766 DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", 1767 desc->d1, desc->d2); 1768 1769 // Set the length of the data in the EtherPacket 1770 if (useTso) { 1771 DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d " 1772 "used: %d loaded hdr: %d\n", useTso, tsoHeaderLen, tsoMss, 1773 tsoTotalLen, tsoUsedLen, tsoLoadedHeader); 1774 pktPtr->length += tsoCopyBytes; 1775 tsoUsedLen += tsoCopyBytes; 1776 DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d\n", 1777 tsoDescBytesUsed, tsoCopyBytes); 1778 } else 1779 pktPtr->length += TxdOp::getLen(desc); 1780 1781 1782 1783 if ((!TxdOp::eop(desc) && !useTso) || 1784 (pktPtr->length < ( tsoMss + tsoHeaderLen) && 1785 tsoTotalLen != tsoUsedLen && useTso)) { 1786 assert(!useTso || (tsoDescBytesUsed == TxdOp::getLen(desc))); 1787 igbe->anDq("TXS", annUnusedCacheQ); 1788 unusedCache.pop_front(); 1789 igbe->anQ("TXS", annUsedCacheQ); 1790 usedCache.push_back(desc); 1791 1792 tsoDescBytesUsed = 0; 1793 pktDone = true; 1794 pktWaiting = false; 1795 pktMultiDesc = true; 1796 1797 DPRINTF(EthernetDesc, "Partial Packet Descriptor of %d bytes Done\n", 1798 pktPtr->length); 1799 pktPtr = NULL; 1800 1801 enableSm(); 1802 igbe->checkDrain(); 1803 return; 1804 } 1805 1806 1807 pktMultiDesc = false; 1808 // no support for vlans 1809 assert(!TxdOp::vle(desc)); 1810 1811 // we only support single packet descriptors at this point 1812 if (!useTso) 1813 assert(TxdOp::eop(desc)); 1814 1815 // set that this packet is done 1816 if (TxdOp::rs(desc)) 1817 TxdOp::setDd(desc); 1818 1819 DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", 1820 desc->d1, desc->d2); 1821 1822 if (useTso) { 1823 IpPtr ip(pktPtr); 1824 if (ip) { 1825 DPRINTF(EthernetDesc, "TSO: Modifying IP header. Id + %d\n", 1826 tsoPkts); 1827 ip->id(ip->id() + tsoPkts++); 1828 ip->len(pktPtr->length - EthPtr(pktPtr)->size()); 1829 1830 TcpPtr tcp(ip); 1831 if (tcp) { 1832 DPRINTF(EthernetDesc, 1833 "TSO: Modifying TCP header. old seq %d + %d\n", 1834 tcp->seq(), tsoPrevSeq); 1835 tcp->seq(tcp->seq() + tsoPrevSeq); 1836 if (tsoUsedLen != tsoTotalLen) 1837 tcp->flags(tcp->flags() & ~9); // clear fin & psh 1838 } 1839 UdpPtr udp(ip); 1840 if (udp) { 1841 DPRINTF(EthernetDesc, "TSO: Modifying UDP header.\n"); 1842 udp->len(pktPtr->length - EthPtr(pktPtr)->size()); 1843 } 1844 } 1845 tsoPrevSeq = tsoUsedLen; 1846 } 1847 1848 if (DTRACE(EthernetDesc)) { 1849 IpPtr ip(pktPtr); 1850 if (ip) 1851 DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", 1852 ip->id()); 1853 else 1854 DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); 1855 } 1856 1857 // Checksums are only ofloaded for new descriptor types 1858 if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) { 1859 DPRINTF(EthernetDesc, "Calculating checksums for packet\n"); 1860 IpPtr ip(pktPtr); 1861 assert(ip); 1862 if (TxdOp::ixsm(desc)) { 1863 ip->sum(0); 1864 ip->sum(cksum(ip)); 1865 igbe->txIpChecksums++; 1866 DPRINTF(EthernetDesc, "Calculated IP checksum\n"); 1867 } 1868 if (TxdOp::txsm(desc)) { 1869 TcpPtr tcp(ip); 1870 UdpPtr udp(ip); 1871 if (tcp) { 1872 tcp->sum(0); 1873 tcp->sum(cksum(tcp)); 1874 igbe->txTcpChecksums++; 1875 DPRINTF(EthernetDesc, "Calculated TCP checksum\n"); 1876 } else if (udp) { 1877 assert(udp); 1878 udp->sum(0); 1879 udp->sum(cksum(udp)); 1880 igbe->txUdpChecksums++; 1881 DPRINTF(EthernetDesc, "Calculated UDP checksum\n"); 1882 } else { 1883 panic("Told to checksum, but don't know how\n"); 1884 } 1885 } 1886 } 1887 1888 if (TxdOp::ide(desc)) { 1889 // Deal with the rx timer interrupts 1890 DPRINTF(EthernetDesc, "Descriptor had IDE set\n"); 1891 if (igbe->regs.tidv.idv()) { 1892 Tick delay = igbe->regs.tidv.idv() * igbe->intClock(); 1893 DPRINTF(EthernetDesc, "setting tidv\n"); 1894 igbe->reschedule(igbe->tidvEvent, curTick() + delay, true); 1895 } 1896 1897 if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) { 1898 Tick delay = igbe->regs.tadv.idv() * igbe->intClock(); 1899 DPRINTF(EthernetDesc, "setting tadv\n"); 1900 if (!igbe->tadvEvent.scheduled()) { 1901 igbe->schedule(igbe->tadvEvent, curTick() + delay); 1902 } 1903 } 1904 } 1905 1906 1907 if (!useTso || TxdOp::getLen(desc) == tsoDescBytesUsed) { 1908 DPRINTF(EthernetDesc, "Descriptor Done\n"); 1909 igbe->anDq("TXS", annUnusedCacheQ); 1910 unusedCache.pop_front(); 1911 igbe->anQ("TXS", annUsedCacheQ); 1912 usedCache.push_back(desc); 1913 tsoDescBytesUsed = 0; 1914 } 1915 1916 if (useTso && tsoUsedLen == tsoTotalLen) 1917 useTso = false; 1918 1919 1920 DPRINTF(EthernetDesc, 1921 "------Packet of %d bytes ready for transmission-------\n", 1922 pktPtr->length); 1923 pktDone = true; 1924 pktWaiting = false; 1925 pktPtr = NULL; 1926 tsoPktHasHeader = false; 1927 1928 if (igbe->regs.txdctl.wthresh() == 0) { 1929 igbe->anBegin("TXS", "Desc Writeback"); 1930 DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n"); 1931 writeback(0); 1932 } else if (!igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() <= 1933 descInBlock(usedCache.size())) { 1934 DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); 1935 igbe->anBegin("TXS", "Desc Writeback"); 1936 writeback((igbe->cacheBlockSize()-1)>>4); 1937 } else if (igbe->regs.txdctl.wthresh() <= usedCache.size()) { 1938 DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); 1939 igbe->anBegin("TXS", "Desc Writeback"); 1940 writeback((igbe->cacheBlockSize()-1)>>4); 1941 } 1942 1943 enableSm(); 1944 igbe->checkDrain(); 1945} 1946 1947void 1948IGbE::TxDescCache::actionAfterWb() 1949{ 1950 DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n", 1951 completionEnabled); 1952 igbe->postInterrupt(iGbReg::IT_TXDW); 1953 if (completionEnabled) { 1954 descEnd = igbe->regs.tdh(); 1955 DPRINTF(EthernetDesc, 1956 "Completion writing back value: %d to addr: %#x\n", descEnd, 1957 completionAddress); 1958 igbe->dmaWrite(pciToDma(mbits(completionAddress, 63, 2)), 1959 sizeof(descEnd), &nullEvent, (uint8_t*)&descEnd, 0); 1960 } 1961} 1962 1963void 1964IGbE::TxDescCache::serialize(std::ostream &os) 1965{ 1966 DescCache<TxDesc>::serialize(os); 1967 SERIALIZE_SCALAR(pktDone); 1968 SERIALIZE_SCALAR(isTcp); 1969 SERIALIZE_SCALAR(pktWaiting); 1970 SERIALIZE_SCALAR(pktMultiDesc); 1971 1972 SERIALIZE_SCALAR(useTso); 1973 SERIALIZE_SCALAR(tsoHeaderLen); 1974 SERIALIZE_SCALAR(tsoMss); 1975 SERIALIZE_SCALAR(tsoTotalLen); 1976 SERIALIZE_SCALAR(tsoUsedLen); 1977 SERIALIZE_SCALAR(tsoPrevSeq);; 1978 SERIALIZE_SCALAR(tsoPktPayloadBytes); 1979 SERIALIZE_SCALAR(tsoLoadedHeader); 1980 SERIALIZE_SCALAR(tsoPktHasHeader); 1981 SERIALIZE_ARRAY(tsoHeader, 256); 1982 SERIALIZE_SCALAR(tsoDescBytesUsed); 1983 SERIALIZE_SCALAR(tsoCopyBytes); 1984 SERIALIZE_SCALAR(tsoPkts); 1985 1986 SERIALIZE_SCALAR(completionAddress); 1987 SERIALIZE_SCALAR(completionEnabled); 1988 SERIALIZE_SCALAR(descEnd); 1989} 1990 1991void 1992IGbE::TxDescCache::unserialize(Checkpoint *cp, const std::string §ion) 1993{ 1994 DescCache<TxDesc>::unserialize(cp, section); 1995 UNSERIALIZE_SCALAR(pktDone); 1996 UNSERIALIZE_SCALAR(isTcp); 1997 UNSERIALIZE_SCALAR(pktWaiting); 1998 UNSERIALIZE_SCALAR(pktMultiDesc); 1999 2000 UNSERIALIZE_SCALAR(useTso); 2001 UNSERIALIZE_SCALAR(tsoHeaderLen); 2002 UNSERIALIZE_SCALAR(tsoMss); 2003 UNSERIALIZE_SCALAR(tsoTotalLen); 2004 UNSERIALIZE_SCALAR(tsoUsedLen); 2005 UNSERIALIZE_SCALAR(tsoPrevSeq);; 2006 UNSERIALIZE_SCALAR(tsoPktPayloadBytes); 2007 UNSERIALIZE_SCALAR(tsoLoadedHeader); 2008 UNSERIALIZE_SCALAR(tsoPktHasHeader); 2009 UNSERIALIZE_ARRAY(tsoHeader, 256); 2010 UNSERIALIZE_SCALAR(tsoDescBytesUsed); 2011 UNSERIALIZE_SCALAR(tsoCopyBytes); 2012 UNSERIALIZE_SCALAR(tsoPkts); 2013 2014 UNSERIALIZE_SCALAR(completionAddress); 2015 UNSERIALIZE_SCALAR(completionEnabled); 2016 UNSERIALIZE_SCALAR(descEnd); 2017} 2018 2019bool 2020IGbE::TxDescCache::packetAvailable() 2021{ 2022 if (pktDone) { 2023 pktDone = false; 2024 return true; 2025 } 2026 return false; 2027} 2028 2029void 2030IGbE::TxDescCache::enableSm() 2031{ 2032 if (!igbe->drainEvent) { 2033 igbe->txTick = true; 2034 igbe->restartClock(); 2035 } 2036} 2037 2038bool 2039IGbE::TxDescCache::hasOutstandingEvents() 2040{ 2041 return pktEvent.scheduled() || wbEvent.scheduled() || 2042 fetchEvent.scheduled(); 2043} 2044 2045 2046///////////////////////////////////// IGbE ///////////////////////////////// 2047 2048void 2049IGbE::restartClock() 2050{ 2051 if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && 2052 getState() == SimObject::Running) 2053 schedule(tickEvent, clockEdge(Cycles(1))); 2054} 2055 2056unsigned int 2057IGbE::drain(Event *de) 2058{ 2059 unsigned int count; 2060 count = pioPort.drain(de) + dmaPort.drain(de); 2061 if (rxDescCache.hasOutstandingEvents() || 2062 txDescCache.hasOutstandingEvents()) { 2063 count++; 2064 drainEvent = de; 2065 } 2066 2067 txFifoTick = false; 2068 txTick = false; 2069 rxTick = false; 2070 2071 if (tickEvent.scheduled()) 2072 deschedule(tickEvent); 2073 2074 if (count) { 2075 DPRINTF(Drain, "IGbE not drained\n"); 2076 changeState(Draining); 2077 } else 2078 changeState(Drained); 2079 2080 return count; 2081} 2082 2083void 2084IGbE::resume() 2085{ 2086 SimObject::resume(); 2087 2088 txFifoTick = true; 2089 txTick = true; 2090 rxTick = true; 2091 2092 restartClock(); 2093 DPRINTF(EthernetSM, "resuming from drain"); 2094} 2095 2096void 2097IGbE::checkDrain() 2098{ 2099 if (!drainEvent) 2100 return; 2101 2102 txFifoTick = false; 2103 txTick = false; 2104 rxTick = false; 2105 if (!rxDescCache.hasOutstandingEvents() && 2106 !txDescCache.hasOutstandingEvents()) { 2107 DPRINTF(Drain, "IGbE done draining, processing drain event\n"); 2108 drainEvent->process(); 2109 drainEvent = NULL; 2110 } 2111} 2112 2113void 2114IGbE::txStateMachine() 2115{ 2116 if (!regs.tctl.en()) { 2117 txTick = false; 2118 DPRINTF(EthernetSM, "TXS: TX disabled, stopping ticking\n"); 2119 return; 2120 } 2121 2122 // If we have a packet available and it's length is not 0 (meaning it's not 2123 // a multidescriptor packet) put it in the fifo, otherwise an the next 2124 // iteration we'll get the rest of the data 2125 if (txPacket && txDescCache.packetAvailable() 2126 && !txDescCache.packetMultiDesc() && txPacket->length) { 2127 anQ("TXS", "TX FIFO Q"); 2128 DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n"); 2129#ifndef NDEBUG 2130 bool success = 2131#endif 2132 txFifo.push(txPacket); 2133 txFifoTick = true && !drainEvent; 2134 assert(success); 2135 txPacket = NULL; 2136 anBegin("TXS", "Desc Writeback"); 2137 txDescCache.writeback((cacheBlockSize()-1)>>4); 2138 return; 2139 } 2140 2141 // Only support descriptor granularity 2142 if (regs.txdctl.lwthresh() && 2143 txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) { 2144 DPRINTF(EthernetSM, "TXS: LWTHRESH caused posting of TXDLOW\n"); 2145 postInterrupt(IT_TXDLOW); 2146 } 2147 2148 if (!txPacket) { 2149 txPacket = new EthPacketData(16384); 2150 } 2151 2152 if (!txDescCache.packetWaiting()) { 2153 if (txDescCache.descLeft() == 0) { 2154 postInterrupt(IT_TXQE); 2155 anBegin("TXS", "Desc Writeback"); 2156 txDescCache.writeback(0); 2157 anBegin("TXS", "Desc Fetch"); 2158 anWe("TXS", txDescCache.annUnusedCacheQ); 2159 txDescCache.fetchDescriptors(); 2160 DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing " 2161 "writeback stopping ticking and posting TXQE\n"); 2162 txTick = false; 2163 return; 2164 } 2165 2166 2167 if (!(txDescCache.descUnused())) { 2168 anBegin("TXS", "Desc Fetch"); 2169 txDescCache.fetchDescriptors(); 2170 anWe("TXS", txDescCache.annUnusedCacheQ); 2171 DPRINTF(EthernetSM, "TXS: No descriptors available in cache, " 2172 "fetching and stopping ticking\n"); 2173 txTick = false; 2174 return; 2175 } 2176 anPq("TXS", txDescCache.annUnusedCacheQ); 2177 2178 2179 txDescCache.processContextDesc(); 2180 if (txDescCache.packetWaiting()) { 2181 DPRINTF(EthernetSM, 2182 "TXS: Fetching TSO header, stopping ticking\n"); 2183 txTick = false; 2184 return; 2185 } 2186 2187 unsigned size = txDescCache.getPacketSize(txPacket); 2188 if (size > 0 && txFifo.avail() > size) { 2189 anRq("TXS", "TX FIFO Q"); 2190 anBegin("TXS", "DMA Packet"); 2191 DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and " 2192 "beginning DMA of next packet\n", size); 2193 txFifo.reserve(size); 2194 txDescCache.getPacketData(txPacket); 2195 } else if (size == 0) { 2196 DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size); 2197 DPRINTF(EthernetSM, 2198 "TXS: No packets to get, writing back used descriptors\n"); 2199 anBegin("TXS", "Desc Writeback"); 2200 txDescCache.writeback(0); 2201 } else { 2202 anWf("TXS", "TX FIFO Q"); 2203 DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space " 2204 "available in FIFO\n"); 2205 txTick = false; 2206 } 2207 2208 2209 return; 2210 } 2211 DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n"); 2212 txTick = false; 2213} 2214 2215bool 2216IGbE::ethRxPkt(EthPacketPtr pkt) 2217{ 2218 rxBytes += pkt->length; 2219 rxPackets++; 2220 2221 DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n"); 2222 anBegin("RXQ", "Wire Recv"); 2223 2224 2225 if (!regs.rctl.en()) { 2226 DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n"); 2227 anBegin("RXQ", "FIFO Drop", CPA::FL_BAD); 2228 return true; 2229 } 2230 2231 // restart the state machines if they are stopped 2232 rxTick = true && !drainEvent; 2233 if ((rxTick || txTick) && !tickEvent.scheduled()) { 2234 DPRINTF(EthernetSM, 2235 "RXS: received packet into fifo, starting ticking\n"); 2236 restartClock(); 2237 } 2238 2239 if (!rxFifo.push(pkt)) { 2240 DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n"); 2241 postInterrupt(IT_RXO, true); 2242 anBegin("RXQ", "FIFO Drop", CPA::FL_BAD); 2243 return false; 2244 } 2245 2246 if (CPA::available() && cpa->enabled()) { 2247 assert(sys->numSystemsRunning <= 2); 2248 System *other_sys; 2249 if (sys->systemList[0] == sys) 2250 other_sys = sys->systemList[1]; 2251 else 2252 other_sys = sys->systemList[0]; 2253 2254 cpa->hwDq(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys); 2255 anQ("RXQ", "RX FIFO Q"); 2256 cpa->hwWe(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys); 2257 } 2258 2259 return true; 2260} 2261 2262 2263void 2264IGbE::rxStateMachine() 2265{ 2266 if (!regs.rctl.en()) { 2267 rxTick = false; 2268 DPRINTF(EthernetSM, "RXS: RX disabled, stopping ticking\n"); 2269 return; 2270 } 2271 2272 // If the packet is done check for interrupts/descriptors/etc 2273 if (rxDescCache.packetDone()) { 2274 rxDmaPacket = false; 2275 DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n"); 2276 int descLeft = rxDescCache.descLeft(); 2277 DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n", 2278 descLeft, regs.rctl.rdmts(), regs.rdlen()); 2279 switch (regs.rctl.rdmts()) { 2280 case 2: if (descLeft > .125 * regs.rdlen()) break; 2281 case 1: if (descLeft > .250 * regs.rdlen()) break; 2282 case 0: if (descLeft > .500 * regs.rdlen()) break; 2283 DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) " 2284 "because of descriptors left\n"); 2285 postInterrupt(IT_RXDMT); 2286 break; 2287 } 2288 2289 if (rxFifo.empty()) 2290 rxDescCache.writeback(0); 2291 2292 if (descLeft == 0) { 2293 anBegin("RXS", "Writeback Descriptors"); 2294 rxDescCache.writeback(0); 2295 DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing" 2296 " writeback and stopping ticking\n"); 2297 rxTick = false; 2298 } 2299 2300 // only support descriptor granulaties 2301 assert(regs.rxdctl.gran()); 2302 2303 if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) { 2304 DPRINTF(EthernetSM, 2305 "RXS: Writing back because WTHRESH >= descUsed\n"); 2306 anBegin("RXS", "Writeback Descriptors"); 2307 if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4)) 2308 rxDescCache.writeback(regs.rxdctl.wthresh()-1); 2309 else 2310 rxDescCache.writeback((cacheBlockSize()-1)>>4); 2311 } 2312 2313 if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) && 2314 ((rxDescCache.descLeft() - rxDescCache.descUnused()) > 2315 regs.rxdctl.hthresh())) { 2316 DPRINTF(EthernetSM, "RXS: Fetching descriptors because " 2317 "descUnused < PTHRESH\n"); 2318 anBegin("RXS", "Fetch Descriptors"); 2319 rxDescCache.fetchDescriptors(); 2320 } 2321 2322 if (rxDescCache.descUnused() == 0) { 2323 anBegin("RXS", "Fetch Descriptors"); 2324 rxDescCache.fetchDescriptors(); 2325 anWe("RXS", rxDescCache.annUnusedCacheQ); 2326 DPRINTF(EthernetSM, "RXS: No descriptors available in cache, " 2327 "fetching descriptors and stopping ticking\n"); 2328 rxTick = false; 2329 } 2330 return; 2331 } 2332 2333 if (rxDmaPacket) { 2334 DPRINTF(EthernetSM, 2335 "RXS: stopping ticking until packet DMA completes\n"); 2336 rxTick = false; 2337 return; 2338 } 2339 2340 if (!rxDescCache.descUnused()) { 2341 anBegin("RXS", "Fetch Descriptors"); 2342 rxDescCache.fetchDescriptors(); 2343 anWe("RXS", rxDescCache.annUnusedCacheQ); 2344 DPRINTF(EthernetSM, "RXS: No descriptors available in cache, " 2345 "stopping ticking\n"); 2346 rxTick = false; 2347 DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n"); 2348 return; 2349 } 2350 anPq("RXS", rxDescCache.annUnusedCacheQ); 2351 2352 if (rxFifo.empty()) { 2353 anWe("RXS", "RX FIFO Q"); 2354 DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n"); 2355 rxTick = false; 2356 return; 2357 } 2358 anPq("RXS", "RX FIFO Q"); 2359 anBegin("RXS", "Get Desc"); 2360 2361 EthPacketPtr pkt; 2362 pkt = rxFifo.front(); 2363 2364 2365 pktOffset = rxDescCache.writePacket(pkt, pktOffset); 2366 DPRINTF(EthernetSM, "RXS: Writing packet into memory\n"); 2367 if (pktOffset == pkt->length) { 2368 anBegin( "RXS", "FIFO Dequeue"); 2369 DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n"); 2370 pktOffset = 0; 2371 anDq("RXS", "RX FIFO Q"); 2372 rxFifo.pop(); 2373 } 2374 2375 DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); 2376 rxTick = false; 2377 rxDmaPacket = true; 2378 anBegin("RXS", "DMA Packet"); 2379} 2380 2381void 2382IGbE::txWire() 2383{ 2384 if (txFifo.empty()) { 2385 anWe("TXQ", "TX FIFO Q"); 2386 txFifoTick = false; 2387 return; 2388 } 2389 2390 2391 anPq("TXQ", "TX FIFO Q"); 2392 if (etherInt->sendPacket(txFifo.front())) { 2393 cpa->hwQ(CPA::FL_NONE, sys, macAddr, "TXQ", "WireQ", 0); 2394 if (DTRACE(EthernetSM)) { 2395 IpPtr ip(txFifo.front()); 2396 if (ip) 2397 DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n", 2398 ip->id()); 2399 else 2400 DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n"); 2401 } 2402 anDq("TXQ", "TX FIFO Q"); 2403 anBegin("TXQ", "Wire Send"); 2404 DPRINTF(EthernetSM, 2405 "TxFIFO: Successful transmit, bytes available in fifo: %d\n", 2406 txFifo.avail()); 2407 2408 txBytes += txFifo.front()->length; 2409 txPackets++; 2410 txFifoTick = false; 2411 2412 txFifo.pop(); 2413 } else { 2414 // We'll get woken up when the packet ethTxDone() gets called 2415 txFifoTick = false; 2416 } 2417} 2418 2419void 2420IGbE::tick() 2421{ 2422 DPRINTF(EthernetSM, "IGbE: -------------- Cycle --------------\n"); 2423 2424 if (rxTick) 2425 rxStateMachine(); 2426 2427 if (txTick) 2428 txStateMachine(); 2429 2430 if (txFifoTick) 2431 txWire(); 2432 2433 2434 if (rxTick || txTick || txFifoTick) 2435 schedule(tickEvent, curTick() + clockPeriod()); 2436} 2437 2438void 2439IGbE::ethTxDone() 2440{ 2441 anBegin("TXQ", "Send Done"); 2442 // restart the tx state machines if they are stopped 2443 // fifo to send another packet 2444 // tx sm to put more data into the fifo 2445 txFifoTick = true && !drainEvent; 2446 if (txDescCache.descLeft() != 0 && !drainEvent) 2447 txTick = true; 2448 2449 restartClock(); 2450 txWire(); 2451 DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n"); 2452} 2453 2454void 2455IGbE::serialize(std::ostream &os) 2456{ 2457 PciDev::serialize(os); 2458 2459 regs.serialize(os); 2460 SERIALIZE_SCALAR(eeOpBits); 2461 SERIALIZE_SCALAR(eeAddrBits); 2462 SERIALIZE_SCALAR(eeDataBits); 2463 SERIALIZE_SCALAR(eeOpcode); 2464 SERIALIZE_SCALAR(eeAddr); 2465 SERIALIZE_SCALAR(lastInterrupt); 2466 SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE); 2467 2468 rxFifo.serialize("rxfifo", os); 2469 txFifo.serialize("txfifo", os); 2470 2471 bool txPktExists = txPacket; 2472 SERIALIZE_SCALAR(txPktExists); 2473 if (txPktExists) 2474 txPacket->serialize("txpacket", os); 2475 2476 Tick rdtr_time = 0, radv_time = 0, tidv_time = 0, tadv_time = 0, 2477 inter_time = 0; 2478 2479 if (rdtrEvent.scheduled()) 2480 rdtr_time = rdtrEvent.when(); 2481 SERIALIZE_SCALAR(rdtr_time); 2482 2483 if (radvEvent.scheduled()) 2484 radv_time = radvEvent.when(); 2485 SERIALIZE_SCALAR(radv_time); 2486 2487 if (tidvEvent.scheduled()) 2488 tidv_time = tidvEvent.when(); 2489 SERIALIZE_SCALAR(tidv_time); 2490 2491 if (tadvEvent.scheduled()) 2492 tadv_time = tadvEvent.when(); 2493 SERIALIZE_SCALAR(tadv_time); 2494 2495 if (interEvent.scheduled()) 2496 inter_time = interEvent.when(); 2497 SERIALIZE_SCALAR(inter_time); 2498 2499 SERIALIZE_SCALAR(pktOffset); 2500 2501 nameOut(os, csprintf("%s.TxDescCache", name())); 2502 txDescCache.serialize(os); 2503 2504 nameOut(os, csprintf("%s.RxDescCache", name())); 2505 rxDescCache.serialize(os); 2506} 2507 2508void 2509IGbE::unserialize(Checkpoint *cp, const std::string §ion) 2510{ 2511 PciDev::unserialize(cp, section); 2512 2513 regs.unserialize(cp, section); 2514 UNSERIALIZE_SCALAR(eeOpBits); 2515 UNSERIALIZE_SCALAR(eeAddrBits); 2516 UNSERIALIZE_SCALAR(eeDataBits); 2517 UNSERIALIZE_SCALAR(eeOpcode); 2518 UNSERIALIZE_SCALAR(eeAddr); 2519 UNSERIALIZE_SCALAR(lastInterrupt); 2520 UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE); 2521 2522 rxFifo.unserialize("rxfifo", cp, section); 2523 txFifo.unserialize("txfifo", cp, section); 2524 2525 bool txPktExists; 2526 UNSERIALIZE_SCALAR(txPktExists); 2527 if (txPktExists) { 2528 txPacket = new EthPacketData(16384); 2529 txPacket->unserialize("txpacket", cp, section); 2530 } 2531 2532 rxTick = true; 2533 txTick = true; 2534 txFifoTick = true; 2535 2536 Tick rdtr_time, radv_time, tidv_time, tadv_time, inter_time; 2537 UNSERIALIZE_SCALAR(rdtr_time); 2538 UNSERIALIZE_SCALAR(radv_time); 2539 UNSERIALIZE_SCALAR(tidv_time); 2540 UNSERIALIZE_SCALAR(tadv_time); 2541 UNSERIALIZE_SCALAR(inter_time); 2542 2543 if (rdtr_time) 2544 schedule(rdtrEvent, rdtr_time); 2545 2546 if (radv_time) 2547 schedule(radvEvent, radv_time); 2548 2549 if (tidv_time) 2550 schedule(tidvEvent, tidv_time); 2551 2552 if (tadv_time) 2553 schedule(tadvEvent, tadv_time); 2554 2555 if (inter_time) 2556 schedule(interEvent, inter_time); 2557 2558 UNSERIALIZE_SCALAR(pktOffset); 2559 2560 txDescCache.unserialize(cp, csprintf("%s.TxDescCache", section)); 2561 2562 rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section)); 2563} 2564 2565IGbE * 2566IGbEParams::create() 2567{ 2568 return new IGbE(this); 2569} 2570