i8254xGBe.cc revision 9180
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com/* @file 3211793Sbrandon.potter@amd.com * Device model for Intel's 8254x line of gigabit ethernet controllers. 333918Ssaidi@eecs.umich.edu * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the 343918Ssaidi@eecs.umich.edu * fewest workarounds in the driver. It will probably work with most of the 353804Ssaidi@eecs.umich.edu * other MACs with slight modifications. 367678Sgblack@eecs.umich.edu */ 3713912Sgabeblack@google.com 386335Sgblack@eecs.umich.edu 393824Ssaidi@eecs.umich.edu/* 4012620Sgabeblack@google.com * @todo really there are multiple dma engines.. we should implement them. 413811Ssaidi@eecs.umich.edu */ 428229Snate@binkert.org 433811Ssaidi@eecs.umich.edu#include <algorithm> 448232Snate@binkert.org 458232Snate@binkert.org#include "base/inet.hh" 463823Ssaidi@eecs.umich.edu#include "base/trace.hh" 473823Ssaidi@eecs.umich.edu#include "debug/Drain.hh" 488751Sgblack@eecs.umich.edu#include "debug/EthernetAll.hh" 494103Ssaidi@eecs.umich.edu#include "dev/i8254xGBe.hh" 503569Sgblack@eecs.umich.edu#include "mem/packet.hh" 513804Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 523804Ssaidi@eecs.umich.edu#include "params/IGbE.hh" 534088Sbinkertn@umich.edu#include "sim/stats.hh" 543569Sgblack@eecs.umich.edu#include "sim/system.hh" 555034Smilesck@eecs.umich.edu 565358Sgblack@eecs.umich.eduusing namespace iGbReg; 578374Sksewell@umich.eduusing namespace Net; 583804Ssaidi@eecs.umich.edu 593804Ssaidi@eecs.umich.eduIGbE::IGbE(const Params *p) 603804Ssaidi@eecs.umich.edu : EtherDevice(p), etherInt(NULL), drainEvent(NULL), 615555Snate@binkert.org useFlowControl(p->use_flow_control), 623569Sgblack@eecs.umich.edu rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false), 633804Ssaidi@eecs.umich.edu txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0), 643918Ssaidi@eecs.umich.edu fetchDelay(p->fetch_delay), wbDelay(p->wb_delay), 653881Ssaidi@eecs.umich.edu fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay), 663881Ssaidi@eecs.umich.edu rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay), 673881Ssaidi@eecs.umich.edu rdtrEvent(this), radvEvent(this), 684990Sgblack@eecs.umich.edu tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this), 694990Sgblack@eecs.umich.edu rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size), 704990Sgblack@eecs.umich.edu txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), 714990Sgblack@eecs.umich.edu lastInterrupt(0) 724990Sgblack@eecs.umich.edu{ 734990Sgblack@eecs.umich.edu etherInt = new IGbEInt(name() + ".int", this); 744990Sgblack@eecs.umich.edu 754990Sgblack@eecs.umich.edu // Initialized internal registers per Intel documentation 764990Sgblack@eecs.umich.edu // All registers intialized to 0 by per register constructor 776022Sgblack@eecs.umich.edu regs.ctrl.fd(1); 786022Sgblack@eecs.umich.edu regs.ctrl.lrst(1); 796022Sgblack@eecs.umich.edu regs.ctrl.speed(2); 803804Ssaidi@eecs.umich.edu regs.ctrl.frcspd(1); 813569Sgblack@eecs.umich.edu regs.sts.speed(3); // Say we're 1000Mbps 823804Ssaidi@eecs.umich.edu regs.sts.fd(1); // full duplex 833804Ssaidi@eecs.umich.edu regs.sts.lu(1); // link up 843804Ssaidi@eecs.umich.edu regs.eecd.fwe(1); 853804Ssaidi@eecs.umich.edu regs.eecd.ee_type(1); 863881Ssaidi@eecs.umich.edu regs.imr = 0; 873804Ssaidi@eecs.umich.edu regs.iam = 0; 883804Ssaidi@eecs.umich.edu regs.rxdctl.gran(1); 893804Ssaidi@eecs.umich.edu regs.rxdctl.wthresh(1); 903804Ssaidi@eecs.umich.edu regs.fcrth(1); 913804Ssaidi@eecs.umich.edu regs.tdwba = 0; 923804Ssaidi@eecs.umich.edu regs.rlpml = 0; 933804Ssaidi@eecs.umich.edu regs.sw_fw_sync = 0; 943569Sgblack@eecs.umich.edu 953569Sgblack@eecs.umich.edu regs.pba.rxa(0x30); 963804Ssaidi@eecs.umich.edu regs.pba.txa(0x10); 973804Ssaidi@eecs.umich.edu 983826Ssaidi@eecs.umich.edu eeOpBits = 0; 993804Ssaidi@eecs.umich.edu eeAddrBits = 0; 1003804Ssaidi@eecs.umich.edu eeDataBits = 0; 1013826Ssaidi@eecs.umich.edu eeOpcode = 0; 1023907Ssaidi@eecs.umich.edu 1033826Ssaidi@eecs.umich.edu // clear all 64 16 bit words of the eeprom 1043811Ssaidi@eecs.umich.edu memset(&flash, 0, EEPROM_SIZE*2); 1053836Ssaidi@eecs.umich.edu 1063915Ssaidi@eecs.umich.edu // Set the MAC address 1073907Ssaidi@eecs.umich.edu memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN); 1083881Ssaidi@eecs.umich.edu for (int x = 0; x < ETH_ADDR_LEN/2; x++) 1093881Ssaidi@eecs.umich.edu flash[x] = htobe(flash[x]); 1103881Ssaidi@eecs.umich.edu 1113881Ssaidi@eecs.umich.edu uint16_t csum = 0; 1123907Ssaidi@eecs.umich.edu for (int x = 0; x < EEPROM_SIZE; x++) 1133881Ssaidi@eecs.umich.edu csum += htobe(flash[x]); 1145555Snate@binkert.org 1155555Snate@binkert.org 1165555Snate@binkert.org // Magic happy checksum value 1173881Ssaidi@eecs.umich.edu flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum)); 1183881Ssaidi@eecs.umich.edu 1193907Ssaidi@eecs.umich.edu // Store the MAC address as queue ID 1203907Ssaidi@eecs.umich.edu macAddr = p->hardware_address; 1213907Ssaidi@eecs.umich.edu 1223907Ssaidi@eecs.umich.edu rxFifo.clear(); 1233907Ssaidi@eecs.umich.edu txFifo.clear(); 1243907Ssaidi@eecs.umich.edu} 1253907Ssaidi@eecs.umich.edu 1263907Ssaidi@eecs.umich.eduIGbE::~IGbE() 1273907Ssaidi@eecs.umich.edu{ 1283907Ssaidi@eecs.umich.edu delete etherInt; 1293907Ssaidi@eecs.umich.edu} 1303907Ssaidi@eecs.umich.edu 1313907Ssaidi@eecs.umich.eduvoid 1323907Ssaidi@eecs.umich.eduIGbE::init() 1333907Ssaidi@eecs.umich.edu{ 1343907Ssaidi@eecs.umich.edu cpa = CPA::cpa(); 1353907Ssaidi@eecs.umich.edu PciDev::init(); 1363907Ssaidi@eecs.umich.edu} 1373907Ssaidi@eecs.umich.edu 1383907Ssaidi@eecs.umich.eduEtherInt* 1393907Ssaidi@eecs.umich.eduIGbE::getEthPort(const std::string &if_name, int idx) 1403826Ssaidi@eecs.umich.edu{ 1413826Ssaidi@eecs.umich.edu 1423826Ssaidi@eecs.umich.edu if (if_name == "interface") { 1433826Ssaidi@eecs.umich.edu if (etherInt->getPeer()) 1443881Ssaidi@eecs.umich.edu panic("Port already connected to\n"); 1453881Ssaidi@eecs.umich.edu return etherInt; 1463881Ssaidi@eecs.umich.edu } 1473881Ssaidi@eecs.umich.edu return NULL; 1483881Ssaidi@eecs.umich.edu} 1493881Ssaidi@eecs.umich.edu 1503881Ssaidi@eecs.umich.eduTick 1513881Ssaidi@eecs.umich.eduIGbE::writeConfig(PacketPtr pkt) 1523881Ssaidi@eecs.umich.edu{ 1533881Ssaidi@eecs.umich.edu int offset = pkt->getAddr() & PCI_CONFIG_SIZE; 1543881Ssaidi@eecs.umich.edu if (offset < PCI_DEVICE_SPECIFIC) 1553881Ssaidi@eecs.umich.edu PciDev::writeConfig(pkt); 1563881Ssaidi@eecs.umich.edu else 1573881Ssaidi@eecs.umich.edu panic("Device specific PCI config space not implemented.\n"); 1583569Sgblack@eecs.umich.edu 1593569Sgblack@eecs.umich.edu // 1603881Ssaidi@eecs.umich.edu // Some work may need to be done here based for the pci COMMAND bits. 1613804Ssaidi@eecs.umich.edu // 1623881Ssaidi@eecs.umich.edu 1633826Ssaidi@eecs.umich.edu return pioDelay; 1643881Ssaidi@eecs.umich.edu} 1653881Ssaidi@eecs.umich.edu 1663881Ssaidi@eecs.umich.edu// Handy macro for range-testing register access addresses 1673907Ssaidi@eecs.umich.edu#define IN_RANGE(val, base, len) (val >= base && val < (base + len)) 1683907Ssaidi@eecs.umich.edu 1693929Ssaidi@eecs.umich.eduTick 1703929Ssaidi@eecs.umich.eduIGbE::read(PacketPtr pkt) 1713907Ssaidi@eecs.umich.edu{ 1723907Ssaidi@eecs.umich.edu int bar; 1733804Ssaidi@eecs.umich.edu Addr daddr; 1743804Ssaidi@eecs.umich.edu 1753881Ssaidi@eecs.umich.edu if (!getBAR(pkt->getAddr(), bar, daddr)) 1763804Ssaidi@eecs.umich.edu panic("Invalid PCI memory access to unmapped memory.\n"); 1773804Ssaidi@eecs.umich.edu 1783804Ssaidi@eecs.umich.edu // Only Memory register BAR is allowed 1793804Ssaidi@eecs.umich.edu assert(bar == 0); 1803804Ssaidi@eecs.umich.edu 1813804Ssaidi@eecs.umich.edu // Only 32bit accesses allowed 1823804Ssaidi@eecs.umich.edu assert(pkt->getSize() == 4); 1833569Sgblack@eecs.umich.edu 1843863Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Read device register %#X\n", daddr); 1853863Ssaidi@eecs.umich.edu 1863804Ssaidi@eecs.umich.edu pkt->allocate(); 1875555Snate@binkert.org 1885555Snate@binkert.org // 1893804Ssaidi@eecs.umich.edu // Handle read of register here 1903804Ssaidi@eecs.umich.edu // 1913804Ssaidi@eecs.umich.edu 1923804Ssaidi@eecs.umich.edu 1933804Ssaidi@eecs.umich.edu switch (daddr) { 1943569Sgblack@eecs.umich.edu case REG_CTRL: 1953804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.ctrl()); 1963804Ssaidi@eecs.umich.edu break; 1973804Ssaidi@eecs.umich.edu case REG_STATUS: 1985555Snate@binkert.org pkt->set<uint32_t>(regs.sts()); 1995555Snate@binkert.org break; 2003804Ssaidi@eecs.umich.edu case REG_EECD: 2013804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.eecd()); 2023804Ssaidi@eecs.umich.edu break; 2033804Ssaidi@eecs.umich.edu case REG_EERD: 2043804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.eerd()); 2053811Ssaidi@eecs.umich.edu break; 2063811Ssaidi@eecs.umich.edu case REG_CTRL_EXT: 2073804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.ctrl_ext()); 2083804Ssaidi@eecs.umich.edu break; 2095312Sgblack@eecs.umich.edu case REG_MDIC: 2103804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.mdic()); 2113804Ssaidi@eecs.umich.edu break; 2123804Ssaidi@eecs.umich.edu case REG_ICR: 2133804Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", 2143804Ssaidi@eecs.umich.edu regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame()); 2153804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.icr()); 2163804Ssaidi@eecs.umich.edu if (regs.icr.int_assert() || regs.imr == 0) { 2173811Ssaidi@eecs.umich.edu regs.icr = regs.icr() & ~mask(30); 2183804Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr()); 2193804Ssaidi@eecs.umich.edu } 2203804Ssaidi@eecs.umich.edu if (regs.ctrl_ext.iame() && regs.icr.int_assert()) 2213804Ssaidi@eecs.umich.edu regs.imr &= ~regs.iam; 2223804Ssaidi@eecs.umich.edu chkInterrupt(); 2233826Ssaidi@eecs.umich.edu break; 2243826Ssaidi@eecs.umich.edu case REG_EICR: 2254070Ssaidi@eecs.umich.edu // This is only useful for MSI, but the driver reads it every time 2265555Snate@binkert.org // Just don't do anything 2275555Snate@binkert.org pkt->set<uint32_t>(0); 2284070Ssaidi@eecs.umich.edu break; 2293804Ssaidi@eecs.umich.edu case REG_ITR: 2303804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.itr()); 2313804Ssaidi@eecs.umich.edu break; 2323804Ssaidi@eecs.umich.edu case REG_RCTL: 2333804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rctl()); 2343804Ssaidi@eecs.umich.edu break; 2353804Ssaidi@eecs.umich.edu case REG_FCTTV: 2363804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.fcttv()); 2373804Ssaidi@eecs.umich.edu break; 2383804Ssaidi@eecs.umich.edu case REG_TCTL: 2393804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tctl()); 2403804Ssaidi@eecs.umich.edu break; 2413826Ssaidi@eecs.umich.edu case REG_PBA: 2423826Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.pba()); 2433826Ssaidi@eecs.umich.edu break; 2443863Ssaidi@eecs.umich.edu case REG_WUC: 2453826Ssaidi@eecs.umich.edu case REG_LEDCTL: 2463826Ssaidi@eecs.umich.edu pkt->set<uint32_t>(0); // We don't care, so just return 0 2473826Ssaidi@eecs.umich.edu break; 2483826Ssaidi@eecs.umich.edu case REG_FCRTL: 2493826Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.fcrtl()); 2503826Ssaidi@eecs.umich.edu break; 2513826Ssaidi@eecs.umich.edu case REG_FCRTH: 2523826Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.fcrth()); 2533826Ssaidi@eecs.umich.edu break; 2543804Ssaidi@eecs.umich.edu case REG_RDBAL: 2553804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rdba.rdbal()); 2563804Ssaidi@eecs.umich.edu break; 2573804Ssaidi@eecs.umich.edu case REG_RDBAH: 2583804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rdba.rdbah()); 2593804Ssaidi@eecs.umich.edu break; 2603804Ssaidi@eecs.umich.edu case REG_RDLEN: 2613863Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rdlen()); 2623863Ssaidi@eecs.umich.edu break; 2633863Ssaidi@eecs.umich.edu case REG_SRRCTL: 2643836Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.srrctl()); 2653836Ssaidi@eecs.umich.edu break; 2663804Ssaidi@eecs.umich.edu case REG_RDH: 2673804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rdh()); 2685312Sgblack@eecs.umich.edu break; 2693804Ssaidi@eecs.umich.edu case REG_RDT: 2703804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rdt()); 2713804Ssaidi@eecs.umich.edu break; 2723804Ssaidi@eecs.umich.edu case REG_RDTR: 2733804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rdtr()); 2743804Ssaidi@eecs.umich.edu if (regs.rdtr.fpd()) { 2753804Ssaidi@eecs.umich.edu rxDescCache.writeback(0); 2763863Ssaidi@eecs.umich.edu DPRINTF(EthernetIntr, 2773804Ssaidi@eecs.umich.edu "Posting interrupt because of RDTR.FPD write\n"); 2783804Ssaidi@eecs.umich.edu postInterrupt(IT_RXT); 2793804Ssaidi@eecs.umich.edu regs.rdtr.fpd(0); 2803804Ssaidi@eecs.umich.edu } 2813804Ssaidi@eecs.umich.edu break; 2823881Ssaidi@eecs.umich.edu case REG_RXDCTL: 2833804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rxdctl()); 2843804Ssaidi@eecs.umich.edu break; 2853804Ssaidi@eecs.umich.edu case REG_RADV: 2863804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.radv()); 2873804Ssaidi@eecs.umich.edu break; 2883804Ssaidi@eecs.umich.edu case REG_TDBAL: 2893804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tdba.tdbal()); 2903863Ssaidi@eecs.umich.edu break; 2913863Ssaidi@eecs.umich.edu case REG_TDBAH: 2923836Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tdba.tdbah()); 2935555Snate@binkert.org break; 2943804Ssaidi@eecs.umich.edu case REG_TDLEN: 2953804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tdlen()); 29610231Ssteve.reinhardt@amd.com break; 2973881Ssaidi@eecs.umich.edu case REG_TDH: 2983881Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tdh()); 2993804Ssaidi@eecs.umich.edu break; 3003804Ssaidi@eecs.umich.edu case REG_TXDCA_CTL: 3013804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.txdca_ctl()); 3023804Ssaidi@eecs.umich.edu break; 3033804Ssaidi@eecs.umich.edu case REG_TDT: 3043804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tdt()); 3053804Ssaidi@eecs.umich.edu break; 3063804Ssaidi@eecs.umich.edu case REG_TIDV: 3073804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tidv()); 3083804Ssaidi@eecs.umich.edu break; 3093804Ssaidi@eecs.umich.edu case REG_TXDCTL: 3103804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.txdctl()); 3113804Ssaidi@eecs.umich.edu break; 3123863Ssaidi@eecs.umich.edu case REG_TADV: 3133836Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tadv()); 3145555Snate@binkert.org break; 3155288Sgblack@eecs.umich.edu case REG_TDWBAL: 3165288Sgblack@eecs.umich.edu pkt->set<uint32_t>(regs.tdwba & mask(32)); 3175288Sgblack@eecs.umich.edu break; 3183804Ssaidi@eecs.umich.edu case REG_TDWBAH: 3193804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.tdwba >> 32); 3203804Ssaidi@eecs.umich.edu break; 3213804Ssaidi@eecs.umich.edu case REG_RXCSUM: 3223804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rxcsum()); 3233804Ssaidi@eecs.umich.edu break; 3243804Ssaidi@eecs.umich.edu case REG_RLPML: 3253804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rlpml); 3263804Ssaidi@eecs.umich.edu break; 3273804Ssaidi@eecs.umich.edu case REG_RFCTL: 3283804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.rfctl()); 3299423SAndreas.Sandberg@arm.com break; 3303804Ssaidi@eecs.umich.edu case REG_MANC: 3313836Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.manc()); 3325555Snate@binkert.org break; 3333836Ssaidi@eecs.umich.edu case REG_SWSM: 3345555Snate@binkert.org pkt->set<uint32_t>(regs.swsm()); 33510231Ssteve.reinhardt@amd.com regs.swsm.smbi(1); 3363881Ssaidi@eecs.umich.edu break; 3373804Ssaidi@eecs.umich.edu case REG_FWSM: 3383907Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.fwsm()); 3393804Ssaidi@eecs.umich.edu break; 3403804Ssaidi@eecs.umich.edu case REG_SWFWSYNC: 3413804Ssaidi@eecs.umich.edu pkt->set<uint32_t>(regs.sw_fw_sync); 3423804Ssaidi@eecs.umich.edu break; 3433804Ssaidi@eecs.umich.edu default: 3445555Snate@binkert.org if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) && 3455555Snate@binkert.org !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) && 3463881Ssaidi@eecs.umich.edu !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4) && 3473881Ssaidi@eecs.umich.edu !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE)) 3483881Ssaidi@eecs.umich.edu panic("Read request to unknown register number: %#x\n", daddr); 3493804Ssaidi@eecs.umich.edu else 3503881Ssaidi@eecs.umich.edu pkt->set<uint32_t>(0); 3513881Ssaidi@eecs.umich.edu }; 3523881Ssaidi@eecs.umich.edu 3533881Ssaidi@eecs.umich.edu pkt->makeAtomicResponse(); 3543804Ssaidi@eecs.umich.edu return pioDelay; 3553804Ssaidi@eecs.umich.edu} 3563804Ssaidi@eecs.umich.edu 3575555Snate@binkert.orgTick 3585555Snate@binkert.orgIGbE::write(PacketPtr pkt) 3593804Ssaidi@eecs.umich.edu{ 3603804Ssaidi@eecs.umich.edu int bar; 3613881Ssaidi@eecs.umich.edu Addr daddr; 3623881Ssaidi@eecs.umich.edu 3633804Ssaidi@eecs.umich.edu 3643881Ssaidi@eecs.umich.edu if (!getBAR(pkt->getAddr(), bar, daddr)) 3653881Ssaidi@eecs.umich.edu panic("Invalid PCI memory access to unmapped memory.\n"); 3663881Ssaidi@eecs.umich.edu 3673804Ssaidi@eecs.umich.edu // Only Memory register BAR is allowed 3683804Ssaidi@eecs.umich.edu assert(bar == 0); 3693804Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edu // Only 32bit accesses allowed 3713804Ssaidi@eecs.umich.edu assert(pkt->getSize() == sizeof(uint32_t)); 3723804Ssaidi@eecs.umich.edu 3733804Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", 3743804Ssaidi@eecs.umich.edu daddr, pkt->get<uint32_t>()); 3753804Ssaidi@eecs.umich.edu 3763804Ssaidi@eecs.umich.edu // 3773804Ssaidi@eecs.umich.edu // Handle write of register here 3783804Ssaidi@eecs.umich.edu // 3793804Ssaidi@eecs.umich.edu uint32_t val = pkt->get<uint32_t>(); 3803804Ssaidi@eecs.umich.edu 3813804Ssaidi@eecs.umich.edu Regs::RCTL oldrctl; 3823804Ssaidi@eecs.umich.edu Regs::TCTL oldtctl; 3834990Sgblack@eecs.umich.edu 3843804Ssaidi@eecs.umich.edu switch (daddr) { 3853804Ssaidi@eecs.umich.edu case REG_CTRL: 3863804Ssaidi@eecs.umich.edu regs.ctrl = val; 3873804Ssaidi@eecs.umich.edu if (regs.ctrl.tfce()) 3883804Ssaidi@eecs.umich.edu warn("TX Flow control enabled, should implement\n"); 3893804Ssaidi@eecs.umich.edu if (regs.ctrl.rfce()) 3903804Ssaidi@eecs.umich.edu warn("RX Flow control enabled, should implement\n"); 3913804Ssaidi@eecs.umich.edu break; 3923804Ssaidi@eecs.umich.edu case REG_CTRL_EXT: 3933804Ssaidi@eecs.umich.edu regs.ctrl_ext = val; 3943804Ssaidi@eecs.umich.edu break; 3953804Ssaidi@eecs.umich.edu case REG_STATUS: 3963804Ssaidi@eecs.umich.edu regs.sts = val; 3973804Ssaidi@eecs.umich.edu break; 3983804Ssaidi@eecs.umich.edu case REG_EECD: 3993826Ssaidi@eecs.umich.edu int oldClk; 4004990Sgblack@eecs.umich.edu oldClk = regs.eecd.sk(); 4013826Ssaidi@eecs.umich.edu regs.eecd = val; 4023916Ssaidi@eecs.umich.edu // See if this is a eeprom access and emulate accordingly 4033916Ssaidi@eecs.umich.edu if (!oldClk && regs.eecd.sk()) { 4043916Ssaidi@eecs.umich.edu if (eeOpBits < 8) { 4054990Sgblack@eecs.umich.edu eeOpcode = eeOpcode << 1 | regs.eecd.din(); 4063826Ssaidi@eecs.umich.edu eeOpBits++; 4073804Ssaidi@eecs.umich.edu } else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) { 4083804Ssaidi@eecs.umich.edu eeAddr = eeAddr << 1 | regs.eecd.din(); 4096022Sgblack@eecs.umich.edu eeAddrBits++; 4103804Ssaidi@eecs.umich.edu } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) { 4113804Ssaidi@eecs.umich.edu assert(eeAddr>>1 < EEPROM_SIZE); 4126022Sgblack@eecs.umich.edu DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n", 4133811Ssaidi@eecs.umich.edu flash[eeAddr>>1] >> eeDataBits & 0x1, 4144990Sgblack@eecs.umich.edu flash[eeAddr>>1]); 4154990Sgblack@eecs.umich.edu regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1); 4163804Ssaidi@eecs.umich.edu eeDataBits++; 4173804Ssaidi@eecs.umich.edu } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) { 4183804Ssaidi@eecs.umich.edu regs.eecd.dout(0); 41912749Sgiacomo.travaglini@arm.com eeDataBits++; 4203804Ssaidi@eecs.umich.edu } else 4214172Ssaidi@eecs.umich.edu panic("What's going on with eeprom interface? opcode:" 4223833Ssaidi@eecs.umich.edu " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode, 4233836Ssaidi@eecs.umich.edu (uint32_t)eeOpBits, (uint32_t)eeAddr, 4243836Ssaidi@eecs.umich.edu (uint32_t)eeAddrBits, (uint32_t)eeDataBits); 4253836Ssaidi@eecs.umich.edu 4269912Sandreas@sandberg.pp.se // Reset everything for the next command 4273836Ssaidi@eecs.umich.edu if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) || 4283836Ssaidi@eecs.umich.edu (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) { 4293836Ssaidi@eecs.umich.edu eeOpBits = 0; 4303836Ssaidi@eecs.umich.edu eeAddrBits = 0; 4313836Ssaidi@eecs.umich.edu eeDataBits = 0; 4323836Ssaidi@eecs.umich.edu eeOpcode = 0; 4336022Sgblack@eecs.umich.edu eeAddr = 0; 4346022Sgblack@eecs.umich.edu } 4356022Sgblack@eecs.umich.edu 4366022Sgblack@eecs.umich.edu DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n", 4375555Snate@binkert.org (uint32_t)eeOpcode, (uint32_t) eeOpBits, 4383836Ssaidi@eecs.umich.edu (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits); 4393836Ssaidi@eecs.umich.edu if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI || 4403836Ssaidi@eecs.umich.edu eeOpcode == EEPROM_RDSR_OPCODE_SPI )) 4413836Ssaidi@eecs.umich.edu panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode, 4423836Ssaidi@eecs.umich.edu (uint32_t)eeOpBits); 4433836Ssaidi@eecs.umich.edu 4443836Ssaidi@eecs.umich.edu 4453833Ssaidi@eecs.umich.edu } 4463833Ssaidi@eecs.umich.edu // If driver requests eeprom access, immediately give it to it 4473833Ssaidi@eecs.umich.edu regs.eecd.ee_gnt(regs.eecd.ee_req()); 4483833Ssaidi@eecs.umich.edu break; 4493833Ssaidi@eecs.umich.edu case REG_EERD: 4503833Ssaidi@eecs.umich.edu regs.eerd = val; 4513833Ssaidi@eecs.umich.edu if (regs.eerd.start()) { 4523833Ssaidi@eecs.umich.edu regs.eerd.done(1); 4533833Ssaidi@eecs.umich.edu assert(regs.eerd.addr() < EEPROM_SIZE); 4543804Ssaidi@eecs.umich.edu regs.eerd.data(flash[regs.eerd.addr()]); 4553804Ssaidi@eecs.umich.edu regs.eerd.start(0); 4563804Ssaidi@eecs.umich.edu DPRINTF(EthernetEEPROM, "EEPROM: read addr: %#X data %#x\n", 4573804Ssaidi@eecs.umich.edu regs.eerd.addr(), regs.eerd.data()); 4583804Ssaidi@eecs.umich.edu } 4593833Ssaidi@eecs.umich.edu break; 4603833Ssaidi@eecs.umich.edu case REG_MDIC: 4613811Ssaidi@eecs.umich.edu regs.mdic = val; 4623804Ssaidi@eecs.umich.edu if (regs.mdic.i()) 4633804Ssaidi@eecs.umich.edu panic("No support for interrupt on mdic complete\n"); 4643804Ssaidi@eecs.umich.edu if (regs.mdic.phyadd() != 1) 4653804Ssaidi@eecs.umich.edu panic("No support for reading anything but phy\n"); 4663804Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "%s phy address %x\n", 4673804Ssaidi@eecs.umich.edu regs.mdic.op() == 1 ? "Writing" : "Reading", 4683804Ssaidi@eecs.umich.edu regs.mdic.regadd()); 4693833Ssaidi@eecs.umich.edu switch (regs.mdic.regadd()) { 4703804Ssaidi@eecs.umich.edu case PHY_PSTATUS: 4713804Ssaidi@eecs.umich.edu regs.mdic.data(0x796D); // link up 4723833Ssaidi@eecs.umich.edu break; 4733836Ssaidi@eecs.umich.edu case PHY_PID: 4743836Ssaidi@eecs.umich.edu regs.mdic.data(params()->phy_pid); 4756022Sgblack@eecs.umich.edu break; 4763836Ssaidi@eecs.umich.edu case PHY_EPID: 4773804Ssaidi@eecs.umich.edu regs.mdic.data(params()->phy_epid); 4783804Ssaidi@eecs.umich.edu break; 4793804Ssaidi@eecs.umich.edu case PHY_GSTATUS: 4803836Ssaidi@eecs.umich.edu regs.mdic.data(0x7C00); 4813836Ssaidi@eecs.umich.edu break; 4824990Sgblack@eecs.umich.edu case PHY_EPSTATUS: 48310474Sandreas.hansson@arm.com regs.mdic.data(0x3000); 4843804Ssaidi@eecs.umich.edu break; 4853804Ssaidi@eecs.umich.edu case PHY_AGC: 4863804Ssaidi@eecs.umich.edu regs.mdic.data(0x180); // some random length 4873804Ssaidi@eecs.umich.edu break; 4883804Ssaidi@eecs.umich.edu default: 4893804Ssaidi@eecs.umich.edu regs.mdic.data(0); 4904990Sgblack@eecs.umich.edu } 49110474Sandreas.hansson@arm.com regs.mdic.r(1); 4923804Ssaidi@eecs.umich.edu break; 4933804Ssaidi@eecs.umich.edu case REG_ICR: 4943833Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", 4953836Ssaidi@eecs.umich.edu regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame()); 4963804Ssaidi@eecs.umich.edu if (regs.ctrl_ext.iame()) 4973804Ssaidi@eecs.umich.edu regs.imr &= ~regs.iam; 4983804Ssaidi@eecs.umich.edu regs.icr = ~bits(val,30,0) & regs.icr(); 4993804Ssaidi@eecs.umich.edu chkInterrupt(); 5003804Ssaidi@eecs.umich.edu break; 5013804Ssaidi@eecs.umich.edu case REG_ITR: 5023804Ssaidi@eecs.umich.edu regs.itr = val; 5034990Sgblack@eecs.umich.edu break; 5048751Sgblack@eecs.umich.edu case REG_ICS: 50510474Sandreas.hansson@arm.com DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n"); 5068751Sgblack@eecs.umich.edu postInterrupt((IntTypes)val); 5078751Sgblack@eecs.umich.edu break; 50810474Sandreas.hansson@arm.com case REG_IMS: 5098751Sgblack@eecs.umich.edu regs.imr |= val; 51010474Sandreas.hansson@arm.com chkInterrupt(); 51110474Sandreas.hansson@arm.com break; 5128751Sgblack@eecs.umich.edu case REG_IMC: 5133804Ssaidi@eecs.umich.edu regs.imr &= ~val; 5143804Ssaidi@eecs.umich.edu chkInterrupt(); 5153804Ssaidi@eecs.umich.edu break; 5163804Ssaidi@eecs.umich.edu case REG_IAM: 5174990Sgblack@eecs.umich.edu regs.iam = val; 5184990Sgblack@eecs.umich.edu break; 51910474Sandreas.hansson@arm.com case REG_RCTL: 5203804Ssaidi@eecs.umich.edu oldrctl = regs.rctl; 5213804Ssaidi@eecs.umich.edu regs.rctl = val; 5223836Ssaidi@eecs.umich.edu if (regs.rctl.rst()) { 5233836Ssaidi@eecs.umich.edu rxDescCache.reset(); 5243836Ssaidi@eecs.umich.edu DPRINTF(EthernetSM, "RXS: Got RESET!\n"); 5256022Sgblack@eecs.umich.edu rxFifo.clear(); 5263836Ssaidi@eecs.umich.edu regs.rctl.rst(0); 5275555Snate@binkert.org } 5283836Ssaidi@eecs.umich.edu if (regs.rctl.en()) 5293804Ssaidi@eecs.umich.edu rxTick = true; 5303804Ssaidi@eecs.umich.edu restartClock(); 5313804Ssaidi@eecs.umich.edu break; 5323804Ssaidi@eecs.umich.edu case REG_FCTTV: 53312749Sgiacomo.travaglini@arm.com regs.fcttv = val; 5343804Ssaidi@eecs.umich.edu break; 5355555Snate@binkert.org case REG_TCTL: 5365555Snate@binkert.org regs.tctl = val; 5375555Snate@binkert.org oldtctl = regs.tctl; 5385555Snate@binkert.org regs.tctl = val; 5394172Ssaidi@eecs.umich.edu if (regs.tctl.en()) 5403836Ssaidi@eecs.umich.edu txTick = true; 5413836Ssaidi@eecs.umich.edu restartClock(); 5423836Ssaidi@eecs.umich.edu if (regs.tctl.en() && !oldtctl.en()) { 5439912Sandreas@sandberg.pp.se txDescCache.reset(); 5443836Ssaidi@eecs.umich.edu } 5453836Ssaidi@eecs.umich.edu break; 5465570Snate@binkert.org case REG_PBA: 5473833Ssaidi@eecs.umich.edu regs.pba.rxa(val); 5483836Ssaidi@eecs.umich.edu regs.pba.txa(64 - regs.pba.rxa()); 5493836Ssaidi@eecs.umich.edu break; 5503836Ssaidi@eecs.umich.edu case REG_WUC: 5513929Ssaidi@eecs.umich.edu case REG_LEDCTL: 5523929Ssaidi@eecs.umich.edu case REG_FCAL: 5533929Ssaidi@eecs.umich.edu case REG_FCAH: 5543836Ssaidi@eecs.umich.edu case REG_FCT: 5553836Ssaidi@eecs.umich.edu case REG_VET: 5563836Ssaidi@eecs.umich.edu case REG_AIFS: 5574996Sgblack@eecs.umich.edu case REG_TIPG: 5584996Sgblack@eecs.umich.edu ; // We don't care, so don't store anything 5594996Sgblack@eecs.umich.edu break; 5604996Sgblack@eecs.umich.edu case REG_IVAR0: 5614996Sgblack@eecs.umich.edu warn("Writing to IVAR0, ignoring...\n"); 5624996Sgblack@eecs.umich.edu break; 5634996Sgblack@eecs.umich.edu case REG_FCRTL: 5644996Sgblack@eecs.umich.edu regs.fcrtl = val; 5654996Sgblack@eecs.umich.edu break; 5664996Sgblack@eecs.umich.edu case REG_FCRTH: 5674996Sgblack@eecs.umich.edu regs.fcrth = val; 5684996Sgblack@eecs.umich.edu break; 5694996Sgblack@eecs.umich.edu case REG_RDBAL: 5704996Sgblack@eecs.umich.edu regs.rdba.rdbal( val & ~mask(4)); 5714996Sgblack@eecs.umich.edu rxDescCache.areaChanged(); 5724996Sgblack@eecs.umich.edu break; 5734996Sgblack@eecs.umich.edu case REG_RDBAH: 5744996Sgblack@eecs.umich.edu regs.rdba.rdbah(val); 5754996Sgblack@eecs.umich.edu rxDescCache.areaChanged(); 5765555Snate@binkert.org break; 57710824SAndreas.Sandberg@ARM.com case REG_RDLEN: 57810824SAndreas.Sandberg@ARM.com regs.rdlen = val & ~mask(7); 57910824SAndreas.Sandberg@ARM.com rxDescCache.areaChanged(); 58010824SAndreas.Sandberg@ARM.com break; 5815555Snate@binkert.org case REG_SRRCTL: 5825555Snate@binkert.org regs.srrctl = val; 5834996Sgblack@eecs.umich.edu break; 5844996Sgblack@eecs.umich.edu case REG_RDH: 5854996Sgblack@eecs.umich.edu regs.rdh = val; 5864996Sgblack@eecs.umich.edu rxDescCache.areaChanged(); 5874996Sgblack@eecs.umich.edu break; 5884996Sgblack@eecs.umich.edu case REG_RDT: 5894996Sgblack@eecs.umich.edu regs.rdt = val; 5904996Sgblack@eecs.umich.edu DPRINTF(EthernetSM, "RXS: RDT Updated.\n"); 5915555Snate@binkert.org if (getState() == SimObject::Running) { 59210824SAndreas.Sandberg@ARM.com DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n"); 59310824SAndreas.Sandberg@ARM.com rxDescCache.fetchDescriptors(); 59410824SAndreas.Sandberg@ARM.com } else { 59510824SAndreas.Sandberg@ARM.com DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n"); 5965555Snate@binkert.org } 5975555Snate@binkert.org break; 5984996Sgblack@eecs.umich.edu case REG_RDTR: 5994996Sgblack@eecs.umich.edu regs.rdtr = val; 6004996Sgblack@eecs.umich.edu break; 6013836Ssaidi@eecs.umich.edu case REG_RADV: 6023836Ssaidi@eecs.umich.edu regs.radv = val; 6033833Ssaidi@eecs.umich.edu break; 6043833Ssaidi@eecs.umich.edu case REG_RXDCTL: 6053833Ssaidi@eecs.umich.edu regs.rxdctl = val; 6063833Ssaidi@eecs.umich.edu break; 6073833Ssaidi@eecs.umich.edu case REG_TDBAL: 6083833Ssaidi@eecs.umich.edu regs.tdba.tdbal( val & ~mask(4)); 6093833Ssaidi@eecs.umich.edu txDescCache.areaChanged(); 6103833Ssaidi@eecs.umich.edu break; 6113916Ssaidi@eecs.umich.edu case REG_TDBAH: 6123833Ssaidi@eecs.umich.edu regs.tdba.tdbah(val); 6133804Ssaidi@eecs.umich.edu txDescCache.areaChanged(); 6143832Ssaidi@eecs.umich.edu break; 6153832Ssaidi@eecs.umich.edu case REG_TDLEN: 6163804Ssaidi@eecs.umich.edu regs.tdlen = val & ~mask(7); 6173804Ssaidi@eecs.umich.edu txDescCache.areaChanged(); 6183804Ssaidi@eecs.umich.edu break; 6193833Ssaidi@eecs.umich.edu case REG_TDH: 6205555Snate@binkert.org regs.tdh = val; 6213804Ssaidi@eecs.umich.edu txDescCache.areaChanged(); 6223804Ssaidi@eecs.umich.edu break; 6233804Ssaidi@eecs.umich.edu case REG_TXDCA_CTL: 6243804Ssaidi@eecs.umich.edu regs.txdca_ctl = val; 6253804Ssaidi@eecs.umich.edu if (regs.txdca_ctl.enabled()) 6263804Ssaidi@eecs.umich.edu panic("No support for DCA\n"); 6273804Ssaidi@eecs.umich.edu break; 6283804Ssaidi@eecs.umich.edu case REG_TDT: 6293804Ssaidi@eecs.umich.edu regs.tdt = val; 6303833Ssaidi@eecs.umich.edu DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n"); 6313804Ssaidi@eecs.umich.edu if (getState() == SimObject::Running) { 6323910Ssaidi@eecs.umich.edu DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n"); 6333804Ssaidi@eecs.umich.edu txDescCache.fetchDescriptors(); 6347741Sgblack@eecs.umich.edu } else { 6353804Ssaidi@eecs.umich.edu DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n"); 6364990Sgblack@eecs.umich.edu } 63710474Sandreas.hansson@arm.com break; 6383804Ssaidi@eecs.umich.edu case REG_TIDV: 6393910Ssaidi@eecs.umich.edu regs.tidv = val; 6407741Sgblack@eecs.umich.edu break; 6414990Sgblack@eecs.umich.edu case REG_TXDCTL: 64210474Sandreas.hansson@arm.com regs.txdctl = val; 6433804Ssaidi@eecs.umich.edu break; 6443804Ssaidi@eecs.umich.edu case REG_TADV: 6457741Sgblack@eecs.umich.edu regs.tadv = val; 6463910Ssaidi@eecs.umich.edu break; 6473910Ssaidi@eecs.umich.edu case REG_TDWBAL: 6487741Sgblack@eecs.umich.edu regs.tdwba &= ~mask(32); 6493910Ssaidi@eecs.umich.edu regs.tdwba |= val; 6503910Ssaidi@eecs.umich.edu txDescCache.completionWriteback(regs.tdwba & ~mask(1), 6517741Sgblack@eecs.umich.edu regs.tdwba & mask(1)); 6523910Ssaidi@eecs.umich.edu break; 6533910Ssaidi@eecs.umich.edu case REG_TDWBAH: 6543910Ssaidi@eecs.umich.edu regs.tdwba &= mask(32); 6553910Ssaidi@eecs.umich.edu regs.tdwba |= (uint64_t)val << 32; 6563910Ssaidi@eecs.umich.edu txDescCache.completionWriteback(regs.tdwba & ~mask(1), 6573910Ssaidi@eecs.umich.edu regs.tdwba & mask(1)); 6583902Ssaidi@eecs.umich.edu break; 6593804Ssaidi@eecs.umich.edu case REG_RXCSUM: 6603926Ssaidi@eecs.umich.edu regs.rxcsum = val; 6617741Sgblack@eecs.umich.edu break; 6623804Ssaidi@eecs.umich.edu case REG_RLPML: 6634989Sgblack@eecs.umich.edu regs.rlpml = val; 6644989Sgblack@eecs.umich.edu break; 6657741Sgblack@eecs.umich.edu case REG_RFCTL: 6667741Sgblack@eecs.umich.edu regs.rfctl = val; 6677741Sgblack@eecs.umich.edu if (regs.rfctl.exsten()) 6684989Sgblack@eecs.umich.edu panic("Extended RX descriptors not implemented\n"); 6693856Ssaidi@eecs.umich.edu break; 6707741Sgblack@eecs.umich.edu case REG_MANC: 6713804Ssaidi@eecs.umich.edu regs.manc = val; 6724103Ssaidi@eecs.umich.edu break; 6737741Sgblack@eecs.umich.edu case REG_SWSM: 6744191Ssaidi@eecs.umich.edu regs.swsm = val; 6754191Ssaidi@eecs.umich.edu if (regs.fwsm.eep_fw_semaphore()) 6767741Sgblack@eecs.umich.edu regs.swsm.swesmbi(0); 6774103Ssaidi@eecs.umich.edu break; 6787741Sgblack@eecs.umich.edu case REG_SWFWSYNC: 6793804Ssaidi@eecs.umich.edu regs.sw_fw_sync = val; 6807741Sgblack@eecs.umich.edu break; 6813804Ssaidi@eecs.umich.edu default: 6827741Sgblack@eecs.umich.edu if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) && 6833824Ssaidi@eecs.umich.edu !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) && 6847741Sgblack@eecs.umich.edu !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4)) 6853825Ssaidi@eecs.umich.edu panic("Write request to unknown register number: %#x\n", daddr); 6863823Ssaidi@eecs.umich.edu }; 6877741Sgblack@eecs.umich.edu 6887741Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 6893823Ssaidi@eecs.umich.edu return pioDelay; 6903804Ssaidi@eecs.umich.edu} 6913804Ssaidi@eecs.umich.edu 6923826Ssaidi@eecs.umich.eduvoid 6934996Sgblack@eecs.umich.eduIGbE::postInterrupt(IntTypes t, bool now) 6944990Sgblack@eecs.umich.edu{ 69510474Sandreas.hansson@arm.com assert(t); 6963826Ssaidi@eecs.umich.edu 6973826Ssaidi@eecs.umich.edu // Interrupt is already pending 6983826Ssaidi@eecs.umich.edu if (t & regs.icr() && !now) 6993826Ssaidi@eecs.umich.edu return; 7003826Ssaidi@eecs.umich.edu 7013826Ssaidi@eecs.umich.edu regs.icr = regs.icr() | t; 7024990Sgblack@eecs.umich.edu 70310474Sandreas.hansson@arm.com Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval(); 7043826Ssaidi@eecs.umich.edu DPRINTF(EthernetIntr, 7053826Ssaidi@eecs.umich.edu "EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n", 7067741Sgblack@eecs.umich.edu curTick(), regs.itr.interval(), itr_interval); 7073804Ssaidi@eecs.umich.edu 7083804Ssaidi@eecs.umich.edu if (regs.itr.interval() == 0 || now || 7095555Snate@binkert.org lastInterrupt + itr_interval <= curTick()) { 7103804Ssaidi@eecs.umich.edu if (interEvent.scheduled()) { 7117741Sgblack@eecs.umich.edu deschedule(interEvent); 7123836Ssaidi@eecs.umich.edu } 7133804Ssaidi@eecs.umich.edu cpuPostInt(); 7143804Ssaidi@eecs.umich.edu } else { 7153804Ssaidi@eecs.umich.edu Tick int_time = lastInterrupt + itr_interval; 7163836Ssaidi@eecs.umich.edu assert(int_time > 0); 7173804Ssaidi@eecs.umich.edu DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n", 7183804Ssaidi@eecs.umich.edu int_time); 7194990Sgblack@eecs.umich.edu if (!interEvent.scheduled()) { 7203811Ssaidi@eecs.umich.edu schedule(interEvent, int_time); 7218751Sgblack@eecs.umich.edu } 72210474Sandreas.hansson@arm.com } 7238751Sgblack@eecs.umich.edu} 7248751Sgblack@eecs.umich.edu 72510474Sandreas.hansson@arm.comvoid 7268751Sgblack@eecs.umich.eduIGbE::delayIntEvent() 72710474Sandreas.hansson@arm.com{ 72810474Sandreas.hansson@arm.com cpuPostInt(); 7298751Sgblack@eecs.umich.edu} 7303804Ssaidi@eecs.umich.edu 7313804Ssaidi@eecs.umich.edu 7323804Ssaidi@eecs.umich.eduvoid 7333928Ssaidi@eecs.umich.eduIGbE::cpuPostInt() 7344990Sgblack@eecs.umich.edu{ 7354990Sgblack@eecs.umich.edu 73610474Sandreas.hansson@arm.com postedInterrupts++; 7373928Ssaidi@eecs.umich.edu 7383804Ssaidi@eecs.umich.edu if (!(regs.icr() & regs.imr)) { 7393804Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n"); 7404990Sgblack@eecs.umich.edu return; 7414990Sgblack@eecs.umich.edu } 74210474Sandreas.hansson@arm.com 7433804Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Posting Interrupt\n"); 7443804Ssaidi@eecs.umich.edu 7457741Sgblack@eecs.umich.edu 7464990Sgblack@eecs.umich.edu if (interEvent.scheduled()) { 7474990Sgblack@eecs.umich.edu deschedule(interEvent); 74810474Sandreas.hansson@arm.com } 7493804Ssaidi@eecs.umich.edu 7503804Ssaidi@eecs.umich.edu if (rdtrEvent.scheduled()) { 7517741Sgblack@eecs.umich.edu regs.icr.rxt0(1); 7524990Sgblack@eecs.umich.edu deschedule(rdtrEvent); 7534990Sgblack@eecs.umich.edu } 75410474Sandreas.hansson@arm.com if (radvEvent.scheduled()) { 7553928Ssaidi@eecs.umich.edu regs.icr.rxt0(1); 7563928Ssaidi@eecs.umich.edu deschedule(radvEvent); 7574090Ssaidi@eecs.umich.edu } 75810824SAndreas.Sandberg@ARM.com if (tadvEvent.scheduled()) { 7593804Ssaidi@eecs.umich.edu regs.icr.txdw(1); 7603836Ssaidi@eecs.umich.edu deschedule(tadvEvent); 7613836Ssaidi@eecs.umich.edu } 7623881Ssaidi@eecs.umich.edu if (tidvEvent.scheduled()) { 7633881Ssaidi@eecs.umich.edu regs.icr.txdw(1); 7643881Ssaidi@eecs.umich.edu deschedule(tidvEvent); 7653881Ssaidi@eecs.umich.edu } 7663881Ssaidi@eecs.umich.edu 7673836Ssaidi@eecs.umich.edu regs.icr.int_assert(1); 7683836Ssaidi@eecs.umich.edu DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n", 7693836Ssaidi@eecs.umich.edu regs.icr()); 7703836Ssaidi@eecs.umich.edu 7713836Ssaidi@eecs.umich.edu intrPost(); 7723836Ssaidi@eecs.umich.edu 7733836Ssaidi@eecs.umich.edu lastInterrupt = curTick(); 7743836Ssaidi@eecs.umich.edu} 7753881Ssaidi@eecs.umich.edu 7765555Snate@binkert.orgvoid 7773836Ssaidi@eecs.umich.eduIGbE::cpuClearInt() 7783804Ssaidi@eecs.umich.edu{ 7794103Ssaidi@eecs.umich.edu if (regs.icr.int_assert()) { 7803806Ssaidi@eecs.umich.edu regs.icr.int_assert(0); 7814103Ssaidi@eecs.umich.edu DPRINTF(EthernetIntr, 7824103Ssaidi@eecs.umich.edu "EINT: Clearing interrupt to CPU now. Vector %#x\n", 7834990Sgblack@eecs.umich.edu regs.icr()); 7844103Ssaidi@eecs.umich.edu intrClear(); 78510474Sandreas.hansson@arm.com } 7864103Ssaidi@eecs.umich.edu} 78710474Sandreas.hansson@arm.com 7884103Ssaidi@eecs.umich.eduvoid 7894103Ssaidi@eecs.umich.eduIGbE::chkInterrupt() 7905570Snate@binkert.org{ 7915570Snate@binkert.org DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(), 7924990Sgblack@eecs.umich.edu regs.imr); 79310474Sandreas.hansson@arm.com // Check if we need to clear the cpu interrupt 7944103Ssaidi@eecs.umich.edu if (!(regs.icr() & regs.imr)) { 7954103Ssaidi@eecs.umich.edu DPRINTF(Ethernet, "Mask cleaned all interrupts\n"); 7964103Ssaidi@eecs.umich.edu if (interEvent.scheduled()) 7974103Ssaidi@eecs.umich.edu deschedule(interEvent); 7983804Ssaidi@eecs.umich.edu if (regs.icr.int_assert()) 7993806Ssaidi@eecs.umich.edu cpuClearInt(); 8003806Ssaidi@eecs.umich.edu } 8014990Sgblack@eecs.umich.edu DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", 80210474Sandreas.hansson@arm.com regs.itr(), regs.itr.interval()); 8033806Ssaidi@eecs.umich.edu 8043824Ssaidi@eecs.umich.edu if (regs.icr() & regs.imr) { 8053824Ssaidi@eecs.umich.edu if (regs.itr.interval() == 0) { 8063824Ssaidi@eecs.umich.edu cpuPostInt(); 8073824Ssaidi@eecs.umich.edu } else { 8084990Sgblack@eecs.umich.edu DPRINTF(Ethernet, 80910474Sandreas.hansson@arm.com "Possibly scheduling interrupt because of imr write\n"); 8103824Ssaidi@eecs.umich.edu if (!interEvent.scheduled()) { 8115570Snate@binkert.org Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval(); 8124990Sgblack@eecs.umich.edu DPRINTF(Ethernet, "Scheduling for %d\n", t); 81310474Sandreas.hansson@arm.com schedule(interEvent, t); 8143824Ssaidi@eecs.umich.edu } 8153824Ssaidi@eecs.umich.edu } 8163824Ssaidi@eecs.umich.edu } 8173825Ssaidi@eecs.umich.edu} 8183825Ssaidi@eecs.umich.edu 8194990Sgblack@eecs.umich.edu 8204070Ssaidi@eecs.umich.edu///////////////////////////// IGbE::DescCache ////////////////////////////// 82110474Sandreas.hansson@arm.com 8224070Ssaidi@eecs.umich.edutemplate<class T> 82310474Sandreas.hansson@arm.comIGbE::DescCache<T>::DescCache(IGbE *i, const std::string n, int s) 8243825Ssaidi@eecs.umich.edu : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), 8253825Ssaidi@eecs.umich.edu wbOut(0), pktPtr(NULL), wbDelayEvent(this), 8263825Ssaidi@eecs.umich.edu fetchDelayEvent(this), fetchEvent(this), wbEvent(this) 8273825Ssaidi@eecs.umich.edu{ 8283824Ssaidi@eecs.umich.edu fetchBuf = new T[size]; 8293804Ssaidi@eecs.umich.edu wbBuf = new T[size]; 8303811Ssaidi@eecs.umich.edu} 8318105Sgblack@eecs.umich.edu 8323806Ssaidi@eecs.umich.edutemplate<class T> 8333806Ssaidi@eecs.umich.eduIGbE::DescCache<T>::~DescCache() 8343804Ssaidi@eecs.umich.edu{ 8353804Ssaidi@eecs.umich.edu reset(); 8366022Sgblack@eecs.umich.edu delete[] fetchBuf; 83712749Sgiacomo.travaglini@arm.com delete[] wbBuf; 8386022Sgblack@eecs.umich.edu} 8396023Snate@binkert.org 8406022Sgblack@eecs.umich.edutemplate<class T> 8416022Sgblack@eecs.umich.eduvoid 8426023Snate@binkert.orgIGbE::DescCache<T>::areaChanged() 8436022Sgblack@eecs.umich.edu{ 8446022Sgblack@eecs.umich.edu if (usedCache.size() > 0 || curFetching || wbOut) 8455894Sgblack@eecs.umich.edu panic("Descriptor Address, Length or Head changed. Bad\n"); 84612749Sgiacomo.travaglini@arm.com reset(); 8476023Snate@binkert.org 8485894Sgblack@eecs.umich.edu} 8495894Sgblack@eecs.umich.edu 8506023Snate@binkert.orgtemplate<class T> 8515894Sgblack@eecs.umich.eduvoid 8525894Sgblack@eecs.umich.eduIGbE::DescCache<T>::writeback(Addr aMask) 8538888Sgeoffrey.blake@arm.com{ 85412749Sgiacomo.travaglini@arm.com int curHead = descHead(); 85512749Sgiacomo.travaglini@arm.com int max_to_wb = usedCache.size(); 8569738Sandreas@sandberg.pp.se 8579738Sandreas@sandberg.pp.se // Check if this writeback is less restrictive that the previous 8589738Sandreas@sandberg.pp.se // and if so setup another one immediately following it 8599738Sandreas@sandberg.pp.se if (wbOut) { 8609180Sandreas.hansson@arm.com if (aMask < wbAlignment) { 8616022Sgblack@eecs.umich.edu moreToWb = true; 8623806Ssaidi@eecs.umich.edu wbAlignment = aMask; 8633823Ssaidi@eecs.umich.edu } 8649912Sandreas@sandberg.pp.se DPRINTF(EthernetDesc, 8654070Ssaidi@eecs.umich.edu "Writing back already in process, returning\n"); 8663823Ssaidi@eecs.umich.edu return; 8673823Ssaidi@eecs.umich.edu } 8689912Sandreas@sandberg.pp.se 8693823Ssaidi@eecs.umich.edu moreToWb = false; 87012406Sgabeblack@google.com wbAlignment = aMask; 8714990Sgblack@eecs.umich.edu 8723823Ssaidi@eecs.umich.edu 8733823Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: " 8743823Ssaidi@eecs.umich.edu "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n", 87513231Sgabeblack@google.com curHead, descTail(), descLen(), cachePnt, max_to_wb, 8763823Ssaidi@eecs.umich.edu descLeft()); 8773823Ssaidi@eecs.umich.edu 8783823Ssaidi@eecs.umich.edu if (max_to_wb + curHead >= descLen()) { 8793823Ssaidi@eecs.umich.edu max_to_wb = descLen() - curHead; 88013231Sgabeblack@google.com moreToWb = true; 8813823Ssaidi@eecs.umich.edu // this is by definition aligned correctly 8823823Ssaidi@eecs.umich.edu } else if (wbAlignment != 0) { 88313231Sgabeblack@google.com // align the wb point to the mask 8843823Ssaidi@eecs.umich.edu max_to_wb = max_to_wb & ~wbAlignment; 8853823Ssaidi@eecs.umich.edu } 8863823Ssaidi@eecs.umich.edu 8873823Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb); 8883823Ssaidi@eecs.umich.edu 8893824Ssaidi@eecs.umich.edu if (max_to_wb <= 0) { 89013231Sgabeblack@google.com if (usedCache.size()) 8913824Ssaidi@eecs.umich.edu igbe->anBegin(annSmWb, "Wait Alignment", CPA::FL_WAIT); 8923824Ssaidi@eecs.umich.edu else 8933823Ssaidi@eecs.umich.edu igbe->anWe(annSmWb, annUsedCacheQ); 8943823Ssaidi@eecs.umich.edu return; 89513231Sgabeblack@google.com } 8963823Ssaidi@eecs.umich.edu 8973823Ssaidi@eecs.umich.edu wbOut = max_to_wb; 8983823Ssaidi@eecs.umich.edu 89913231Sgabeblack@google.com assert(!wbDelayEvent.scheduled()); 9003823Ssaidi@eecs.umich.edu igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay); 9013823Ssaidi@eecs.umich.edu igbe->anBegin(annSmWb, "Prepare Writeback Desc"); 9023823Ssaidi@eecs.umich.edu} 90313231Sgabeblack@google.com 9043823Ssaidi@eecs.umich.edutemplate<class T> 9053823Ssaidi@eecs.umich.eduvoid 9063823Ssaidi@eecs.umich.eduIGbE::DescCache<T>::writeback1() 90713231Sgabeblack@google.com{ 9083823Ssaidi@eecs.umich.edu // If we're draining delay issuing this DMA 9093823Ssaidi@eecs.umich.edu if (igbe->getState() != SimObject::Running) { 9103823Ssaidi@eecs.umich.edu igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay); 91113231Sgabeblack@google.com return; 9123823Ssaidi@eecs.umich.edu } 9133823Ssaidi@eecs.umich.edu 9143823Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Begining DMA of %d descriptors\n", wbOut); 91513231Sgabeblack@google.com 9163823Ssaidi@eecs.umich.edu for (int x = 0; x < wbOut; x++) { 9173823Ssaidi@eecs.umich.edu assert(usedCache.size()); 9183823Ssaidi@eecs.umich.edu memcpy(&wbBuf[x], usedCache[x], sizeof(T)); 91913231Sgabeblack@google.com igbe->anPq(annSmWb, annUsedCacheQ); 9203823Ssaidi@eecs.umich.edu igbe->anPq(annSmWb, annDescQ); 9213823Ssaidi@eecs.umich.edu igbe->anQ(annSmWb, annUsedDescQ); 9223823Ssaidi@eecs.umich.edu } 92313231Sgabeblack@google.com 9243823Ssaidi@eecs.umich.edu 9253823Ssaidi@eecs.umich.edu igbe->anBegin(annSmWb, "Writeback Desc DMA"); 9263823Ssaidi@eecs.umich.edu 92713231Sgabeblack@google.com assert(wbOut); 9283823Ssaidi@eecs.umich.edu igbe->dmaWrite(pciToDma(descBase() + descHead() * sizeof(T)), 9293823Ssaidi@eecs.umich.edu wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf, 9303823Ssaidi@eecs.umich.edu igbe->wbCompDelay); 93113231Sgabeblack@google.com} 9323823Ssaidi@eecs.umich.edu 9333823Ssaidi@eecs.umich.edutemplate<class T> 9343823Ssaidi@eecs.umich.eduvoid 93513231Sgabeblack@google.comIGbE::DescCache<T>::fetchDescriptors() 9363823Ssaidi@eecs.umich.edu{ 9373823Ssaidi@eecs.umich.edu size_t max_to_fetch; 9383823Ssaidi@eecs.umich.edu 93913231Sgabeblack@google.com if (curFetching) { 9403823Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, 9413826Ssaidi@eecs.umich.edu "Currently fetching %d descriptors, returning\n", 94213231Sgabeblack@google.com curFetching); 9433826Ssaidi@eecs.umich.edu return; 9443823Ssaidi@eecs.umich.edu } 9453823Ssaidi@eecs.umich.edu 94613231Sgabeblack@google.com if (descTail() >= cachePnt) 9473823Ssaidi@eecs.umich.edu max_to_fetch = descTail() - cachePnt; 9483826Ssaidi@eecs.umich.edu else 9493826Ssaidi@eecs.umich.edu max_to_fetch = descLen() - cachePnt; 9503833Ssaidi@eecs.umich.edu 9514990Sgblack@eecs.umich.edu size_t free_cache = size - usedCache.size() - unusedCache.size(); 95213231Sgabeblack@google.com 9533833Ssaidi@eecs.umich.edu if (!max_to_fetch) 9543906Ssaidi@eecs.umich.edu igbe->anWe(annSmFetch, annUnusedDescQ); 95513231Sgabeblack@google.com else 9563906Ssaidi@eecs.umich.edu igbe->anPq(annSmFetch, annUnusedDescQ, max_to_fetch); 9573826Ssaidi@eecs.umich.edu 95813231Sgabeblack@google.com if (max_to_fetch) { 9593826Ssaidi@eecs.umich.edu if (!free_cache) 9603826Ssaidi@eecs.umich.edu igbe->anWf(annSmFetch, annDescQ); 9613826Ssaidi@eecs.umich.edu else 9623826Ssaidi@eecs.umich.edu igbe->anRq(annSmFetch, annDescQ, free_cache); 9633826Ssaidi@eecs.umich.edu } 9643823Ssaidi@eecs.umich.edu 9653823Ssaidi@eecs.umich.edu max_to_fetch = std::min(max_to_fetch, free_cache); 9663833Ssaidi@eecs.umich.edu 9674990Sgblack@eecs.umich.edu 96813231Sgabeblack@google.com DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: " 9693833Ssaidi@eecs.umich.edu "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n", 9703906Ssaidi@eecs.umich.edu descHead(), descTail(), descLen(), cachePnt, 97113231Sgabeblack@google.com max_to_fetch, descLeft()); 9723906Ssaidi@eecs.umich.edu 9733906Ssaidi@eecs.umich.edu // Nothing to do 97413231Sgabeblack@google.com if (max_to_fetch == 0) 9753906Ssaidi@eecs.umich.edu return; 9763826Ssaidi@eecs.umich.edu 97713231Sgabeblack@google.com // So we don't have two descriptor fetches going on at once 9783826Ssaidi@eecs.umich.edu curFetching = max_to_fetch; 9793823Ssaidi@eecs.umich.edu 98013231Sgabeblack@google.com assert(!fetchDelayEvent.scheduled()); 9813823Ssaidi@eecs.umich.edu igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay); 9823823Ssaidi@eecs.umich.edu igbe->anBegin(annSmFetch, "Prepare Fetch Desc"); 9833823Ssaidi@eecs.umich.edu} 9843823Ssaidi@eecs.umich.edu 9853823Ssaidi@eecs.umich.edutemplate<class T> 9863833Ssaidi@eecs.umich.eduvoid 98713231Sgabeblack@google.comIGbE::DescCache<T>::fetchDescriptors1() 9884990Sgblack@eecs.umich.edu{ 9894990Sgblack@eecs.umich.edu // If we're draining delay issuing this DMA 9904990Sgblack@eecs.umich.edu if (igbe->getState() != SimObject::Running) { 9914990Sgblack@eecs.umich.edu igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay); 9924990Sgblack@eecs.umich.edu return; 9933833Ssaidi@eecs.umich.edu } 9943833Ssaidi@eecs.umich.edu 99513231Sgabeblack@google.com igbe->anBegin(annSmFetch, "Fetch Desc"); 9964990Sgblack@eecs.umich.edu 9974990Sgblack@eecs.umich.edu DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n", 9984990Sgblack@eecs.umich.edu descBase() + cachePnt * sizeof(T), 9994990Sgblack@eecs.umich.edu pciToDma(descBase() + cachePnt * sizeof(T)), 10004990Sgblack@eecs.umich.edu curFetching * sizeof(T)); 10013833Ssaidi@eecs.umich.edu assert(curFetching); 10023899Ssaidi@eecs.umich.edu igbe->dmaRead(pciToDma(descBase() + cachePnt * sizeof(T)), 100313231Sgabeblack@google.com curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf, 10044990Sgblack@eecs.umich.edu igbe->fetchCompDelay); 10054990Sgblack@eecs.umich.edu} 10064990Sgblack@eecs.umich.edu 10074990Sgblack@eecs.umich.edutemplate<class T> 10084990Sgblack@eecs.umich.eduvoid 10093899Ssaidi@eecs.umich.eduIGbE::DescCache<T>::fetchComplete() 10103899Ssaidi@eecs.umich.edu{ 101113231Sgabeblack@google.com T *newDesc; 10124990Sgblack@eecs.umich.edu igbe->anBegin(annSmFetch, "Fetch Complete"); 10134990Sgblack@eecs.umich.edu for (int x = 0; x < curFetching; x++) { 10144990Sgblack@eecs.umich.edu newDesc = new T; 10154990Sgblack@eecs.umich.edu memcpy(newDesc, &fetchBuf[x], sizeof(T)); 10164990Sgblack@eecs.umich.edu unusedCache.push_back(newDesc); 10173899Ssaidi@eecs.umich.edu igbe->anDq(annSmFetch, annUnusedDescQ); 10184103Ssaidi@eecs.umich.edu igbe->anQ(annSmFetch, annUnusedCacheQ); 10195646Sgblack@eecs.umich.edu igbe->anQ(annSmFetch, annDescQ); 10205646Sgblack@eecs.umich.edu } 10215646Sgblack@eecs.umich.edu 102211150Smitch.hayenga@arm.com 102313231Sgabeblack@google.com#ifndef NDEBUG 10245646Sgblack@eecs.umich.edu int oldCp = cachePnt; 10254103Ssaidi@eecs.umich.edu#endif 10264103Ssaidi@eecs.umich.edu 10275646Sgblack@eecs.umich.edu cachePnt += curFetching; 10285646Sgblack@eecs.umich.edu assert(cachePnt <= descLen()); 10295646Sgblack@eecs.umich.edu if (cachePnt == descLen()) 103011150Smitch.hayenga@arm.com cachePnt = 0; 10315646Sgblack@eecs.umich.edu 103211150Smitch.hayenga@arm.com curFetching = 0; 103313231Sgabeblack@google.com 10345646Sgblack@eecs.umich.edu DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n", 10354103Ssaidi@eecs.umich.edu oldCp, cachePnt); 10363823Ssaidi@eecs.umich.edu 10373823Ssaidi@eecs.umich.edu if ((descTail() >= cachePnt ? (descTail() - cachePnt) : (descLen() - 10383823Ssaidi@eecs.umich.edu cachePnt)) == 0) 10393823Ssaidi@eecs.umich.edu { 10403823Ssaidi@eecs.umich.edu igbe->anWe(annSmFetch, annUnusedDescQ); 10414870Sstever@eecs.umich.edu } else if (!(size - usedCache.size() - unusedCache.size())) { 10429180Sandreas.hansson@arm.com igbe->anWf(annSmFetch, annDescQ); 10433806Ssaidi@eecs.umich.edu } else { 10443806Ssaidi@eecs.umich.edu igbe->anBegin(annSmFetch, "Wait", CPA::FL_WAIT); 10459180Sandreas.hansson@arm.com } 10466022Sgblack@eecs.umich.edu 10473806Ssaidi@eecs.umich.edu enableSm(); 104813231Sgabeblack@google.com igbe->checkDrain(); 10493823Ssaidi@eecs.umich.edu} 10509912Sandreas@sandberg.pp.se 10513823Ssaidi@eecs.umich.edutemplate<class T> 10523826Ssaidi@eecs.umich.eduvoid 10533826Ssaidi@eecs.umich.eduIGbE::DescCache<T>::wbComplete() 10543826Ssaidi@eecs.umich.edu{ 10553826Ssaidi@eecs.umich.edu 10563826Ssaidi@eecs.umich.edu igbe->anBegin(annSmWb, "Finish Writeback"); 10573826Ssaidi@eecs.umich.edu 10583863Ssaidi@eecs.umich.edu long curHead = descHead(); 10593863Ssaidi@eecs.umich.edu#ifndef NDEBUG 10603863Ssaidi@eecs.umich.edu long oldHead = curHead; 10613826Ssaidi@eecs.umich.edu#endif 10623826Ssaidi@eecs.umich.edu 10633825Ssaidi@eecs.umich.edu for (int x = 0; x < wbOut; x++) { 10643823Ssaidi@eecs.umich.edu assert(usedCache.size()); 10653823Ssaidi@eecs.umich.edu delete usedCache[0]; 106612406Sgabeblack@google.com usedCache.pop_front(); 10674990Sgblack@eecs.umich.edu 10683823Ssaidi@eecs.umich.edu igbe->anDq(annSmWb, annUsedCacheQ); 10693823Ssaidi@eecs.umich.edu igbe->anDq(annSmWb, annDescQ); 10703823Ssaidi@eecs.umich.edu } 10714172Ssaidi@eecs.umich.edu 10723823Ssaidi@eecs.umich.edu curHead += wbOut; 10733823Ssaidi@eecs.umich.edu wbOut = 0; 10743823Ssaidi@eecs.umich.edu 10753823Ssaidi@eecs.umich.edu if (curHead >= descLen()) 10764172Ssaidi@eecs.umich.edu curHead -= descLen(); 10773823Ssaidi@eecs.umich.edu 10783823Ssaidi@eecs.umich.edu // Update the head 10794172Ssaidi@eecs.umich.edu updateHead(curHead); 10803823Ssaidi@eecs.umich.edu 10813823Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n", 10823823Ssaidi@eecs.umich.edu oldHead, curHead); 10833823Ssaidi@eecs.umich.edu 10843823Ssaidi@eecs.umich.edu // If we still have more to wb, call wb now 10853824Ssaidi@eecs.umich.edu actionAfterWb(); 10863825Ssaidi@eecs.umich.edu if (moreToWb) { 10874172Ssaidi@eecs.umich.edu moreToWb = false; 10883824Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Writeback has more todo\n"); 10893824Ssaidi@eecs.umich.edu writeback(wbAlignment); 10903823Ssaidi@eecs.umich.edu } 10913823Ssaidi@eecs.umich.edu 10924990Sgblack@eecs.umich.edu if (!wbOut) { 10933823Ssaidi@eecs.umich.edu igbe->checkDrain(); 10943823Ssaidi@eecs.umich.edu if (usedCache.size()) 10953823Ssaidi@eecs.umich.edu igbe->anBegin(annSmWb, "Wait", CPA::FL_WAIT); 10964990Sgblack@eecs.umich.edu else 10973823Ssaidi@eecs.umich.edu igbe->anWe(annSmWb, annUsedCacheQ); 10983823Ssaidi@eecs.umich.edu } 10993823Ssaidi@eecs.umich.edu fetchAfterWb(); 11004990Sgblack@eecs.umich.edu} 11013823Ssaidi@eecs.umich.edu 11023823Ssaidi@eecs.umich.edutemplate<class T> 11033823Ssaidi@eecs.umich.eduvoid 11044990Sgblack@eecs.umich.eduIGbE::DescCache<T>::reset() 11053823Ssaidi@eecs.umich.edu{ 11063823Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Reseting descriptor cache\n"); 11073823Ssaidi@eecs.umich.edu for (typename CacheType::size_type x = 0; x < usedCache.size(); x++) 11084990Sgblack@eecs.umich.edu delete usedCache[x]; 11093823Ssaidi@eecs.umich.edu for (typename CacheType::size_type x = 0; x < unusedCache.size(); x++) 11103823Ssaidi@eecs.umich.edu delete unusedCache[x]; 11113823Ssaidi@eecs.umich.edu 11124990Sgblack@eecs.umich.edu usedCache.clear(); 11133823Ssaidi@eecs.umich.edu unusedCache.clear(); 11143823Ssaidi@eecs.umich.edu 11153823Ssaidi@eecs.umich.edu cachePnt = 0; 11164990Sgblack@eecs.umich.edu 11173823Ssaidi@eecs.umich.edu} 11183823Ssaidi@eecs.umich.edu 11193823Ssaidi@eecs.umich.edutemplate<class T> 11204990Sgblack@eecs.umich.eduvoid 11213823Ssaidi@eecs.umich.eduIGbE::DescCache<T>::serialize(std::ostream &os) 11223823Ssaidi@eecs.umich.edu{ 11233823Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cachePnt); 11244990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(curFetching); 11253823Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(wbOut); 11263823Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(moreToWb); 11273823Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(wbAlignment); 11284990Sgblack@eecs.umich.edu 11293823Ssaidi@eecs.umich.edu typename CacheType::size_type usedCacheSize = usedCache.size(); 11303823Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedCacheSize); 11313823Ssaidi@eecs.umich.edu for (typename CacheType::size_type x = 0; x < usedCacheSize; x++) { 11324990Sgblack@eecs.umich.edu arrayParamOut(os, csprintf("usedCache_%d", x), 11333823Ssaidi@eecs.umich.edu (uint8_t*)usedCache[x],sizeof(T)); 11343823Ssaidi@eecs.umich.edu } 11353823Ssaidi@eecs.umich.edu 11364990Sgblack@eecs.umich.edu typename CacheType::size_type unusedCacheSize = unusedCache.size(); 11373823Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(unusedCacheSize); 11383825Ssaidi@eecs.umich.edu for (typename CacheType::size_type x = 0; x < unusedCacheSize; x++) { 11393825Ssaidi@eecs.umich.edu arrayParamOut(os, csprintf("unusedCache_%d", x), 11405823Ssaidi@eecs.umich.edu (uint8_t*)unusedCache[x],sizeof(T)); 11413825Ssaidi@eecs.umich.edu } 11423823Ssaidi@eecs.umich.edu 11433823Ssaidi@eecs.umich.edu Tick fetch_delay = 0, wb_delay = 0; 11444172Ssaidi@eecs.umich.edu if (fetchDelayEvent.scheduled()) 11453823Ssaidi@eecs.umich.edu fetch_delay = fetchDelayEvent.when(); 11463826Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(fetch_delay); 11473826Ssaidi@eecs.umich.edu if (wbDelayEvent.scheduled()) 11483906Ssaidi@eecs.umich.edu wb_delay = wbDelayEvent.when(); 11494990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(wb_delay); 11503906Ssaidi@eecs.umich.edu 11513826Ssaidi@eecs.umich.edu 11523916Ssaidi@eecs.umich.edu} 11534990Sgblack@eecs.umich.edu 11543826Ssaidi@eecs.umich.edutemplate<class T> 11553826Ssaidi@eecs.umich.eduvoid 11563826Ssaidi@eecs.umich.eduIGbE::DescCache<T>::unserialize(Checkpoint *cp, const std::string §ion) 11573826Ssaidi@eecs.umich.edu{ 11583826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cachePnt); 11593826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(curFetching); 11603826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(wbOut); 116112620Sgabeblack@google.com UNSERIALIZE_SCALAR(moreToWb); 11623826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(wbAlignment); 11633826Ssaidi@eecs.umich.edu 11644990Sgblack@eecs.umich.edu typename CacheType::size_type usedCacheSize; 11653826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedCacheSize); 11663826Ssaidi@eecs.umich.edu T *temp; 11674172Ssaidi@eecs.umich.edu for (typename CacheType::size_type x = 0; x < usedCacheSize; x++) { 11683826Ssaidi@eecs.umich.edu temp = new T; 11693826Ssaidi@eecs.umich.edu arrayParamIn(cp, section, csprintf("usedCache_%d", x), 11703826Ssaidi@eecs.umich.edu (uint8_t*)temp,sizeof(T)); 117112406Sgabeblack@google.com usedCache.push_back(temp); 117212406Sgabeblack@google.com } 11733826Ssaidi@eecs.umich.edu 11743826Ssaidi@eecs.umich.edu typename CacheType::size_type unusedCacheSize; 11753826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(unusedCacheSize); 117612620Sgabeblack@google.com for (typename CacheType::size_type x = 0; x < unusedCacheSize; x++) { 11773826Ssaidi@eecs.umich.edu temp = new T; 11783826Ssaidi@eecs.umich.edu arrayParamIn(cp, section, csprintf("unusedCache_%d", x), 11794990Sgblack@eecs.umich.edu (uint8_t*)temp,sizeof(T)); 11803826Ssaidi@eecs.umich.edu unusedCache.push_back(temp); 11813826Ssaidi@eecs.umich.edu } 11824172Ssaidi@eecs.umich.edu Tick fetch_delay = 0, wb_delay = 0; 11833826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(fetch_delay); 11843826Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(wb_delay); 11853826Ssaidi@eecs.umich.edu if (fetch_delay) 11865555Snate@binkert.org igbe->schedule(fetchDelayEvent, fetch_delay); 11875555Snate@binkert.org if (wb_delay) 11883826Ssaidi@eecs.umich.edu igbe->schedule(wbDelayEvent, wb_delay); 11893863Ssaidi@eecs.umich.edu 11903863Ssaidi@eecs.umich.edu 11913863Ssaidi@eecs.umich.edu} 11924172Ssaidi@eecs.umich.edu 11933863Ssaidi@eecs.umich.edu///////////////////////////// IGbE::RxDescCache ////////////////////////////// 11943863Ssaidi@eecs.umich.edu 11954172Ssaidi@eecs.umich.eduIGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s) 11963863Ssaidi@eecs.umich.edu : DescCache<RxDesc>(i, n, s), pktDone(false), splitCount(0), 11973863Ssaidi@eecs.umich.edu pktEvent(this), pktHdrEvent(this), pktDataEvent(this) 11983863Ssaidi@eecs.umich.edu 11993863Ssaidi@eecs.umich.edu{ 12003863Ssaidi@eecs.umich.edu annSmFetch = "RX Desc Fetch"; 12013863Ssaidi@eecs.umich.edu annSmWb = "RX Desc Writeback"; 12023863Ssaidi@eecs.umich.edu annUnusedDescQ = "RX Unused Descriptors"; 12033863Ssaidi@eecs.umich.edu annUnusedCacheQ = "RX Unused Descriptor Cache"; 12043863Ssaidi@eecs.umich.edu annUsedCacheQ = "RX Used Descriptor Cache"; 12053863Ssaidi@eecs.umich.edu annUsedDescQ = "RX Used Descriptors"; 12063863Ssaidi@eecs.umich.edu annDescQ = "RX Descriptors"; 12077741Sgblack@eecs.umich.edu} 12083863Ssaidi@eecs.umich.edu 12093863Ssaidi@eecs.umich.eduvoid 121012406Sgabeblack@google.comIGbE::RxDescCache::pktSplitDone() 12113863Ssaidi@eecs.umich.edu{ 12127741Sgblack@eecs.umich.edu splitCount++; 12133863Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, 121412406Sgabeblack@google.com "Part of split packet done: splitcount now %d\n", splitCount); 12153863Ssaidi@eecs.umich.edu assert(splitCount <= 2); 12163863Ssaidi@eecs.umich.edu if (splitCount != 2) 121712406Sgabeblack@google.com return; 12183863Ssaidi@eecs.umich.edu splitCount = 0; 12193863Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, 12203863Ssaidi@eecs.umich.edu "Part of split packet done: calling pktComplete()\n"); 12213863Ssaidi@eecs.umich.edu pktComplete(); 12223863Ssaidi@eecs.umich.edu} 12233823Ssaidi@eecs.umich.edu 12243823Ssaidi@eecs.umich.eduint 12253906Ssaidi@eecs.umich.eduIGbE::RxDescCache::writePacket(EthPacketPtr packet, int pkt_offset) 12264990Sgblack@eecs.umich.edu{ 12273906Ssaidi@eecs.umich.edu assert(unusedCache.size()); 12283826Ssaidi@eecs.umich.edu //if (!unusedCache.size()) 12293916Ssaidi@eecs.umich.edu // return false; 12304990Sgblack@eecs.umich.edu 12313826Ssaidi@eecs.umich.edu pktPtr = packet; 12323823Ssaidi@eecs.umich.edu pktDone = false; 12334172Ssaidi@eecs.umich.edu unsigned buf_len, hdr_len; 12343823Ssaidi@eecs.umich.edu 12353823Ssaidi@eecs.umich.edu RxDesc *desc = unusedCache.front(); 12363823Ssaidi@eecs.umich.edu switch (igbe->regs.srrctl.desctype()) { 12373823Ssaidi@eecs.umich.edu case RXDT_LEGACY: 12383823Ssaidi@eecs.umich.edu assert(pkt_offset == 0); 12393863Ssaidi@eecs.umich.edu bytesCopied = packet->length; 12403863Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Packet Length: %d Desc Size: %d\n", 12413863Ssaidi@eecs.umich.edu packet->length, igbe->regs.rctl.descSize()); 12424172Ssaidi@eecs.umich.edu assert(packet->length < igbe->regs.rctl.descSize()); 12433863Ssaidi@eecs.umich.edu igbe->dmaWrite(pciToDma(desc->legacy.buf), 12443863Ssaidi@eecs.umich.edu packet->length, &pktEvent, packet->data, 12454172Ssaidi@eecs.umich.edu igbe->rxWriteDelay); 12463863Ssaidi@eecs.umich.edu break; 12473863Ssaidi@eecs.umich.edu case RXDT_ADV_ONEBUF: 12484172Ssaidi@eecs.umich.edu assert(pkt_offset == 0); 12493863Ssaidi@eecs.umich.edu bytesCopied = packet->length; 12503863Ssaidi@eecs.umich.edu buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() : 12513863Ssaidi@eecs.umich.edu igbe->regs.rctl.descSize(); 12523863Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Packet Length: %d srrctl: %#x Desc Size: %d\n", 12533863Ssaidi@eecs.umich.edu packet->length, igbe->regs.srrctl(), buf_len); 12543863Ssaidi@eecs.umich.edu assert(packet->length < buf_len); 12553863Ssaidi@eecs.umich.edu igbe->dmaWrite(pciToDma(desc->adv_read.pkt), 12563863Ssaidi@eecs.umich.edu packet->length, &pktEvent, packet->data, 12577741Sgblack@eecs.umich.edu igbe->rxWriteDelay); 12583863Ssaidi@eecs.umich.edu desc->adv_wb.header_len = htole(0); 12593863Ssaidi@eecs.umich.edu desc->adv_wb.sph = htole(0); 12603863Ssaidi@eecs.umich.edu desc->adv_wb.pkt_len = htole((uint16_t)(pktPtr->length)); 12613863Ssaidi@eecs.umich.edu break; 12627741Sgblack@eecs.umich.edu case RXDT_ADV_SPLIT_A: 12633863Ssaidi@eecs.umich.edu int split_point; 12643863Ssaidi@eecs.umich.edu 12653863Ssaidi@eecs.umich.edu buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() : 12663863Ssaidi@eecs.umich.edu igbe->regs.rctl.descSize(); 12673863Ssaidi@eecs.umich.edu hdr_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.hdrLen() : 0; 12683863Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, 12693863Ssaidi@eecs.umich.edu "lpe: %d Packet Length: %d offset: %d srrctl: %#x " 12703863Ssaidi@eecs.umich.edu "hdr addr: %#x Hdr Size: %d desc addr: %#x Desc Size: %d\n", 12713863Ssaidi@eecs.umich.edu igbe->regs.rctl.lpe(), packet->length, pkt_offset, 12723863Ssaidi@eecs.umich.edu igbe->regs.srrctl(), desc->adv_read.hdr, hdr_len, 12734103Ssaidi@eecs.umich.edu desc->adv_read.pkt, buf_len); 12745646Sgblack@eecs.umich.edu 12755646Sgblack@eecs.umich.edu split_point = hsplit(pktPtr); 12765646Sgblack@eecs.umich.edu 12775646Sgblack@eecs.umich.edu if (packet->length <= hdr_len) { 12785646Sgblack@eecs.umich.edu bytesCopied = packet->length; 127911150Smitch.hayenga@arm.com assert(pkt_offset == 0); 12805704Snate@binkert.org DPRINTF(EthernetDesc, "Hdr split: Entire packet in header\n"); 12815646Sgblack@eecs.umich.edu igbe->dmaWrite(pciToDma(desc->adv_read.hdr), 128211150Smitch.hayenga@arm.com packet->length, &pktEvent, packet->data, 12835646Sgblack@eecs.umich.edu igbe->rxWriteDelay); 12844103Ssaidi@eecs.umich.edu desc->adv_wb.header_len = htole((uint16_t)packet->length); 12854103Ssaidi@eecs.umich.edu desc->adv_wb.sph = htole(0); 12864103Ssaidi@eecs.umich.edu desc->adv_wb.pkt_len = htole(0); 12874103Ssaidi@eecs.umich.edu } else if (split_point) { 128811150Smitch.hayenga@arm.com if (pkt_offset) { 12894103Ssaidi@eecs.umich.edu // we are only copying some data, header/data has already been 12905555Snate@binkert.org // copied 12913823Ssaidi@eecs.umich.edu int max_to_copy = 12923823Ssaidi@eecs.umich.edu std::min(packet->length - pkt_offset, buf_len); 12939912Sandreas@sandberg.pp.se bytesCopied += max_to_copy; 12943823Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, 12954870Sstever@eecs.umich.edu "Hdr split: Continuing data buffer copy\n"); 12969180Sandreas.hansson@arm.com igbe->dmaWrite(pciToDma(desc->adv_read.pkt), 12973806Ssaidi@eecs.umich.edu max_to_copy, &pktEvent, 12983806Ssaidi@eecs.umich.edu packet->data + pkt_offset, igbe->rxWriteDelay); 12993804Ssaidi@eecs.umich.edu desc->adv_wb.header_len = htole(0); 13006022Sgblack@eecs.umich.edu desc->adv_wb.pkt_len = htole((uint16_t)max_to_copy); 13014070Ssaidi@eecs.umich.edu desc->adv_wb.sph = htole(0); 13024070Ssaidi@eecs.umich.edu } else { 130312406Sgabeblack@google.com int max_to_copy = 13044070Ssaidi@eecs.umich.edu std::min(packet->length - split_point, buf_len); 13054990Sgblack@eecs.umich.edu bytesCopied += max_to_copy + split_point; 13064990Sgblack@eecs.umich.edu 13074990Sgblack@eecs.umich.edu DPRINTF(EthernetDesc, "Hdr split: splitting at %d\n", 13084990Sgblack@eecs.umich.edu split_point); 13094070Ssaidi@eecs.umich.edu igbe->dmaWrite(pciToDma(desc->adv_read.hdr), 13104990Sgblack@eecs.umich.edu split_point, &pktHdrEvent, 13114990Sgblack@eecs.umich.edu packet->data, igbe->rxWriteDelay); 13124990Sgblack@eecs.umich.edu igbe->dmaWrite(pciToDma(desc->adv_read.pkt), 13134990Sgblack@eecs.umich.edu max_to_copy, &pktDataEvent, 13144070Ssaidi@eecs.umich.edu packet->data + split_point, igbe->rxWriteDelay); 13154990Sgblack@eecs.umich.edu desc->adv_wb.header_len = htole(split_point); 13164990Sgblack@eecs.umich.edu desc->adv_wb.sph = 1; 13174990Sgblack@eecs.umich.edu desc->adv_wb.pkt_len = htole((uint16_t)(max_to_copy)); 13184990Sgblack@eecs.umich.edu } 13194070Ssaidi@eecs.umich.edu } else { 13204990Sgblack@eecs.umich.edu panic("Header split not fitting within header buffer or " 13214990Sgblack@eecs.umich.edu "undecodable packet not fitting in header unsupported\n"); 13224990Sgblack@eecs.umich.edu } 13234990Sgblack@eecs.umich.edu break; 13244070Ssaidi@eecs.umich.edu default: 13254070Ssaidi@eecs.umich.edu panic("Unimplemnted RX receive buffer type: %d\n", 13264070Ssaidi@eecs.umich.edu igbe->regs.srrctl.desctype()); 13276022Sgblack@eecs.umich.edu } 13284070Ssaidi@eecs.umich.edu return bytesCopied; 13294070Ssaidi@eecs.umich.edu 13304070Ssaidi@eecs.umich.edu} 13314070Ssaidi@eecs.umich.edu 13324070Ssaidi@eecs.umich.eduvoid 13334070Ssaidi@eecs.umich.eduIGbE::RxDescCache::pktComplete() 13344070Ssaidi@eecs.umich.edu{ 13354070Ssaidi@eecs.umich.edu assert(unusedCache.size()); 13364070Ssaidi@eecs.umich.edu RxDesc *desc; 13374070Ssaidi@eecs.umich.edu desc = unusedCache.front(); 13384070Ssaidi@eecs.umich.edu 13394070Ssaidi@eecs.umich.edu igbe->anBegin("RXS", "Update Desc"); 13404070Ssaidi@eecs.umich.edu 13414070Ssaidi@eecs.umich.edu uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ; 13424070Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "pktPtr->length: %d bytesCopied: %d " 13434070Ssaidi@eecs.umich.edu "stripcrc offset: %d value written: %d %d\n", 13444070Ssaidi@eecs.umich.edu pktPtr->length, bytesCopied, crcfixup, 13454070Ssaidi@eecs.umich.edu htole((uint16_t)(pktPtr->length + crcfixup)), 13464070Ssaidi@eecs.umich.edu (uint16_t)(pktPtr->length + crcfixup)); 13474070Ssaidi@eecs.umich.edu 13484070Ssaidi@eecs.umich.edu // no support for anything but starting at 0 13494070Ssaidi@eecs.umich.edu assert(igbe->regs.rxcsum.pcss() == 0); 13504070Ssaidi@eecs.umich.edu 13514070Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n"); 13524070Ssaidi@eecs.umich.edu 13534070Ssaidi@eecs.umich.edu uint16_t status = RXDS_DD; 135410905Sandreas.sandberg@arm.com uint8_t err = 0; 13553804Ssaidi@eecs.umich.edu uint16_t ext_err = 0; 13564000Ssaidi@eecs.umich.edu uint16_t csum = 0; 13574000Ssaidi@eecs.umich.edu uint16_t ptype = 0; 13584000Ssaidi@eecs.umich.edu uint16_t ip_id = 0; 13594000Ssaidi@eecs.umich.edu 13604000Ssaidi@eecs.umich.edu assert(bytesCopied <= pktPtr->length); 136110905Sandreas.sandberg@arm.com if (bytesCopied == pktPtr->length) 136210905Sandreas.sandberg@arm.com status |= RXDS_EOP; 136310905Sandreas.sandberg@arm.com 136410905Sandreas.sandberg@arm.com IpPtr ip(pktPtr); 136510905Sandreas.sandberg@arm.com 13664000Ssaidi@eecs.umich.edu if (ip) { 13674990Sgblack@eecs.umich.edu DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id()); 13684990Sgblack@eecs.umich.edu ptype |= RXDP_IPV4; 13694990Sgblack@eecs.umich.edu ip_id = ip->id(); 13704990Sgblack@eecs.umich.edu 13714990Sgblack@eecs.umich.edu if (igbe->regs.rxcsum.ipofld()) { 13724990Sgblack@eecs.umich.edu DPRINTF(EthernetDesc, "Checking IP checksum\n"); 13734990Sgblack@eecs.umich.edu status |= RXDS_IPCS; 13744990Sgblack@eecs.umich.edu csum = htole(cksum(ip)); 137512544Skhalique913@gmail.com igbe->rxIpChecksums++; 13765276Ssaidi@eecs.umich.edu if (cksum(ip) != 0) { 13775276Ssaidi@eecs.umich.edu err |= RXDE_IPE; 137810905Sandreas.sandberg@arm.com ext_err |= RXDEE_IPE; 137910905Sandreas.sandberg@arm.com DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 13805276Ssaidi@eecs.umich.edu } 13813804Ssaidi@eecs.umich.edu } 13823804Ssaidi@eecs.umich.edu TcpPtr tcp(ip); 13833804Ssaidi@eecs.umich.edu if (tcp && igbe->regs.rxcsum.tuofld()) { 138410905Sandreas.sandberg@arm.com DPRINTF(EthernetDesc, "Checking TCP checksum\n"); 13853804Ssaidi@eecs.umich.edu status |= RXDS_TCPCS; 13864000Ssaidi@eecs.umich.edu ptype |= RXDP_TCP; 13874000Ssaidi@eecs.umich.edu csum = htole(cksum(tcp)); 138810905Sandreas.sandberg@arm.com igbe->rxTcpChecksums++; 13894000Ssaidi@eecs.umich.edu if (cksum(tcp) != 0) { 13904000Ssaidi@eecs.umich.edu DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 13914000Ssaidi@eecs.umich.edu err |= RXDE_TCPE; 13924000Ssaidi@eecs.umich.edu ext_err |= RXDEE_TCPE; 13934000Ssaidi@eecs.umich.edu } 139410905Sandreas.sandberg@arm.com } 139510905Sandreas.sandberg@arm.com 13964000Ssaidi@eecs.umich.edu UdpPtr udp(ip); 139710905Sandreas.sandberg@arm.com if (udp && igbe->regs.rxcsum.tuofld()) { 139810905Sandreas.sandberg@arm.com DPRINTF(EthernetDesc, "Checking UDP checksum\n"); 13994000Ssaidi@eecs.umich.edu status |= RXDS_UDPCS; 14004990Sgblack@eecs.umich.edu ptype |= RXDP_UDP; 14014990Sgblack@eecs.umich.edu csum = htole(cksum(udp)); 14024990Sgblack@eecs.umich.edu igbe->rxUdpChecksums++; 14034990Sgblack@eecs.umich.edu if (cksum(udp) != 0) { 14044990Sgblack@eecs.umich.edu DPRINTF(EthernetDesc, "Checksum is bad!!\n"); 14054990Sgblack@eecs.umich.edu ext_err |= RXDEE_TCPE; 14064990Sgblack@eecs.umich.edu err |= RXDE_TCPE; 14074990Sgblack@eecs.umich.edu } 14085276Ssaidi@eecs.umich.edu } 14095276Ssaidi@eecs.umich.edu } else { // if ip 14105276Ssaidi@eecs.umich.edu DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); 141110905Sandreas.sandberg@arm.com } 141210905Sandreas.sandberg@arm.com 14135276Ssaidi@eecs.umich.edu switch (igbe->regs.srrctl.desctype()) { 14145276Ssaidi@eecs.umich.edu case RXDT_LEGACY: 14155276Ssaidi@eecs.umich.edu desc->legacy.len = htole((uint16_t)(pktPtr->length + crcfixup)); 14165276Ssaidi@eecs.umich.edu desc->legacy.status = htole(status); 14174990Sgblack@eecs.umich.edu desc->legacy.errors = htole(err); 14183804Ssaidi@eecs.umich.edu // No vlan support at this point... just set it to 0 14193804Ssaidi@eecs.umich.edu desc->legacy.vlan = 0; 14207811Ssteve.reinhardt@amd.com break; 14214088Sbinkertn@umich.edu case RXDT_ADV_SPLIT_A: 14226022Sgblack@eecs.umich.edu case RXDT_ADV_ONEBUF: 14236022Sgblack@eecs.umich.edu desc->adv_wb.rss_type = htole(0); 14243804Ssaidi@eecs.umich.edu desc->adv_wb.pkt_type = htole(ptype); 14256022Sgblack@eecs.umich.edu if (igbe->regs.rxcsum.pcsd()) { 14263804Ssaidi@eecs.umich.edu // no rss support right now 1427 desc->adv_wb.rss_hash = htole(0); 1428 } else { 1429 desc->adv_wb.id = htole(ip_id); 1430 desc->adv_wb.csum = htole(csum); 1431 } 1432 desc->adv_wb.status = htole(status); 1433 desc->adv_wb.errors = htole(ext_err); 1434 // no vlan support 1435 desc->adv_wb.vlan_tag = htole(0); 1436 break; 1437 default: 1438 panic("Unimplemnted RX receive buffer type %d\n", 1439 igbe->regs.srrctl.desctype()); 1440 } 1441 1442 DPRINTF(EthernetDesc, "Descriptor complete w0: %#x w1: %#x\n", 1443 desc->adv_read.pkt, desc->adv_read.hdr); 1444 1445 if (bytesCopied == pktPtr->length) { 1446 DPRINTF(EthernetDesc, 1447 "Packet completely written to descriptor buffers\n"); 1448 // Deal with the rx timer interrupts 1449 if (igbe->regs.rdtr.delay()) { 1450 Tick delay = igbe->regs.rdtr.delay() * igbe->intClock(); 1451 DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", delay); 1452 igbe->reschedule(igbe->rdtrEvent, curTick() + delay); 1453 } 1454 1455 if (igbe->regs.radv.idv()) { 1456 Tick delay = igbe->regs.radv.idv() * igbe->intClock(); 1457 DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", delay); 1458 if (!igbe->radvEvent.scheduled()) { 1459 igbe->schedule(igbe->radvEvent, curTick() + delay); 1460 } 1461 } 1462 1463 // if neither radv or rdtr, maybe itr is set... 1464 if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) { 1465 DPRINTF(EthernetSM, 1466 "RXS: Receive interrupt delay disabled, posting IT_RXT\n"); 1467 igbe->postInterrupt(IT_RXT); 1468 } 1469 1470 // If the packet is small enough, interrupt appropriately 1471 // I wonder if this is delayed or not?! 1472 if (pktPtr->length <= igbe->regs.rsrpd.idv()) { 1473 DPRINTF(EthernetSM, 1474 "RXS: Posting IT_SRPD beacuse small packet received\n"); 1475 igbe->postInterrupt(IT_SRPD); 1476 } 1477 bytesCopied = 0; 1478 } 1479 1480 pktPtr = NULL; 1481 igbe->checkDrain(); 1482 enableSm(); 1483 pktDone = true; 1484 1485 igbe->anBegin("RXS", "Done Updating Desc"); 1486 DPRINTF(EthernetDesc, "Processing of this descriptor complete\n"); 1487 igbe->anDq("RXS", annUnusedCacheQ); 1488 unusedCache.pop_front(); 1489 igbe->anQ("RXS", annUsedCacheQ); 1490 usedCache.push_back(desc); 1491} 1492 1493void 1494IGbE::RxDescCache::enableSm() 1495{ 1496 if (!igbe->drainEvent) { 1497 igbe->rxTick = true; 1498 igbe->restartClock(); 1499 } 1500} 1501 1502bool 1503IGbE::RxDescCache::packetDone() 1504{ 1505 if (pktDone) { 1506 pktDone = false; 1507 return true; 1508 } 1509 return false; 1510} 1511 1512bool 1513IGbE::RxDescCache::hasOutstandingEvents() 1514{ 1515 return pktEvent.scheduled() || wbEvent.scheduled() || 1516 fetchEvent.scheduled() || pktHdrEvent.scheduled() || 1517 pktDataEvent.scheduled(); 1518 1519} 1520 1521void 1522IGbE::RxDescCache::serialize(std::ostream &os) 1523{ 1524 DescCache<RxDesc>::serialize(os); 1525 SERIALIZE_SCALAR(pktDone); 1526 SERIALIZE_SCALAR(splitCount); 1527 SERIALIZE_SCALAR(bytesCopied); 1528} 1529 1530void 1531IGbE::RxDescCache::unserialize(Checkpoint *cp, const std::string §ion) 1532{ 1533 DescCache<RxDesc>::unserialize(cp, section); 1534 UNSERIALIZE_SCALAR(pktDone); 1535 UNSERIALIZE_SCALAR(splitCount); 1536 UNSERIALIZE_SCALAR(bytesCopied); 1537} 1538 1539 1540///////////////////////////// IGbE::TxDescCache ////////////////////////////// 1541 1542IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s) 1543 : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), 1544 pktWaiting(false), completionAddress(0), completionEnabled(false), 1545 useTso(false), tsoHeaderLen(0), tsoMss(0), tsoTotalLen(0), tsoUsedLen(0), 1546 tsoPrevSeq(0), tsoPktPayloadBytes(0), tsoLoadedHeader(false), 1547 tsoPktHasHeader(false), tsoDescBytesUsed(0), tsoCopyBytes(0), tsoPkts(0), 1548 pktEvent(this), headerEvent(this), nullEvent(this) 1549{ 1550 annSmFetch = "TX Desc Fetch"; 1551 annSmWb = "TX Desc Writeback"; 1552 annUnusedDescQ = "TX Unused Descriptors"; 1553 annUnusedCacheQ = "TX Unused Descriptor Cache"; 1554 annUsedCacheQ = "TX Used Descriptor Cache"; 1555 annUsedDescQ = "TX Used Descriptors"; 1556 annDescQ = "TX Descriptors"; 1557} 1558 1559void 1560IGbE::TxDescCache::processContextDesc() 1561{ 1562 assert(unusedCache.size()); 1563 TxDesc *desc; 1564 1565 DPRINTF(EthernetDesc, "Checking and processing context descriptors\n"); 1566 1567 while (!useTso && unusedCache.size() && 1568 TxdOp::isContext(unusedCache.front())) { 1569 DPRINTF(EthernetDesc, "Got context descriptor type...\n"); 1570 1571 desc = unusedCache.front(); 1572 DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", 1573 desc->d1, desc->d2); 1574 1575 1576 // is this going to be a tcp or udp packet? 1577 isTcp = TxdOp::tcp(desc) ? true : false; 1578 1579 // setup all the TSO variables, they'll be ignored if we don't use 1580 // tso for this connection 1581 tsoHeaderLen = TxdOp::hdrlen(desc); 1582 tsoMss = TxdOp::mss(desc); 1583 1584 if (TxdOp::isType(desc, TxdOp::TXD_CNXT) && TxdOp::tse(desc)) { 1585 DPRINTF(EthernetDesc, "TCP offload enabled for packet hdrlen: " 1586 "%d mss: %d paylen %d\n", TxdOp::hdrlen(desc), 1587 TxdOp::mss(desc), TxdOp::getLen(desc)); 1588 useTso = true; 1589 tsoTotalLen = TxdOp::getLen(desc); 1590 tsoLoadedHeader = false; 1591 tsoDescBytesUsed = 0; 1592 tsoUsedLen = 0; 1593 tsoPrevSeq = 0; 1594 tsoPktHasHeader = false; 1595 tsoPkts = 0; 1596 tsoCopyBytes = 0; 1597 } 1598 1599 TxdOp::setDd(desc); 1600 unusedCache.pop_front(); 1601 igbe->anDq("TXS", annUnusedCacheQ); 1602 usedCache.push_back(desc); 1603 igbe->anQ("TXS", annUsedCacheQ); 1604 } 1605 1606 if (!unusedCache.size()) 1607 return; 1608 1609 desc = unusedCache.front(); 1610 if (!useTso && TxdOp::isType(desc, TxdOp::TXD_ADVDATA) && 1611 TxdOp::tse(desc)) { 1612 DPRINTF(EthernetDesc, "TCP offload(adv) enabled for packet " 1613 "hdrlen: %d mss: %d paylen %d\n", 1614 tsoHeaderLen, tsoMss, TxdOp::getTsoLen(desc)); 1615 useTso = true; 1616 tsoTotalLen = TxdOp::getTsoLen(desc); 1617 tsoLoadedHeader = false; 1618 tsoDescBytesUsed = 0; 1619 tsoUsedLen = 0; 1620 tsoPrevSeq = 0; 1621 tsoPktHasHeader = false; 1622 tsoPkts = 0; 1623 } 1624 1625 if (useTso && !tsoLoadedHeader) { 1626 // we need to fetch a header 1627 DPRINTF(EthernetDesc, "Starting DMA of TSO header\n"); 1628 assert(TxdOp::isData(desc) && TxdOp::getLen(desc) >= tsoHeaderLen); 1629 pktWaiting = true; 1630 assert(tsoHeaderLen <= 256); 1631 igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)), 1632 tsoHeaderLen, &headerEvent, tsoHeader, 0); 1633 } 1634} 1635 1636void 1637IGbE::TxDescCache::headerComplete() 1638{ 1639 DPRINTF(EthernetDesc, "TSO: Fetching TSO header complete\n"); 1640 pktWaiting = false; 1641 1642 assert(unusedCache.size()); 1643 TxDesc *desc = unusedCache.front(); 1644 DPRINTF(EthernetDesc, "TSO: len: %d tsoHeaderLen: %d\n", 1645 TxdOp::getLen(desc), tsoHeaderLen); 1646 1647 if (TxdOp::getLen(desc) == tsoHeaderLen) { 1648 tsoDescBytesUsed = 0; 1649 tsoLoadedHeader = true; 1650 unusedCache.pop_front(); 1651 usedCache.push_back(desc); 1652 } else { 1653 // I don't think this case happens, I think the headrer is always 1654 // it's own packet, if it wasn't it might be as simple as just 1655 // incrementing descBytesUsed by the header length, but I'm not 1656 // completely sure 1657 panic("TSO header part of bigger packet, not implemented\n"); 1658 } 1659 enableSm(); 1660 igbe->checkDrain(); 1661} 1662 1663unsigned 1664IGbE::TxDescCache::getPacketSize(EthPacketPtr p) 1665{ 1666 if (!unusedCache.size()) 1667 return 0; 1668 1669 DPRINTF(EthernetDesc, "Starting processing of descriptor\n"); 1670 1671 assert(!useTso || tsoLoadedHeader); 1672 TxDesc *desc = unusedCache.front(); 1673 1674 if (useTso) { 1675 DPRINTF(EthernetDesc, "getPacket(): TxDescriptor data " 1676 "d1: %#llx d2: %#llx\n", desc->d1, desc->d2); 1677 DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d " 1678 "used: %d loaded hdr: %d\n", useTso, tsoHeaderLen, tsoMss, 1679 tsoTotalLen, tsoUsedLen, tsoLoadedHeader); 1680 1681 if (tsoPktHasHeader) 1682 tsoCopyBytes = std::min((tsoMss + tsoHeaderLen) - p->length, 1683 TxdOp::getLen(desc) - tsoDescBytesUsed); 1684 else 1685 tsoCopyBytes = std::min(tsoMss, 1686 TxdOp::getLen(desc) - tsoDescBytesUsed); 1687 unsigned pkt_size = 1688 tsoCopyBytes + (tsoPktHasHeader ? 0 : tsoHeaderLen); 1689 1690 DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d " 1691 "this descLen: %d\n", 1692 tsoDescBytesUsed, tsoCopyBytes, TxdOp::getLen(desc)); 1693 DPRINTF(EthernetDesc, "TSO: pktHasHeader: %d\n", tsoPktHasHeader); 1694 DPRINTF(EthernetDesc, "TSO: Next packet is %d bytes\n", pkt_size); 1695 return pkt_size; 1696 } 1697 1698 DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n", 1699 TxdOp::getLen(unusedCache.front())); 1700 return TxdOp::getLen(desc); 1701} 1702 1703void 1704IGbE::TxDescCache::getPacketData(EthPacketPtr p) 1705{ 1706 assert(unusedCache.size()); 1707 1708 TxDesc *desc; 1709 desc = unusedCache.front(); 1710 1711 DPRINTF(EthernetDesc, "getPacketData(): TxDescriptor data " 1712 "d1: %#llx d2: %#llx\n", desc->d1, desc->d2); 1713 assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && 1714 TxdOp::getLen(desc)); 1715 1716 pktPtr = p; 1717 1718 pktWaiting = true; 1719 1720 DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length); 1721 1722 if (useTso) { 1723 assert(tsoLoadedHeader); 1724 if (!tsoPktHasHeader) { 1725 DPRINTF(EthernetDesc, 1726 "Loading TSO header (%d bytes) into start of packet\n", 1727 tsoHeaderLen); 1728 memcpy(p->data, &tsoHeader,tsoHeaderLen); 1729 p->length +=tsoHeaderLen; 1730 tsoPktHasHeader = true; 1731 } 1732 } 1733 1734 if (useTso) { 1735 DPRINTF(EthernetDesc, 1736 "Starting DMA of packet at offset %d length: %d\n", 1737 p->length, tsoCopyBytes); 1738 igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)) 1739 + tsoDescBytesUsed, 1740 tsoCopyBytes, &pktEvent, p->data + p->length, 1741 igbe->txReadDelay); 1742 tsoDescBytesUsed += tsoCopyBytes; 1743 assert(tsoDescBytesUsed <= TxdOp::getLen(desc)); 1744 } else { 1745 igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)), 1746 TxdOp::getLen(desc), &pktEvent, p->data + p->length, 1747 igbe->txReadDelay); 1748 } 1749} 1750 1751void 1752IGbE::TxDescCache::pktComplete() 1753{ 1754 1755 TxDesc *desc; 1756 assert(unusedCache.size()); 1757 assert(pktPtr); 1758 1759 igbe->anBegin("TXS", "Update Desc"); 1760 1761 DPRINTF(EthernetDesc, "DMA of packet complete\n"); 1762 1763 1764 desc = unusedCache.front(); 1765 assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && 1766 TxdOp::getLen(desc)); 1767 1768 DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", 1769 desc->d1, desc->d2); 1770 1771 // Set the length of the data in the EtherPacket 1772 if (useTso) { 1773 DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d " 1774 "used: %d loaded hdr: %d\n", useTso, tsoHeaderLen, tsoMss, 1775 tsoTotalLen, tsoUsedLen, tsoLoadedHeader); 1776 pktPtr->length += tsoCopyBytes; 1777 tsoUsedLen += tsoCopyBytes; 1778 DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d\n", 1779 tsoDescBytesUsed, tsoCopyBytes); 1780 } else 1781 pktPtr->length += TxdOp::getLen(desc); 1782 1783 1784 1785 if ((!TxdOp::eop(desc) && !useTso) || 1786 (pktPtr->length < ( tsoMss + tsoHeaderLen) && 1787 tsoTotalLen != tsoUsedLen && useTso)) { 1788 assert(!useTso || (tsoDescBytesUsed == TxdOp::getLen(desc))); 1789 igbe->anDq("TXS", annUnusedCacheQ); 1790 unusedCache.pop_front(); 1791 igbe->anQ("TXS", annUsedCacheQ); 1792 usedCache.push_back(desc); 1793 1794 tsoDescBytesUsed = 0; 1795 pktDone = true; 1796 pktWaiting = false; 1797 pktMultiDesc = true; 1798 1799 DPRINTF(EthernetDesc, "Partial Packet Descriptor of %d bytes Done\n", 1800 pktPtr->length); 1801 pktPtr = NULL; 1802 1803 enableSm(); 1804 igbe->checkDrain(); 1805 return; 1806 } 1807 1808 1809 pktMultiDesc = false; 1810 // no support for vlans 1811 assert(!TxdOp::vle(desc)); 1812 1813 // we only support single packet descriptors at this point 1814 if (!useTso) 1815 assert(TxdOp::eop(desc)); 1816 1817 // set that this packet is done 1818 if (TxdOp::rs(desc)) 1819 TxdOp::setDd(desc); 1820 1821 DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", 1822 desc->d1, desc->d2); 1823 1824 if (useTso) { 1825 IpPtr ip(pktPtr); 1826 if (ip) { 1827 DPRINTF(EthernetDesc, "TSO: Modifying IP header. Id + %d\n", 1828 tsoPkts); 1829 ip->id(ip->id() + tsoPkts++); 1830 ip->len(pktPtr->length - EthPtr(pktPtr)->size()); 1831 1832 TcpPtr tcp(ip); 1833 if (tcp) { 1834 DPRINTF(EthernetDesc, 1835 "TSO: Modifying TCP header. old seq %d + %d\n", 1836 tcp->seq(), tsoPrevSeq); 1837 tcp->seq(tcp->seq() + tsoPrevSeq); 1838 if (tsoUsedLen != tsoTotalLen) 1839 tcp->flags(tcp->flags() & ~9); // clear fin & psh 1840 } 1841 UdpPtr udp(ip); 1842 if (udp) { 1843 DPRINTF(EthernetDesc, "TSO: Modifying UDP header.\n"); 1844 udp->len(pktPtr->length - EthPtr(pktPtr)->size()); 1845 } 1846 } 1847 tsoPrevSeq = tsoUsedLen; 1848 } 1849 1850 if (DTRACE(EthernetDesc)) { 1851 IpPtr ip(pktPtr); 1852 if (ip) 1853 DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", 1854 ip->id()); 1855 else 1856 DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); 1857 } 1858 1859 // Checksums are only ofloaded for new descriptor types 1860 if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) { 1861 DPRINTF(EthernetDesc, "Calculating checksums for packet\n"); 1862 IpPtr ip(pktPtr); 1863 assert(ip); 1864 if (TxdOp::ixsm(desc)) { 1865 ip->sum(0); 1866 ip->sum(cksum(ip)); 1867 igbe->txIpChecksums++; 1868 DPRINTF(EthernetDesc, "Calculated IP checksum\n"); 1869 } 1870 if (TxdOp::txsm(desc)) { 1871 TcpPtr tcp(ip); 1872 UdpPtr udp(ip); 1873 if (tcp) { 1874 tcp->sum(0); 1875 tcp->sum(cksum(tcp)); 1876 igbe->txTcpChecksums++; 1877 DPRINTF(EthernetDesc, "Calculated TCP checksum\n"); 1878 } else if (udp) { 1879 assert(udp); 1880 udp->sum(0); 1881 udp->sum(cksum(udp)); 1882 igbe->txUdpChecksums++; 1883 DPRINTF(EthernetDesc, "Calculated UDP checksum\n"); 1884 } else { 1885 panic("Told to checksum, but don't know how\n"); 1886 } 1887 } 1888 } 1889 1890 if (TxdOp::ide(desc)) { 1891 // Deal with the rx timer interrupts 1892 DPRINTF(EthernetDesc, "Descriptor had IDE set\n"); 1893 if (igbe->regs.tidv.idv()) { 1894 Tick delay = igbe->regs.tidv.idv() * igbe->intClock(); 1895 DPRINTF(EthernetDesc, "setting tidv\n"); 1896 igbe->reschedule(igbe->tidvEvent, curTick() + delay, true); 1897 } 1898 1899 if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) { 1900 Tick delay = igbe->regs.tadv.idv() * igbe->intClock(); 1901 DPRINTF(EthernetDesc, "setting tadv\n"); 1902 if (!igbe->tadvEvent.scheduled()) { 1903 igbe->schedule(igbe->tadvEvent, curTick() + delay); 1904 } 1905 } 1906 } 1907 1908 1909 if (!useTso || TxdOp::getLen(desc) == tsoDescBytesUsed) { 1910 DPRINTF(EthernetDesc, "Descriptor Done\n"); 1911 igbe->anDq("TXS", annUnusedCacheQ); 1912 unusedCache.pop_front(); 1913 igbe->anQ("TXS", annUsedCacheQ); 1914 usedCache.push_back(desc); 1915 tsoDescBytesUsed = 0; 1916 } 1917 1918 if (useTso && tsoUsedLen == tsoTotalLen) 1919 useTso = false; 1920 1921 1922 DPRINTF(EthernetDesc, 1923 "------Packet of %d bytes ready for transmission-------\n", 1924 pktPtr->length); 1925 pktDone = true; 1926 pktWaiting = false; 1927 pktPtr = NULL; 1928 tsoPktHasHeader = false; 1929 1930 if (igbe->regs.txdctl.wthresh() == 0) { 1931 igbe->anBegin("TXS", "Desc Writeback"); 1932 DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n"); 1933 writeback(0); 1934 } else if (!igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() <= 1935 descInBlock(usedCache.size())) { 1936 DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); 1937 igbe->anBegin("TXS", "Desc Writeback"); 1938 writeback((igbe->cacheBlockSize()-1)>>4); 1939 } else if (igbe->regs.txdctl.wthresh() <= usedCache.size()) { 1940 DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); 1941 igbe->anBegin("TXS", "Desc Writeback"); 1942 writeback((igbe->cacheBlockSize()-1)>>4); 1943 } 1944 1945 enableSm(); 1946 igbe->checkDrain(); 1947} 1948 1949void 1950IGbE::TxDescCache::actionAfterWb() 1951{ 1952 DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n", 1953 completionEnabled); 1954 igbe->postInterrupt(iGbReg::IT_TXDW); 1955 if (completionEnabled) { 1956 descEnd = igbe->regs.tdh(); 1957 DPRINTF(EthernetDesc, 1958 "Completion writing back value: %d to addr: %#x\n", descEnd, 1959 completionAddress); 1960 igbe->dmaWrite(pciToDma(mbits(completionAddress, 63, 2)), 1961 sizeof(descEnd), &nullEvent, (uint8_t*)&descEnd, 0); 1962 } 1963} 1964 1965void 1966IGbE::TxDescCache::serialize(std::ostream &os) 1967{ 1968 DescCache<TxDesc>::serialize(os); 1969 SERIALIZE_SCALAR(pktDone); 1970 SERIALIZE_SCALAR(isTcp); 1971 SERIALIZE_SCALAR(pktWaiting); 1972 SERIALIZE_SCALAR(pktMultiDesc); 1973 1974 SERIALIZE_SCALAR(useTso); 1975 SERIALIZE_SCALAR(tsoHeaderLen); 1976 SERIALIZE_SCALAR(tsoMss); 1977 SERIALIZE_SCALAR(tsoTotalLen); 1978 SERIALIZE_SCALAR(tsoUsedLen); 1979 SERIALIZE_SCALAR(tsoPrevSeq);; 1980 SERIALIZE_SCALAR(tsoPktPayloadBytes); 1981 SERIALIZE_SCALAR(tsoLoadedHeader); 1982 SERIALIZE_SCALAR(tsoPktHasHeader); 1983 SERIALIZE_ARRAY(tsoHeader, 256); 1984 SERIALIZE_SCALAR(tsoDescBytesUsed); 1985 SERIALIZE_SCALAR(tsoCopyBytes); 1986 SERIALIZE_SCALAR(tsoPkts); 1987 1988 SERIALIZE_SCALAR(completionAddress); 1989 SERIALIZE_SCALAR(completionEnabled); 1990 SERIALIZE_SCALAR(descEnd); 1991} 1992 1993void 1994IGbE::TxDescCache::unserialize(Checkpoint *cp, const std::string §ion) 1995{ 1996 DescCache<TxDesc>::unserialize(cp, section); 1997 UNSERIALIZE_SCALAR(pktDone); 1998 UNSERIALIZE_SCALAR(isTcp); 1999 UNSERIALIZE_SCALAR(pktWaiting); 2000 UNSERIALIZE_SCALAR(pktMultiDesc); 2001 2002 UNSERIALIZE_SCALAR(useTso); 2003 UNSERIALIZE_SCALAR(tsoHeaderLen); 2004 UNSERIALIZE_SCALAR(tsoMss); 2005 UNSERIALIZE_SCALAR(tsoTotalLen); 2006 UNSERIALIZE_SCALAR(tsoUsedLen); 2007 UNSERIALIZE_SCALAR(tsoPrevSeq);; 2008 UNSERIALIZE_SCALAR(tsoPktPayloadBytes); 2009 UNSERIALIZE_SCALAR(tsoLoadedHeader); 2010 UNSERIALIZE_SCALAR(tsoPktHasHeader); 2011 UNSERIALIZE_ARRAY(tsoHeader, 256); 2012 UNSERIALIZE_SCALAR(tsoDescBytesUsed); 2013 UNSERIALIZE_SCALAR(tsoCopyBytes); 2014 UNSERIALIZE_SCALAR(tsoPkts); 2015 2016 UNSERIALIZE_SCALAR(completionAddress); 2017 UNSERIALIZE_SCALAR(completionEnabled); 2018 UNSERIALIZE_SCALAR(descEnd); 2019} 2020 2021bool 2022IGbE::TxDescCache::packetAvailable() 2023{ 2024 if (pktDone) { 2025 pktDone = false; 2026 return true; 2027 } 2028 return false; 2029} 2030 2031void 2032IGbE::TxDescCache::enableSm() 2033{ 2034 if (!igbe->drainEvent) { 2035 igbe->txTick = true; 2036 igbe->restartClock(); 2037 } 2038} 2039 2040bool 2041IGbE::TxDescCache::hasOutstandingEvents() 2042{ 2043 return pktEvent.scheduled() || wbEvent.scheduled() || 2044 fetchEvent.scheduled(); 2045} 2046 2047 2048///////////////////////////////////// IGbE ///////////////////////////////// 2049 2050void 2051IGbE::restartClock() 2052{ 2053 if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && 2054 getState() == SimObject::Running) 2055 schedule(tickEvent, clockEdge(Cycles(1))); 2056} 2057 2058unsigned int 2059IGbE::drain(Event *de) 2060{ 2061 unsigned int count; 2062 count = pioPort.drain(de) + dmaPort.drain(de); 2063 if (rxDescCache.hasOutstandingEvents() || 2064 txDescCache.hasOutstandingEvents()) { 2065 count++; 2066 drainEvent = de; 2067 } 2068 2069 txFifoTick = false; 2070 txTick = false; 2071 rxTick = false; 2072 2073 if (tickEvent.scheduled()) 2074 deschedule(tickEvent); 2075 2076 if (count) { 2077 DPRINTF(Drain, "IGbE not drained\n"); 2078 changeState(Draining); 2079 } else 2080 changeState(Drained); 2081 2082 return count; 2083} 2084 2085void 2086IGbE::resume() 2087{ 2088 SimObject::resume(); 2089 2090 txFifoTick = true; 2091 txTick = true; 2092 rxTick = true; 2093 2094 restartClock(); 2095 DPRINTF(EthernetSM, "resuming from drain"); 2096} 2097 2098void 2099IGbE::checkDrain() 2100{ 2101 if (!drainEvent) 2102 return; 2103 2104 txFifoTick = false; 2105 txTick = false; 2106 rxTick = false; 2107 if (!rxDescCache.hasOutstandingEvents() && 2108 !txDescCache.hasOutstandingEvents()) { 2109 DPRINTF(Drain, "IGbE done draining, processing drain event\n"); 2110 drainEvent->process(); 2111 drainEvent = NULL; 2112 } 2113} 2114 2115void 2116IGbE::txStateMachine() 2117{ 2118 if (!regs.tctl.en()) { 2119 txTick = false; 2120 DPRINTF(EthernetSM, "TXS: TX disabled, stopping ticking\n"); 2121 return; 2122 } 2123 2124 // If we have a packet available and it's length is not 0 (meaning it's not 2125 // a multidescriptor packet) put it in the fifo, otherwise an the next 2126 // iteration we'll get the rest of the data 2127 if (txPacket && txDescCache.packetAvailable() 2128 && !txDescCache.packetMultiDesc() && txPacket->length) { 2129 anQ("TXS", "TX FIFO Q"); 2130 DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n"); 2131#ifndef NDEBUG 2132 bool success = 2133#endif 2134 txFifo.push(txPacket); 2135 txFifoTick = true && !drainEvent; 2136 assert(success); 2137 txPacket = NULL; 2138 anBegin("TXS", "Desc Writeback"); 2139 txDescCache.writeback((cacheBlockSize()-1)>>4); 2140 return; 2141 } 2142 2143 // Only support descriptor granularity 2144 if (regs.txdctl.lwthresh() && 2145 txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) { 2146 DPRINTF(EthernetSM, "TXS: LWTHRESH caused posting of TXDLOW\n"); 2147 postInterrupt(IT_TXDLOW); 2148 } 2149 2150 if (!txPacket) { 2151 txPacket = new EthPacketData(16384); 2152 } 2153 2154 if (!txDescCache.packetWaiting()) { 2155 if (txDescCache.descLeft() == 0) { 2156 postInterrupt(IT_TXQE); 2157 anBegin("TXS", "Desc Writeback"); 2158 txDescCache.writeback(0); 2159 anBegin("TXS", "Desc Fetch"); 2160 anWe("TXS", txDescCache.annUnusedCacheQ); 2161 txDescCache.fetchDescriptors(); 2162 DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing " 2163 "writeback stopping ticking and posting TXQE\n"); 2164 txTick = false; 2165 return; 2166 } 2167 2168 2169 if (!(txDescCache.descUnused())) { 2170 anBegin("TXS", "Desc Fetch"); 2171 txDescCache.fetchDescriptors(); 2172 anWe("TXS", txDescCache.annUnusedCacheQ); 2173 DPRINTF(EthernetSM, "TXS: No descriptors available in cache, " 2174 "fetching and stopping ticking\n"); 2175 txTick = false; 2176 return; 2177 } 2178 anPq("TXS", txDescCache.annUnusedCacheQ); 2179 2180 2181 txDescCache.processContextDesc(); 2182 if (txDescCache.packetWaiting()) { 2183 DPRINTF(EthernetSM, 2184 "TXS: Fetching TSO header, stopping ticking\n"); 2185 txTick = false; 2186 return; 2187 } 2188 2189 unsigned size = txDescCache.getPacketSize(txPacket); 2190 if (size > 0 && txFifo.avail() > size) { 2191 anRq("TXS", "TX FIFO Q"); 2192 anBegin("TXS", "DMA Packet"); 2193 DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and " 2194 "beginning DMA of next packet\n", size); 2195 txFifo.reserve(size); 2196 txDescCache.getPacketData(txPacket); 2197 } else if (size == 0) { 2198 DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size); 2199 DPRINTF(EthernetSM, 2200 "TXS: No packets to get, writing back used descriptors\n"); 2201 anBegin("TXS", "Desc Writeback"); 2202 txDescCache.writeback(0); 2203 } else { 2204 anWf("TXS", "TX FIFO Q"); 2205 DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space " 2206 "available in FIFO\n"); 2207 txTick = false; 2208 } 2209 2210 2211 return; 2212 } 2213 DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n"); 2214 txTick = false; 2215} 2216 2217bool 2218IGbE::ethRxPkt(EthPacketPtr pkt) 2219{ 2220 rxBytes += pkt->length; 2221 rxPackets++; 2222 2223 DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n"); 2224 anBegin("RXQ", "Wire Recv"); 2225 2226 2227 if (!regs.rctl.en()) { 2228 DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n"); 2229 anBegin("RXQ", "FIFO Drop", CPA::FL_BAD); 2230 return true; 2231 } 2232 2233 // restart the state machines if they are stopped 2234 rxTick = true && !drainEvent; 2235 if ((rxTick || txTick) && !tickEvent.scheduled()) { 2236 DPRINTF(EthernetSM, 2237 "RXS: received packet into fifo, starting ticking\n"); 2238 restartClock(); 2239 } 2240 2241 if (!rxFifo.push(pkt)) { 2242 DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n"); 2243 postInterrupt(IT_RXO, true); 2244 anBegin("RXQ", "FIFO Drop", CPA::FL_BAD); 2245 return false; 2246 } 2247 2248 if (CPA::available() && cpa->enabled()) { 2249 assert(sys->numSystemsRunning <= 2); 2250 System *other_sys; 2251 if (sys->systemList[0] == sys) 2252 other_sys = sys->systemList[1]; 2253 else 2254 other_sys = sys->systemList[0]; 2255 2256 cpa->hwDq(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys); 2257 anQ("RXQ", "RX FIFO Q"); 2258 cpa->hwWe(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys); 2259 } 2260 2261 return true; 2262} 2263 2264 2265void 2266IGbE::rxStateMachine() 2267{ 2268 if (!regs.rctl.en()) { 2269 rxTick = false; 2270 DPRINTF(EthernetSM, "RXS: RX disabled, stopping ticking\n"); 2271 return; 2272 } 2273 2274 // If the packet is done check for interrupts/descriptors/etc 2275 if (rxDescCache.packetDone()) { 2276 rxDmaPacket = false; 2277 DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n"); 2278 int descLeft = rxDescCache.descLeft(); 2279 DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n", 2280 descLeft, regs.rctl.rdmts(), regs.rdlen()); 2281 switch (regs.rctl.rdmts()) { 2282 case 2: if (descLeft > .125 * regs.rdlen()) break; 2283 case 1: if (descLeft > .250 * regs.rdlen()) break; 2284 case 0: if (descLeft > .500 * regs.rdlen()) break; 2285 DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) " 2286 "because of descriptors left\n"); 2287 postInterrupt(IT_RXDMT); 2288 break; 2289 } 2290 2291 if (rxFifo.empty()) 2292 rxDescCache.writeback(0); 2293 2294 if (descLeft == 0) { 2295 anBegin("RXS", "Writeback Descriptors"); 2296 rxDescCache.writeback(0); 2297 DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing" 2298 " writeback and stopping ticking\n"); 2299 rxTick = false; 2300 } 2301 2302 // only support descriptor granulaties 2303 assert(regs.rxdctl.gran()); 2304 2305 if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) { 2306 DPRINTF(EthernetSM, 2307 "RXS: Writing back because WTHRESH >= descUsed\n"); 2308 anBegin("RXS", "Writeback Descriptors"); 2309 if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4)) 2310 rxDescCache.writeback(regs.rxdctl.wthresh()-1); 2311 else 2312 rxDescCache.writeback((cacheBlockSize()-1)>>4); 2313 } 2314 2315 if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) && 2316 ((rxDescCache.descLeft() - rxDescCache.descUnused()) > 2317 regs.rxdctl.hthresh())) { 2318 DPRINTF(EthernetSM, "RXS: Fetching descriptors because " 2319 "descUnused < PTHRESH\n"); 2320 anBegin("RXS", "Fetch Descriptors"); 2321 rxDescCache.fetchDescriptors(); 2322 } 2323 2324 if (rxDescCache.descUnused() == 0) { 2325 anBegin("RXS", "Fetch Descriptors"); 2326 rxDescCache.fetchDescriptors(); 2327 anWe("RXS", rxDescCache.annUnusedCacheQ); 2328 DPRINTF(EthernetSM, "RXS: No descriptors available in cache, " 2329 "fetching descriptors and stopping ticking\n"); 2330 rxTick = false; 2331 } 2332 return; 2333 } 2334 2335 if (rxDmaPacket) { 2336 DPRINTF(EthernetSM, 2337 "RXS: stopping ticking until packet DMA completes\n"); 2338 rxTick = false; 2339 return; 2340 } 2341 2342 if (!rxDescCache.descUnused()) { 2343 anBegin("RXS", "Fetch Descriptors"); 2344 rxDescCache.fetchDescriptors(); 2345 anWe("RXS", rxDescCache.annUnusedCacheQ); 2346 DPRINTF(EthernetSM, "RXS: No descriptors available in cache, " 2347 "stopping ticking\n"); 2348 rxTick = false; 2349 DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n"); 2350 return; 2351 } 2352 anPq("RXS", rxDescCache.annUnusedCacheQ); 2353 2354 if (rxFifo.empty()) { 2355 anWe("RXS", "RX FIFO Q"); 2356 DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n"); 2357 rxTick = false; 2358 return; 2359 } 2360 anPq("RXS", "RX FIFO Q"); 2361 anBegin("RXS", "Get Desc"); 2362 2363 EthPacketPtr pkt; 2364 pkt = rxFifo.front(); 2365 2366 2367 pktOffset = rxDescCache.writePacket(pkt, pktOffset); 2368 DPRINTF(EthernetSM, "RXS: Writing packet into memory\n"); 2369 if (pktOffset == pkt->length) { 2370 anBegin( "RXS", "FIFO Dequeue"); 2371 DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n"); 2372 pktOffset = 0; 2373 anDq("RXS", "RX FIFO Q"); 2374 rxFifo.pop(); 2375 } 2376 2377 DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); 2378 rxTick = false; 2379 rxDmaPacket = true; 2380 anBegin("RXS", "DMA Packet"); 2381} 2382 2383void 2384IGbE::txWire() 2385{ 2386 if (txFifo.empty()) { 2387 anWe("TXQ", "TX FIFO Q"); 2388 txFifoTick = false; 2389 return; 2390 } 2391 2392 2393 anPq("TXQ", "TX FIFO Q"); 2394 if (etherInt->sendPacket(txFifo.front())) { 2395 cpa->hwQ(CPA::FL_NONE, sys, macAddr, "TXQ", "WireQ", 0); 2396 if (DTRACE(EthernetSM)) { 2397 IpPtr ip(txFifo.front()); 2398 if (ip) 2399 DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n", 2400 ip->id()); 2401 else 2402 DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n"); 2403 } 2404 anDq("TXQ", "TX FIFO Q"); 2405 anBegin("TXQ", "Wire Send"); 2406 DPRINTF(EthernetSM, 2407 "TxFIFO: Successful transmit, bytes available in fifo: %d\n", 2408 txFifo.avail()); 2409 2410 txBytes += txFifo.front()->length; 2411 txPackets++; 2412 txFifoTick = false; 2413 2414 txFifo.pop(); 2415 } else { 2416 // We'll get woken up when the packet ethTxDone() gets called 2417 txFifoTick = false; 2418 } 2419} 2420 2421void 2422IGbE::tick() 2423{ 2424 DPRINTF(EthernetSM, "IGbE: -------------- Cycle --------------\n"); 2425 2426 if (rxTick) 2427 rxStateMachine(); 2428 2429 if (txTick) 2430 txStateMachine(); 2431 2432 if (txFifoTick) 2433 txWire(); 2434 2435 2436 if (rxTick || txTick || txFifoTick) 2437 schedule(tickEvent, curTick() + clockPeriod()); 2438} 2439 2440void 2441IGbE::ethTxDone() 2442{ 2443 anBegin("TXQ", "Send Done"); 2444 // restart the tx state machines if they are stopped 2445 // fifo to send another packet 2446 // tx sm to put more data into the fifo 2447 txFifoTick = true && !drainEvent; 2448 if (txDescCache.descLeft() != 0 && !drainEvent) 2449 txTick = true; 2450 2451 restartClock(); 2452 txWire(); 2453 DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n"); 2454} 2455 2456void 2457IGbE::serialize(std::ostream &os) 2458{ 2459 PciDev::serialize(os); 2460 2461 regs.serialize(os); 2462 SERIALIZE_SCALAR(eeOpBits); 2463 SERIALIZE_SCALAR(eeAddrBits); 2464 SERIALIZE_SCALAR(eeDataBits); 2465 SERIALIZE_SCALAR(eeOpcode); 2466 SERIALIZE_SCALAR(eeAddr); 2467 SERIALIZE_SCALAR(lastInterrupt); 2468 SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE); 2469 2470 rxFifo.serialize("rxfifo", os); 2471 txFifo.serialize("txfifo", os); 2472 2473 bool txPktExists = txPacket; 2474 SERIALIZE_SCALAR(txPktExists); 2475 if (txPktExists) 2476 txPacket->serialize("txpacket", os); 2477 2478 Tick rdtr_time = 0, radv_time = 0, tidv_time = 0, tadv_time = 0, 2479 inter_time = 0; 2480 2481 if (rdtrEvent.scheduled()) 2482 rdtr_time = rdtrEvent.when(); 2483 SERIALIZE_SCALAR(rdtr_time); 2484 2485 if (radvEvent.scheduled()) 2486 radv_time = radvEvent.when(); 2487 SERIALIZE_SCALAR(radv_time); 2488 2489 if (tidvEvent.scheduled()) 2490 tidv_time = tidvEvent.when(); 2491 SERIALIZE_SCALAR(tidv_time); 2492 2493 if (tadvEvent.scheduled()) 2494 tadv_time = tadvEvent.when(); 2495 SERIALIZE_SCALAR(tadv_time); 2496 2497 if (interEvent.scheduled()) 2498 inter_time = interEvent.when(); 2499 SERIALIZE_SCALAR(inter_time); 2500 2501 SERIALIZE_SCALAR(pktOffset); 2502 2503 nameOut(os, csprintf("%s.TxDescCache", name())); 2504 txDescCache.serialize(os); 2505 2506 nameOut(os, csprintf("%s.RxDescCache", name())); 2507 rxDescCache.serialize(os); 2508} 2509 2510void 2511IGbE::unserialize(Checkpoint *cp, const std::string §ion) 2512{ 2513 PciDev::unserialize(cp, section); 2514 2515 regs.unserialize(cp, section); 2516 UNSERIALIZE_SCALAR(eeOpBits); 2517 UNSERIALIZE_SCALAR(eeAddrBits); 2518 UNSERIALIZE_SCALAR(eeDataBits); 2519 UNSERIALIZE_SCALAR(eeOpcode); 2520 UNSERIALIZE_SCALAR(eeAddr); 2521 UNSERIALIZE_SCALAR(lastInterrupt); 2522 UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE); 2523 2524 rxFifo.unserialize("rxfifo", cp, section); 2525 txFifo.unserialize("txfifo", cp, section); 2526 2527 bool txPktExists; 2528 UNSERIALIZE_SCALAR(txPktExists); 2529 if (txPktExists) { 2530 txPacket = new EthPacketData(16384); 2531 txPacket->unserialize("txpacket", cp, section); 2532 } 2533 2534 rxTick = true; 2535 txTick = true; 2536 txFifoTick = true; 2537 2538 Tick rdtr_time, radv_time, tidv_time, tadv_time, inter_time; 2539 UNSERIALIZE_SCALAR(rdtr_time); 2540 UNSERIALIZE_SCALAR(radv_time); 2541 UNSERIALIZE_SCALAR(tidv_time); 2542 UNSERIALIZE_SCALAR(tadv_time); 2543 UNSERIALIZE_SCALAR(inter_time); 2544 2545 if (rdtr_time) 2546 schedule(rdtrEvent, rdtr_time); 2547 2548 if (radv_time) 2549 schedule(radvEvent, radv_time); 2550 2551 if (tidv_time) 2552 schedule(tidvEvent, tidv_time); 2553 2554 if (tadv_time) 2555 schedule(tadvEvent, tadv_time); 2556 2557 if (inter_time) 2558 schedule(interEvent, inter_time); 2559 2560 UNSERIALIZE_SCALAR(pktOffset); 2561 2562 txDescCache.unserialize(cp, csprintf("%s.TxDescCache", section)); 2563 2564 rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section)); 2565} 2566 2567IGbE * 2568IGbEParams::create() 2569{ 2570 return new IGbE(this); 2571} 2572