i8254xGBe.cc revision 5762 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
34 * fewest workarounds in the driver. It will probably work with most of the
35 * other MACs with slight modifications.
36 */
37
38
39/*
40 * @todo really there are multiple dma engines.. we should implement them.
41 */
42
43#include <algorithm>
44
45#include "base/inet.hh"
46#include "base/trace.hh"
47#include "dev/i8254xGBe.hh"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50#include "params/IGbE.hh"
51#include "sim/stats.hh"
52#include "sim/system.hh"
53
54using namespace iGbReg;
55using namespace Net;
56
57IGbE::IGbE(const Params *p)
58    : EtherDevice(p), etherInt(NULL),  drainEvent(NULL), useFlowControl(p->use_flow_control),
59      rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
60      txTick(false), txFifoTick(false), rxDmaPacket(false),
61      fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
62      fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay),
63      rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),
64      rdtrEvent(this), radvEvent(this),
65      tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
66      rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
67      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
68      clock(p->clock), lastInterrupt(0)
69{
70    etherInt = new IGbEInt(name() + ".int", this);
71
72    // Initialized internal registers per Intel documentation
73    // All registers intialized to 0 by per register constructor
74    regs.ctrl.fd(1);
75    regs.ctrl.lrst(1);
76    regs.ctrl.speed(2);
77    regs.ctrl.frcspd(1);
78    regs.sts.speed(3); // Say we're 1000Mbps
79    regs.sts.fd(1); // full duplex
80    regs.sts.lu(1); // link up
81    regs.eecd.fwe(1);
82    regs.eecd.ee_type(1);
83    regs.imr = 0;
84    regs.iam = 0;
85    regs.rxdctl.gran(1);
86    regs.rxdctl.wthresh(1);
87    regs.fcrth(1);
88
89    regs.pba.rxa(0x30);
90    regs.pba.txa(0x10);
91
92    eeOpBits            = 0;
93    eeAddrBits          = 0;
94    eeDataBits          = 0;
95    eeOpcode            = 0;
96
97    // clear all 64 16 bit words of the eeprom
98    memset(&flash, 0, EEPROM_SIZE*2);
99
100    // Set the MAC address
101    memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN);
102    for (int x = 0; x < ETH_ADDR_LEN/2; x++)
103        flash[x] = htobe(flash[x]);
104
105    uint16_t csum = 0;
106    for (int x = 0; x < EEPROM_SIZE; x++)
107        csum += htobe(flash[x]);
108
109
110    // Magic happy checksum value
111    flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum));
112
113    rxFifo.clear();
114    txFifo.clear();
115}
116
117EtherInt*
118IGbE::getEthPort(const std::string &if_name, int idx)
119{
120
121    if (if_name == "interface") {
122        if (etherInt->getPeer())
123            panic("Port already connected to\n");
124        return etherInt;
125    }
126    return NULL;
127}
128
129Tick
130IGbE::writeConfig(PacketPtr pkt)
131{
132    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
133    if (offset < PCI_DEVICE_SPECIFIC)
134        PciDev::writeConfig(pkt);
135    else
136        panic("Device specific PCI config space not implemented.\n");
137
138    ///
139    /// Some work may need to be done here based for the pci COMMAND bits.
140    ///
141
142    return pioDelay;
143}
144
145Tick
146IGbE::read(PacketPtr pkt)
147{
148    int bar;
149    Addr daddr;
150
151    if (!getBAR(pkt->getAddr(), bar, daddr))
152        panic("Invalid PCI memory access to unmapped memory.\n");
153
154    // Only Memory register BAR is allowed
155    assert(bar == 0);
156
157    // Only 32bit accesses allowed
158    assert(pkt->getSize() == 4);
159
160    DPRINTF(Ethernet, "Read device register %#X\n", daddr);
161
162    pkt->allocate();
163
164    ///
165    /// Handle read of register here
166    ///
167
168
169    switch (daddr) {
170      case REG_CTRL:
171        pkt->set<uint32_t>(regs.ctrl());
172        break;
173      case REG_STATUS:
174        pkt->set<uint32_t>(regs.sts());
175        break;
176      case REG_EECD:
177        pkt->set<uint32_t>(regs.eecd());
178        break;
179      case REG_EERD:
180        pkt->set<uint32_t>(regs.eerd());
181        break;
182      case REG_CTRL_EXT:
183        pkt->set<uint32_t>(regs.ctrl_ext());
184        break;
185      case REG_MDIC:
186        pkt->set<uint32_t>(regs.mdic());
187        break;
188      case REG_ICR:
189        DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(),
190                regs.imr, regs.iam, regs.ctrl_ext.iame());
191        pkt->set<uint32_t>(regs.icr());
192        if (regs.icr.int_assert() || regs.imr == 0) {
193            regs.icr = regs.icr() & ~mask(30);
194            DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
195        }
196        if (regs.ctrl_ext.iame() && regs.icr.int_assert())
197            regs.imr &= ~regs.iam;
198        chkInterrupt();
199        break;
200      case REG_ITR:
201        pkt->set<uint32_t>(regs.itr());
202        break;
203      case REG_RCTL:
204        pkt->set<uint32_t>(regs.rctl());
205        break;
206      case REG_FCTTV:
207        pkt->set<uint32_t>(regs.fcttv());
208        break;
209      case REG_TCTL:
210        pkt->set<uint32_t>(regs.tctl());
211        break;
212      case REG_PBA:
213        pkt->set<uint32_t>(regs.pba());
214        break;
215      case REG_WUC:
216      case REG_LEDCTL:
217        pkt->set<uint32_t>(0); // We don't care, so just return 0
218        break;
219      case REG_FCRTL:
220        pkt->set<uint32_t>(regs.fcrtl());
221        break;
222      case REG_FCRTH:
223        pkt->set<uint32_t>(regs.fcrth());
224        break;
225      case REG_RDBAL:
226        pkt->set<uint32_t>(regs.rdba.rdbal());
227        break;
228      case REG_RDBAH:
229        pkt->set<uint32_t>(regs.rdba.rdbah());
230        break;
231      case REG_RDLEN:
232        pkt->set<uint32_t>(regs.rdlen());
233        break;
234      case REG_RDH:
235        pkt->set<uint32_t>(regs.rdh());
236        break;
237      case REG_RDT:
238        pkt->set<uint32_t>(regs.rdt());
239        break;
240      case REG_RDTR:
241        pkt->set<uint32_t>(regs.rdtr());
242        if (regs.rdtr.fpd()) {
243            rxDescCache.writeback(0);
244            DPRINTF(EthernetIntr, "Posting interrupt because of RDTR.FPD write\n");
245            postInterrupt(IT_RXT);
246            regs.rdtr.fpd(0);
247        }
248        break;
249      case REG_RADV:
250        pkt->set<uint32_t>(regs.radv());
251        break;
252      case REG_TDBAL:
253        pkt->set<uint32_t>(regs.tdba.tdbal());
254        break;
255      case REG_TDBAH:
256        pkt->set<uint32_t>(regs.tdba.tdbah());
257        break;
258      case REG_TDLEN:
259        pkt->set<uint32_t>(regs.tdlen());
260        break;
261      case REG_TDH:
262        pkt->set<uint32_t>(regs.tdh());
263        break;
264      case REG_TDT:
265        pkt->set<uint32_t>(regs.tdt());
266        break;
267      case REG_TIDV:
268        pkt->set<uint32_t>(regs.tidv());
269        break;
270      case REG_TXDCTL:
271        pkt->set<uint32_t>(regs.txdctl());
272        break;
273      case REG_TADV:
274        pkt->set<uint32_t>(regs.tadv());
275        break;
276      case REG_RXCSUM:
277        pkt->set<uint32_t>(regs.rxcsum());
278        break;
279      case REG_MANC:
280        pkt->set<uint32_t>(regs.manc());
281        break;
282      default:
283        if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) &&
284            !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) &&
285            !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)) &&
286            !(daddr >= REG_CRCERRS && daddr < (REG_CRCERRS + STATS_REGS_SIZE)))
287            panic("Read request to unknown register number: %#x\n", daddr);
288        else
289            pkt->set<uint32_t>(0);
290    };
291
292    pkt->makeAtomicResponse();
293    return pioDelay;
294}
295
296Tick
297IGbE::write(PacketPtr pkt)
298{
299    int bar;
300    Addr daddr;
301
302
303    if (!getBAR(pkt->getAddr(), bar, daddr))
304        panic("Invalid PCI memory access to unmapped memory.\n");
305
306    // Only Memory register BAR is allowed
307    assert(bar == 0);
308
309    // Only 32bit accesses allowed
310    assert(pkt->getSize() == sizeof(uint32_t));
311
312    DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>());
313
314    ///
315    /// Handle write of register here
316    ///
317    uint32_t val = pkt->get<uint32_t>();
318
319    Regs::RCTL oldrctl;
320    Regs::TCTL oldtctl;
321
322    switch (daddr) {
323      case REG_CTRL:
324        regs.ctrl = val;
325        if (regs.ctrl.tfce())
326            warn("TX Flow control enabled, should implement\n");
327        if (regs.ctrl.rfce())
328            warn("RX Flow control enabled, should implement\n");
329        break;
330      case REG_CTRL_EXT:
331        regs.ctrl_ext = val;
332        break;
333      case REG_STATUS:
334        regs.sts = val;
335        break;
336      case REG_EECD:
337        int oldClk;
338        oldClk = regs.eecd.sk();
339        regs.eecd = val;
340        // See if this is a eeprom access and emulate accordingly
341        if (!oldClk && regs.eecd.sk()) {
342            if (eeOpBits < 8) {
343                eeOpcode = eeOpcode << 1 | regs.eecd.din();
344                eeOpBits++;
345            } else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
346                eeAddr = eeAddr << 1 | regs.eecd.din();
347                eeAddrBits++;
348            } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
349                assert(eeAddr>>1 < EEPROM_SIZE);
350                DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n",
351                        flash[eeAddr>>1] >> eeDataBits & 0x1, flash[eeAddr>>1]);
352                regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1);
353                eeDataBits++;
354            } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) {
355                regs.eecd.dout(0);
356                eeDataBits++;
357            } else
358                panic("What's going on with eeprom interface? opcode:"
359                       " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
360                       (uint32_t)eeOpBits, (uint32_t)eeAddr,
361                       (uint32_t)eeAddrBits, (uint32_t)eeDataBits);
362
363            // Reset everything for the next command
364            if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) ||
365               (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
366                eeOpBits = 0;
367                eeAddrBits = 0;
368                eeDataBits = 0;
369               eeOpcode = 0;
370                eeAddr = 0;
371            }
372
373           DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
374                    (uint32_t)eeOpcode, (uint32_t) eeOpBits,
375                    (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits);
376           if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
377                                   eeOpcode == EEPROM_RDSR_OPCODE_SPI ))
378                panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode,
379                        (uint32_t)eeOpBits);
380
381
382        }
383        // If driver requests eeprom access, immediately give it to it
384        regs.eecd.ee_gnt(regs.eecd.ee_req());
385        break;
386      case REG_EERD:
387        regs.eerd = val;
388        break;
389      case REG_MDIC:
390        regs.mdic = val;
391        if (regs.mdic.i())
392            panic("No support for interrupt on mdic complete\n");
393        if (regs.mdic.phyadd() != 1)
394            panic("No support for reading anything but phy\n");
395        DPRINTF(Ethernet, "%s phy address %x\n", regs.mdic.op() == 1 ? "Writing"
396                : "Reading", regs.mdic.regadd());
397        switch (regs.mdic.regadd()) {
398            case PHY_PSTATUS:
399                regs.mdic.data(0x796D); // link up
400                break;
401            case PHY_PID:
402                regs.mdic.data(0x02A8);
403                break;
404            case PHY_EPID:
405                regs.mdic.data(0x0380);
406                break;
407            case PHY_GSTATUS:
408                regs.mdic.data(0x7C00);
409                break;
410            case PHY_EPSTATUS:
411                regs.mdic.data(0x3000);
412                break;
413            case PHY_AGC:
414                regs.mdic.data(0x180); // some random length
415                break;
416            default:
417                regs.mdic.data(0);
418        }
419        regs.mdic.r(1);
420        break;
421      case REG_ICR:
422        DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(),
423                regs.imr, regs.iam, regs.ctrl_ext.iame());
424        if (regs.ctrl_ext.iame())
425            regs.imr &= ~regs.iam;
426        regs.icr = ~bits(val,30,0) & regs.icr();
427        chkInterrupt();
428        break;
429      case REG_ITR:
430        regs.itr = val;
431        break;
432      case REG_ICS:
433        DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n");
434        postInterrupt((IntTypes)val);
435        break;
436       case REG_IMS:
437        regs.imr |= val;
438        chkInterrupt();
439        break;
440      case REG_IMC:
441        regs.imr &= ~val;
442        chkInterrupt();
443        break;
444      case REG_IAM:
445        regs.iam = val;
446        break;
447      case REG_RCTL:
448        oldrctl = regs.rctl;
449        regs.rctl = val;
450        if (regs.rctl.rst()) {
451            rxDescCache.reset();
452            DPRINTF(EthernetSM, "RXS: Got RESET!\n");
453            rxFifo.clear();
454            regs.rctl.rst(0);
455        }
456        if (regs.rctl.en())
457            rxTick = true;
458        restartClock();
459        break;
460      case REG_FCTTV:
461        regs.fcttv = val;
462        break;
463      case REG_TCTL:
464        regs.tctl = val;
465        oldtctl = regs.tctl;
466        regs.tctl = val;
467        if (regs.tctl.en())
468           txTick = true;
469        restartClock();
470        if (regs.tctl.en() && !oldtctl.en()) {
471            txDescCache.reset();
472        }
473         break;
474      case REG_PBA:
475        regs.pba.rxa(val);
476        regs.pba.txa(64 - regs.pba.rxa());
477        break;
478      case REG_WUC:
479      case REG_LEDCTL:
480      case REG_FCAL:
481      case REG_FCAH:
482      case REG_FCT:
483      case REG_VET:
484      case REG_AIFS:
485      case REG_TIPG:
486        ; // We don't care, so don't store anything
487        break;
488      case REG_FCRTL:
489        regs.fcrtl = val;
490        break;
491      case REG_FCRTH:
492        regs.fcrth = val;
493        break;
494      case REG_RDBAL:
495        regs.rdba.rdbal( val & ~mask(4));
496        rxDescCache.areaChanged();
497        break;
498      case REG_RDBAH:
499        regs.rdba.rdbah(val);
500        rxDescCache.areaChanged();
501        break;
502      case REG_RDLEN:
503        regs.rdlen = val & ~mask(7);
504        rxDescCache.areaChanged();
505        break;
506      case REG_RDH:
507        regs.rdh = val;
508        rxDescCache.areaChanged();
509        break;
510      case REG_RDT:
511        regs.rdt = val;
512        DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
513        if (getState() == SimObject::Running) {
514            DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
515            rxDescCache.fetchDescriptors();
516        } else {
517            DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n");
518        }
519        break;
520      case REG_RDTR:
521        regs.rdtr = val;
522        break;
523      case REG_RADV:
524        regs.radv = val;
525        break;
526      case REG_TDBAL:
527        regs.tdba.tdbal( val & ~mask(4));
528        txDescCache.areaChanged();
529        break;
530      case REG_TDBAH:
531        regs.tdba.tdbah(val);
532        txDescCache.areaChanged();
533        break;
534      case REG_TDLEN:
535        regs.tdlen = val & ~mask(7);
536        txDescCache.areaChanged();
537        break;
538      case REG_TDH:
539        regs.tdh = val;
540        txDescCache.areaChanged();
541        break;
542      case REG_TDT:
543        regs.tdt = val;
544        DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
545        if (getState() == SimObject::Running) {
546            DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
547            txDescCache.fetchDescriptors();
548        } else {
549            DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n");
550        }
551        break;
552      case REG_TIDV:
553        regs.tidv = val;
554        break;
555      case REG_TXDCTL:
556        regs.txdctl = val;
557        break;
558      case REG_TADV:
559        regs.tadv = val;
560        break;
561      case REG_RXCSUM:
562        regs.rxcsum = val;
563        break;
564      case REG_MANC:
565        regs.manc = val;
566        break;
567      default:
568       if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) &&
569           !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) &&
570           !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)))
571           panic("Write request to unknown register number: %#x\n", daddr);
572    };
573
574    pkt->makeAtomicResponse();
575    return pioDelay;
576}
577
578void
579IGbE::postInterrupt(IntTypes t, bool now)
580{
581    assert(t);
582
583    // Interrupt is already pending
584    if (t & regs.icr() && !now)
585        return;
586
587    regs.icr = regs.icr() | t;
588
589    Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
590    DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
591            curTick, regs.itr.interval(), itr_interval);
592
593    if (regs.itr.interval() == 0 || now || lastInterrupt + itr_interval <= curTick) {
594        if (interEvent.scheduled()) {
595            deschedule(interEvent);
596        }
597        cpuPostInt();
598    } else {
599       Tick int_time = lastInterrupt + itr_interval;
600       assert(int_time > 0);
601       DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
602                int_time);
603       if (!interEvent.scheduled()) {
604           schedule(interEvent, int_time);
605       }
606    }
607}
608
609void
610IGbE::delayIntEvent()
611{
612    cpuPostInt();
613}
614
615
616void
617IGbE::cpuPostInt()
618{
619
620    postedInterrupts++;
621
622    if (!(regs.icr() & regs.imr)) {
623        DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
624        return;
625    }
626
627    DPRINTF(Ethernet, "Posting Interrupt\n");
628
629
630    if (interEvent.scheduled()) {
631        deschedule(interEvent);
632    }
633
634    if (rdtrEvent.scheduled()) {
635        regs.icr.rxt0(1);
636        deschedule(rdtrEvent);
637    }
638    if (radvEvent.scheduled()) {
639        regs.icr.rxt0(1);
640        deschedule(radvEvent);
641    }
642    if (tadvEvent.scheduled()) {
643        regs.icr.txdw(1);
644        deschedule(tadvEvent);
645    }
646    if (tidvEvent.scheduled()) {
647        regs.icr.txdw(1);
648        deschedule(tidvEvent);
649    }
650
651    regs.icr.int_assert(1);
652    DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
653            regs.icr());
654
655    intrPost();
656
657    lastInterrupt = curTick;
658}
659
660void
661IGbE::cpuClearInt()
662{
663    if (regs.icr.int_assert()) {
664        regs.icr.int_assert(0);
665        DPRINTF(EthernetIntr, "EINT: Clearing interrupt to CPU now. Vector %#x\n",
666                regs.icr());
667        intrClear();
668    }
669}
670
671void
672IGbE::chkInterrupt()
673{
674    DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(),
675            regs.imr);
676    // Check if we need to clear the cpu interrupt
677    if (!(regs.icr() & regs.imr)) {
678        DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
679        if (interEvent.scheduled())
680           deschedule(interEvent);
681        if (regs.icr.int_assert())
682            cpuClearInt();
683    }
684    DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", regs.itr(), regs.itr.interval());
685
686    if (regs.icr() & regs.imr) {
687        if (regs.itr.interval() == 0)  {
688            cpuPostInt();
689        } else {
690            DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n");
691            if (!interEvent.scheduled()) {
692               DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns
693                       * 256 * regs.itr.interval());
694               schedule(interEvent,
695                   curTick + Clock::Int::ns * 256 * regs.itr.interval());
696            }
697        }
698    }
699
700
701}
702
703
704IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s)
705    : DescCache<RxDesc>(i, n, s), pktDone(false), pktEvent(this)
706
707{
708}
709
710void
711IGbE::RxDescCache::writePacket(EthPacketPtr packet)
712{
713    // We shouldn't have to deal with any of these yet
714    DPRINTF(EthernetDesc, "Packet Length: %d Desc Size: %d\n",
715            packet->length, igbe->regs.rctl.descSize());
716    assert(packet->length < igbe->regs.rctl.descSize());
717
718    assert(unusedCache.size());
719    //if (!unusedCache.size())
720    //    return false;
721
722    pktPtr = packet;
723    pktDone = false;
724    igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
725            packet->length, &pktEvent, packet->data, igbe->rxWriteDelay);
726}
727
728void
729IGbE::RxDescCache::pktComplete()
730{
731    assert(unusedCache.size());
732    RxDesc *desc;
733    desc = unusedCache.front();
734
735    uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
736    desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
737    DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
738            pktPtr->length, crcfixup,
739            htole((uint16_t)(pktPtr->length + crcfixup)),
740            (uint16_t)(pktPtr->length + crcfixup));
741
742    // no support for anything but starting at 0
743    assert(igbe->regs.rxcsum.pcss() == 0);
744
745    DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n");
746
747    uint8_t status = RXDS_DD | RXDS_EOP;
748    uint8_t err = 0;
749
750    IpPtr ip(pktPtr);
751
752    if (ip) {
753        DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id());
754
755        if (igbe->regs.rxcsum.ipofld()) {
756            DPRINTF(EthernetDesc, "Checking IP checksum\n");
757            status |= RXDS_IPCS;
758            desc->csum = htole(cksum(ip));
759            igbe->rxIpChecksums++;
760            if (cksum(ip) != 0) {
761                err |= RXDE_IPE;
762                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
763            }
764        }
765        TcpPtr tcp(ip);
766        if (tcp && igbe->regs.rxcsum.tuofld()) {
767            DPRINTF(EthernetDesc, "Checking TCP checksum\n");
768            status |= RXDS_TCPCS;
769            desc->csum = htole(cksum(tcp));
770            igbe->rxTcpChecksums++;
771            if (cksum(tcp) != 0) {
772                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
773                err |= RXDE_TCPE;
774            }
775        }
776
777        UdpPtr udp(ip);
778        if (udp && igbe->regs.rxcsum.tuofld()) {
779            DPRINTF(EthernetDesc, "Checking UDP checksum\n");
780            status |= RXDS_UDPCS;
781            desc->csum = htole(cksum(udp));
782            igbe->rxUdpChecksums++;
783            if (cksum(udp) != 0) {
784                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
785                err |= RXDE_TCPE;
786            }
787        }
788    } else { // if ip
789        DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
790    }
791
792
793    desc->status = htole(status);
794    desc->errors = htole(err);
795
796    // No vlan support at this point... just set it to 0
797    desc->vlan = 0;
798
799    // Deal with the rx timer interrupts
800    if (igbe->regs.rdtr.delay()) {
801        DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
802                igbe->regs.rdtr.delay() * igbe->intClock());
803        igbe->reschedule(igbe->rdtrEvent,
804            curTick + igbe->regs.rdtr.delay() * igbe->intClock(), true);
805    }
806
807    if (igbe->regs.radv.idv()) {
808        DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
809                igbe->regs.radv.idv() * igbe->intClock());
810        if (!igbe->radvEvent.scheduled()) {
811            igbe->schedule(igbe->radvEvent,
812                curTick + igbe->regs.radv.idv() * igbe->intClock());
813        }
814    }
815
816    // if neither radv or rdtr, maybe itr is set...
817    if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) {
818        DPRINTF(EthernetSM, "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
819        igbe->postInterrupt(IT_RXT);
820    }
821
822    // If the packet is small enough, interrupt appropriately
823    // I wonder if this is delayed or not?!
824    if (pktPtr->length <= igbe->regs.rsrpd.idv()) {
825        DPRINTF(EthernetSM, "RXS: Posting IT_SRPD beacuse small packet received\n");
826        igbe->postInterrupt(IT_SRPD);
827    }
828
829    DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
830    unusedCache.pop_front();
831    usedCache.push_back(desc);
832
833
834    pktPtr = NULL;
835    enableSm();
836    pktDone = true;
837    igbe->checkDrain();
838
839}
840
841void
842IGbE::RxDescCache::enableSm()
843{
844    if (!igbe->drainEvent) {
845        igbe->rxTick = true;
846        igbe->restartClock();
847    }
848}
849
850bool
851IGbE::RxDescCache::packetDone()
852{
853    if (pktDone) {
854        pktDone = false;
855        return true;
856    }
857    return false;
858}
859
860bool
861IGbE::RxDescCache::hasOutstandingEvents()
862{
863    return pktEvent.scheduled() || wbEvent.scheduled() ||
864        fetchEvent.scheduled();
865}
866
867void
868IGbE::RxDescCache::serialize(std::ostream &os)
869{
870    DescCache<RxDesc>::serialize(os);
871    SERIALIZE_SCALAR(pktDone);
872}
873
874void
875IGbE::RxDescCache::unserialize(Checkpoint *cp, const std::string &section)
876{
877    DescCache<RxDesc>::unserialize(cp, section);
878    UNSERIALIZE_SCALAR(pktDone);
879}
880
881
882///////////////////////////////////// IGbE::TxDesc /////////////////////////////////
883
884IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s)
885    : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), pktWaiting(false),
886       useTso(false), pktEvent(this), headerEvent(this)
887
888{
889}
890
891void
892IGbE::TxDescCache::processContextDesc()
893{
894    assert(unusedCache.size());
895    TxDesc *desc;
896
897    DPRINTF(EthernetDesc, "Checking and  processing context descriptors\n");
898
899    while (!useTso && unusedCache.size() && TxdOp::isContext(unusedCache.front())) {
900        DPRINTF(EthernetDesc, "Got context descriptor type...\n");
901
902        desc = unusedCache.front();
903        DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n",
904                    desc->d1, desc->d2);
905
906
907        // is this going to be a tcp or udp packet?
908        isTcp = TxdOp::tcp(desc) ? true : false;
909
910        if (TxdOp::tse(desc)) {
911            DPRINTF(EthernetDesc, "TCP offload enabled for packet hdrlen: %d mss: %d paylen %d\n",
912                    TxdOp::hdrlen(desc), TxdOp::mss(desc), TxdOp::getLen(desc));
913            // setup all the TSO variables
914            useTso = true;
915            tsoHeaderLen = TxdOp::hdrlen(desc);
916            tsoMss  = TxdOp::mss(desc);
917            tsoTotalLen = TxdOp::getLen(desc);
918            tsoLoadedHeader = false;
919            tsoDescBytesUsed = 0;
920            tsoUsedLen = 0;
921            tsoPrevSeq = 0;
922            tsoPktHasHeader = false;
923            tsoPkts = 0;
924        }
925
926        TxdOp::setDd(desc);
927        unusedCache.pop_front();
928        usedCache.push_back(desc);
929    }
930
931    if (!unusedCache.size())
932        return;
933
934    if (useTso && !tsoLoadedHeader) {
935        // we need to fetch a header
936        DPRINTF(EthernetDesc, "Starting DMA of TSO header\n");
937        desc = unusedCache.front();
938        assert(TxdOp::isData(desc) && TxdOp::getLen(desc) >= tsoHeaderLen);
939        pktWaiting = true;
940        assert(tsoHeaderLen <= 256);
941        igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
942                tsoHeaderLen, &headerEvent, tsoHeader, 0);
943    }
944}
945
946void
947IGbE::TxDescCache::headerComplete()
948{
949    DPRINTF(EthernetDesc, "TSO: Fetching TSO header complete\n");
950    pktWaiting = false;
951
952    assert(unusedCache.size());
953    TxDesc *desc = unusedCache.front();
954    DPRINTF(EthernetDesc, "TSO: len: %d tsoHeaderLen: %d\n",
955            TxdOp::getLen(desc), tsoHeaderLen);
956
957    if (TxdOp::getLen(desc) == tsoHeaderLen) {
958        tsoDescBytesUsed = 0;
959        tsoLoadedHeader = true;
960        unusedCache.pop_front();
961        usedCache.push_back(desc);
962    } else {
963        // I don't think this case happens, I think the headrer is always
964        // it's own packet, if it wasn't it might be as simple as just
965        // incrementing descBytesUsed by the header length, but I'm not
966        // completely sure
967        panic("TSO header part of bigger packet, not implemented\n");
968    }
969    enableSm();
970    igbe->checkDrain();
971}
972
973int
974IGbE::TxDescCache::getPacketSize(EthPacketPtr p)
975{
976    TxDesc *desc;
977
978
979    if (!unusedCache.size())
980        return -1;
981
982    DPRINTF(EthernetDesc, "Starting processing of descriptor\n");
983
984    assert(!useTso || tsoLoadedHeader);
985    desc = unusedCache.front();
986
987
988    if (useTso) {
989        DPRINTF(EthernetDesc, "getPacket(): TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
990        DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d used: %d loaded hdr: %d\n",
991                useTso, tsoHeaderLen, tsoMss, tsoTotalLen, tsoUsedLen, tsoLoadedHeader);
992        DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d this descLen: %d\n",
993                tsoDescBytesUsed, tsoCopyBytes, TxdOp::getLen(desc));
994        DPRINTF(EthernetDesc, "TSO: pktHasHeader: %d\n", tsoPktHasHeader);
995
996        if (tsoPktHasHeader)
997            tsoCopyBytes =  std::min((tsoMss + tsoHeaderLen) - p->length, TxdOp::getLen(desc) - tsoDescBytesUsed);
998        else
999            tsoCopyBytes =  std::min(tsoMss, TxdOp::getLen(desc) - tsoDescBytesUsed);
1000        Addr pkt_size = tsoCopyBytes + (tsoPktHasHeader ? 0 : tsoHeaderLen);
1001        DPRINTF(EthernetDesc, "TSO: Next packet is %d bytes\n", pkt_size);
1002        return pkt_size;
1003    }
1004
1005    DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n",
1006                TxdOp::getLen(unusedCache.front()));
1007    return TxdOp::getLen(desc);
1008}
1009
1010void
1011IGbE::TxDescCache::getPacketData(EthPacketPtr p)
1012{
1013    assert(unusedCache.size());
1014
1015    TxDesc *desc;
1016    desc = unusedCache.front();
1017
1018    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
1019
1020    pktPtr = p;
1021
1022    pktWaiting = true;
1023
1024    DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length);
1025
1026    if (useTso) {
1027        assert(tsoLoadedHeader);
1028        if (!tsoPktHasHeader) {
1029            DPRINTF(EthernetDesc, "Loading TSO header (%d bytes) into start of packet\n",
1030                   tsoHeaderLen);
1031            memcpy(p->data, &tsoHeader,tsoHeaderLen);
1032            p->length +=tsoHeaderLen;
1033            tsoPktHasHeader = true;
1034        }
1035    }
1036
1037    if (useTso) {
1038        tsoDescBytesUsed += tsoCopyBytes;
1039        assert(tsoDescBytesUsed <= TxdOp::getLen(desc));
1040        DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d length: %d\n",
1041                p->length, tsoCopyBytes);
1042        igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)) + tsoDescBytesUsed,
1043            tsoCopyBytes, &pktEvent, p->data + p->length, igbe->txReadDelay);
1044    } else {
1045        igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
1046            TxdOp::getLen(desc), &pktEvent, p->data + p->length, igbe->txReadDelay);
1047    }
1048}
1049
1050void
1051IGbE::TxDescCache::pktComplete()
1052{
1053
1054    TxDesc *desc;
1055    assert(unusedCache.size());
1056    assert(pktPtr);
1057
1058    DPRINTF(EthernetDesc, "DMA of packet complete\n");
1059
1060
1061    desc = unusedCache.front();
1062    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
1063
1064    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
1065    DPRINTF(EthernetDesc, "TSO: use: %d hdrlen: %d mss: %d total: %d used: %d loaded hdr: %d\n",
1066            useTso, tsoHeaderLen, tsoMss, tsoTotalLen, tsoUsedLen, tsoLoadedHeader);
1067
1068    // Set the length of the data in the EtherPacket
1069    if (useTso) {
1070        pktPtr->length += tsoCopyBytes;
1071        tsoUsedLen += tsoCopyBytes;
1072    } else
1073        pktPtr->length += TxdOp::getLen(desc);
1074
1075    DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d\n",
1076            tsoDescBytesUsed, tsoCopyBytes);
1077
1078
1079    if ((!TxdOp::eop(desc) && !useTso) ||
1080            (pktPtr->length < ( tsoMss + tsoHeaderLen) && tsoTotalLen != tsoUsedLen)) {
1081        assert(!useTso || (tsoDescBytesUsed == TxdOp::getLen(desc)));
1082        unusedCache.pop_front();
1083        usedCache.push_back(desc);
1084
1085        tsoDescBytesUsed = 0;
1086        pktDone = true;
1087        pktWaiting = false;
1088        pktMultiDesc = true;
1089
1090        DPRINTF(EthernetDesc, "Partial Packet Descriptor of %d bytes Done\n",
1091                pktPtr->length);
1092        pktPtr = NULL;
1093
1094        enableSm();
1095        igbe->checkDrain();
1096        return;
1097    }
1098
1099
1100    pktMultiDesc = false;
1101    // no support for vlans
1102    assert(!TxdOp::vle(desc));
1103
1104    // we only support single packet descriptors at this point
1105    if (!useTso)
1106        assert(TxdOp::eop(desc));
1107
1108    // set that this packet is done
1109    if (TxdOp::rs(desc))
1110        TxdOp::setDd(desc);
1111
1112    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
1113
1114    if (useTso) {
1115        IpPtr ip(pktPtr);
1116        if (ip) {
1117            DPRINTF(EthernetDesc, "TSO: Modifying IP header. Id + %d\n",
1118                    tsoPkts);
1119            ip->id(ip->id() + tsoPkts++);
1120            ip->len(pktPtr->length - EthPtr(pktPtr)->size());
1121
1122            TcpPtr tcp(ip);
1123            if (tcp) {
1124                DPRINTF(EthernetDesc, "TSO: Modifying TCP header. old seq %d + %d\n",
1125                    tcp->seq(), tsoPrevSeq);
1126                tcp->seq(tcp->seq() + tsoPrevSeq);
1127                if (tsoUsedLen != tsoTotalLen)
1128                    tcp->flags(tcp->flags() & ~9); // clear fin & psh
1129            }
1130            UdpPtr udp(ip);
1131            if (udp) {
1132                DPRINTF(EthernetDesc, "TSO: Modifying UDP header.\n");
1133                udp->len(pktPtr->length - EthPtr(pktPtr)->size());
1134            }
1135        }
1136        tsoPrevSeq = tsoUsedLen;
1137    }
1138
1139    if (DTRACE(EthernetDesc)) {
1140        IpPtr ip(pktPtr);
1141        if (ip)
1142            DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n",
1143                    ip->id());
1144        else
1145            DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
1146    }
1147
1148    // Checksums are only ofloaded for new descriptor types
1149    if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
1150        DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
1151        IpPtr ip(pktPtr);
1152        assert(ip);
1153        if (TxdOp::ixsm(desc)) {
1154            ip->sum(0);
1155            ip->sum(cksum(ip));
1156            igbe->txIpChecksums++;
1157            DPRINTF(EthernetDesc, "Calculated IP checksum\n");
1158        }
1159        if (TxdOp::txsm(desc)) {
1160            TcpPtr tcp(ip);
1161            UdpPtr udp(ip);
1162            if (tcp) {
1163                 tcp->sum(0);
1164                 tcp->sum(cksum(tcp));
1165                 igbe->txTcpChecksums++;
1166                 DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
1167            } else if (udp) {
1168                 assert(udp);
1169                 udp->sum(0);
1170                 udp->sum(cksum(udp));
1171                 igbe->txUdpChecksums++;
1172                 DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
1173            } else {
1174                panic("Told to checksum, but don't know how\n");
1175            }
1176        }
1177    }
1178
1179    if (TxdOp::ide(desc)) {
1180        // Deal with the rx timer interrupts
1181        DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
1182        if (igbe->regs.tidv.idv()) {
1183            DPRINTF(EthernetDesc, "setting tidv\n");
1184            igbe->reschedule(igbe->tidvEvent,
1185                curTick + igbe->regs.tidv.idv() * igbe->intClock(), true);
1186        }
1187
1188        if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
1189            DPRINTF(EthernetDesc, "setting tadv\n");
1190            if (!igbe->tadvEvent.scheduled()) {
1191                igbe->schedule(igbe->tadvEvent,
1192                    curTick + igbe->regs.tadv.idv() * igbe->intClock());
1193            }
1194        }
1195    }
1196
1197
1198    if (!useTso ||  TxdOp::getLen(desc) == tsoDescBytesUsed) {
1199        DPRINTF(EthernetDesc, "Descriptor Done\n");
1200        unusedCache.pop_front();
1201        usedCache.push_back(desc);
1202        tsoDescBytesUsed = 0;
1203    }
1204
1205    if (useTso && tsoUsedLen == tsoTotalLen)
1206        useTso = false;
1207
1208
1209    DPRINTF(EthernetDesc, "------Packet of %d bytes ready for transmission-------\n",
1210            pktPtr->length);
1211    pktDone = true;
1212    pktWaiting = false;
1213    pktPtr = NULL;
1214    tsoPktHasHeader = false;
1215
1216    if (igbe->regs.txdctl.wthresh() == 0) {
1217        DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n");
1218        writeback(0);
1219    } else if (igbe->regs.txdctl.wthresh() >= usedCache.size()) {
1220        DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
1221        writeback((igbe->cacheBlockSize()-1)>>4);
1222    }
1223    enableSm();
1224    igbe->checkDrain();
1225}
1226
1227void
1228IGbE::TxDescCache::serialize(std::ostream &os)
1229{
1230    DescCache<TxDesc>::serialize(os);
1231    SERIALIZE_SCALAR(pktDone);
1232    SERIALIZE_SCALAR(isTcp);
1233    SERIALIZE_SCALAR(pktWaiting);
1234    SERIALIZE_SCALAR(pktMultiDesc);
1235
1236    SERIALIZE_SCALAR(useTso);
1237    SERIALIZE_SCALAR(tsoHeaderLen);
1238    SERIALIZE_SCALAR(tsoMss);
1239    SERIALIZE_SCALAR(tsoTotalLen);
1240    SERIALIZE_SCALAR(tsoUsedLen);
1241    SERIALIZE_SCALAR(tsoPrevSeq);;
1242    SERIALIZE_SCALAR(tsoPktPayloadBytes);
1243    SERIALIZE_SCALAR(tsoLoadedHeader);
1244    SERIALIZE_SCALAR(tsoPktHasHeader);
1245    SERIALIZE_ARRAY(tsoHeader, 256);
1246    SERIALIZE_SCALAR(tsoDescBytesUsed);
1247    SERIALIZE_SCALAR(tsoCopyBytes);
1248    SERIALIZE_SCALAR(tsoPkts);
1249
1250
1251}
1252
1253void
1254IGbE::TxDescCache::unserialize(Checkpoint *cp, const std::string &section)
1255{
1256    DescCache<TxDesc>::unserialize(cp, section);
1257    UNSERIALIZE_SCALAR(pktDone);
1258    UNSERIALIZE_SCALAR(isTcp);
1259    UNSERIALIZE_SCALAR(pktWaiting);
1260    UNSERIALIZE_SCALAR(pktMultiDesc);
1261
1262    UNSERIALIZE_SCALAR(useTso);
1263    UNSERIALIZE_SCALAR(tsoHeaderLen);
1264    UNSERIALIZE_SCALAR(tsoMss);
1265    UNSERIALIZE_SCALAR(tsoTotalLen);
1266    UNSERIALIZE_SCALAR(tsoUsedLen);
1267    UNSERIALIZE_SCALAR(tsoPrevSeq);;
1268    UNSERIALIZE_SCALAR(tsoPktPayloadBytes);
1269    UNSERIALIZE_SCALAR(tsoLoadedHeader);
1270    UNSERIALIZE_SCALAR(tsoPktHasHeader);
1271    UNSERIALIZE_ARRAY(tsoHeader, 256);
1272    UNSERIALIZE_SCALAR(tsoDescBytesUsed);
1273    UNSERIALIZE_SCALAR(tsoCopyBytes);
1274    UNSERIALIZE_SCALAR(tsoPkts);
1275}
1276
1277bool
1278IGbE::TxDescCache::packetAvailable()
1279{
1280    if (pktDone) {
1281        pktDone = false;
1282        return true;
1283    }
1284    return false;
1285}
1286
1287void
1288IGbE::TxDescCache::enableSm()
1289{
1290    if (!igbe->drainEvent) {
1291        igbe->txTick = true;
1292        igbe->restartClock();
1293    }
1294}
1295
1296bool
1297IGbE::TxDescCache::hasOutstandingEvents()
1298{
1299    return pktEvent.scheduled() || wbEvent.scheduled() ||
1300        fetchEvent.scheduled();
1301}
1302
1303
1304///////////////////////////////////// IGbE /////////////////////////////////
1305
1306void
1307IGbE::restartClock()
1308{
1309    if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
1310        getState() == SimObject::Running)
1311        schedule(tickEvent, (curTick / ticks(1)) * ticks(1) + ticks(1));
1312}
1313
1314unsigned int
1315IGbE::drain(Event *de)
1316{
1317    unsigned int count;
1318    count = pioPort->drain(de) + dmaPort->drain(de);
1319    if (rxDescCache.hasOutstandingEvents() ||
1320            txDescCache.hasOutstandingEvents()) {
1321        count++;
1322        drainEvent = de;
1323    }
1324
1325    txFifoTick = false;
1326    txTick = false;
1327    rxTick = false;
1328
1329    if (tickEvent.scheduled())
1330        deschedule(tickEvent);
1331
1332    if (count)
1333        changeState(Draining);
1334    else
1335        changeState(Drained);
1336
1337    return count;
1338}
1339
1340void
1341IGbE::resume()
1342{
1343    SimObject::resume();
1344
1345    txFifoTick = true;
1346    txTick = true;
1347    rxTick = true;
1348
1349    restartClock();
1350}
1351
1352void
1353IGbE::checkDrain()
1354{
1355    if (!drainEvent)
1356        return;
1357
1358    txFifoTick = false;
1359    txTick = false;
1360    rxTick = false;
1361    if (!rxDescCache.hasOutstandingEvents() &&
1362            !txDescCache.hasOutstandingEvents()) {
1363        drainEvent->process();
1364        drainEvent = NULL;
1365    }
1366}
1367
1368void
1369IGbE::txStateMachine()
1370{
1371    if (!regs.tctl.en()) {
1372        txTick = false;
1373        DPRINTF(EthernetSM, "TXS: TX disabled, stopping ticking\n");
1374        return;
1375    }
1376
1377    // If we have a packet available and it's length is not 0 (meaning it's not
1378    // a multidescriptor packet) put it in the fifo, otherwise an the next
1379    // iteration we'll get the rest of the data
1380    if (txPacket && txDescCache.packetAvailable()
1381                 && !txDescCache.packetMultiDesc() && txPacket->length) {
1382        bool success;
1383
1384        DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
1385        success = txFifo.push(txPacket);
1386        txFifoTick = true && !drainEvent;
1387        assert(success);
1388        txPacket = NULL;
1389        txDescCache.writeback((cacheBlockSize()-1)>>4);
1390        return;
1391    }
1392
1393    // Only support descriptor granularity
1394    assert(regs.txdctl.gran());
1395    if (regs.txdctl.lwthresh() && txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) {
1396        DPRINTF(EthernetSM, "TXS: LWTHRESH caused posting of TXDLOW\n");
1397        postInterrupt(IT_TXDLOW);
1398    }
1399
1400    if (!txPacket) {
1401        txPacket = new EthPacketData(16384);
1402    }
1403
1404    if (!txDescCache.packetWaiting()) {
1405        if (txDescCache.descLeft() == 0) {
1406            postInterrupt(IT_TXQE);
1407            txDescCache.writeback(0);
1408            txDescCache.fetchDescriptors();
1409            DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
1410                    "writeback stopping ticking and posting TXQE\n");
1411            txTick = false;
1412            return;
1413        }
1414
1415
1416        if (!(txDescCache.descUnused())) {
1417            txDescCache.fetchDescriptors();
1418            DPRINTF(EthernetSM, "TXS: No descriptors available in cache, fetching and stopping ticking\n");
1419            txTick = false;
1420            return;
1421        }
1422
1423
1424        txDescCache.processContextDesc();
1425        if (txDescCache.packetWaiting()) {
1426            DPRINTF(EthernetSM, "TXS: Fetching TSO header, stopping ticking\n");
1427            txTick = false;
1428            return;
1429        }
1430
1431        int size;
1432        size = txDescCache.getPacketSize(txPacket);
1433        if (size > 0 && txFifo.avail() > size) {
1434            DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and begining "
1435                    "DMA of next packet\n", size);
1436            txFifo.reserve(size);
1437            txDescCache.getPacketData(txPacket);
1438        } else if (size <= 0) {
1439            DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size);
1440            DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
1441            txDescCache.writeback(0);
1442        } else {
1443            DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
1444                    "available in FIFO\n");
1445            txTick = false;
1446        }
1447
1448
1449        return;
1450    }
1451    DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n");
1452    txTick = false;
1453}
1454
1455bool
1456IGbE::ethRxPkt(EthPacketPtr pkt)
1457{
1458    rxBytes += pkt->length;
1459    rxPackets++;
1460
1461    DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
1462
1463    if (!regs.rctl.en()) {
1464        DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
1465        return true;
1466    }
1467
1468    // restart the state machines if they are stopped
1469    rxTick = true && !drainEvent;
1470    if ((rxTick || txTick) && !tickEvent.scheduled()) {
1471        DPRINTF(EthernetSM, "RXS: received packet into fifo, starting ticking\n");
1472        restartClock();
1473    }
1474
1475    if (!rxFifo.push(pkt)) {
1476        DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n");
1477        postInterrupt(IT_RXO, true);
1478        return false;
1479    }
1480
1481    return true;
1482}
1483
1484
1485void
1486IGbE::rxStateMachine()
1487{
1488    if (!regs.rctl.en()) {
1489        rxTick = false;
1490        DPRINTF(EthernetSM, "RXS: RX disabled, stopping ticking\n");
1491        return;
1492    }
1493
1494    // If the packet is done check for interrupts/descriptors/etc
1495    if (rxDescCache.packetDone()) {
1496        rxDmaPacket = false;
1497        DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n");
1498        int descLeft = rxDescCache.descLeft();
1499        switch (regs.rctl.rdmts()) {
1500            case 2: if (descLeft > .125 * regs.rdlen()) break;
1501            case 1: if (descLeft > .250 * regs.rdlen()) break;
1502            case 0: if (descLeft > .500 * regs.rdlen())  break;
1503                DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) because of descriptors left\n");
1504                postInterrupt(IT_RXDMT);
1505                break;
1506        }
1507
1508        if (descLeft == 0) {
1509            rxDescCache.writeback(0);
1510            DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
1511                    " writeback and stopping ticking\n");
1512            rxTick = false;
1513        }
1514
1515        // only support descriptor granulaties
1516        assert(regs.rxdctl.gran());
1517
1518        if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) {
1519            DPRINTF(EthernetSM, "RXS: Writing back because WTHRESH >= descUsed\n");
1520            if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4))
1521                rxDescCache.writeback(regs.rxdctl.wthresh()-1);
1522            else
1523                rxDescCache.writeback((cacheBlockSize()-1)>>4);
1524        }
1525
1526        if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) &&
1527             ((rxDescCache.descLeft() - rxDescCache.descUnused()) > regs.rxdctl.hthresh())) {
1528            DPRINTF(EthernetSM, "RXS: Fetching descriptors because descUnused < PTHRESH\n");
1529            rxDescCache.fetchDescriptors();
1530        }
1531
1532        if (rxDescCache.descUnused() == 0) {
1533            rxDescCache.fetchDescriptors();
1534            DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
1535                    "fetching descriptors and stopping ticking\n");
1536            rxTick = false;
1537        }
1538        return;
1539    }
1540
1541    if (rxDmaPacket) {
1542        DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
1543        rxTick = false;
1544        return;
1545    }
1546
1547    if (!rxDescCache.descUnused()) {
1548        rxDescCache.fetchDescriptors();
1549        DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n");
1550        rxTick = false;
1551        DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n");
1552        return;
1553    }
1554
1555    if (rxFifo.empty()) {
1556        DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n");
1557        rxTick = false;
1558        return;
1559    }
1560
1561    EthPacketPtr pkt;
1562    pkt = rxFifo.front();
1563
1564
1565    rxDescCache.writePacket(pkt);
1566    DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
1567    DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
1568    rxFifo.pop();
1569    DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
1570    rxTick = false;
1571    rxDmaPacket = true;
1572}
1573
1574void
1575IGbE::txWire()
1576{
1577    if (txFifo.empty()) {
1578        txFifoTick = false;
1579        return;
1580    }
1581
1582
1583    if (etherInt->sendPacket(txFifo.front())) {
1584        if (DTRACE(EthernetSM)) {
1585            IpPtr ip(txFifo.front());
1586            if (ip)
1587                DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n",
1588                        ip->id());
1589            else
1590                DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
1591        }
1592        DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
1593                txFifo.avail());
1594
1595        txBytes += txFifo.front()->length;
1596        txPackets++;
1597        txFifoTick = false;
1598
1599        txFifo.pop();
1600    } else {
1601        // We'll get woken up when the packet ethTxDone() gets called
1602        txFifoTick = false;
1603    }
1604}
1605
1606void
1607IGbE::tick()
1608{
1609    DPRINTF(EthernetSM, "IGbE: -------------- Cycle --------------\n");
1610
1611    if (rxTick)
1612        rxStateMachine();
1613
1614    if (txTick)
1615        txStateMachine();
1616
1617    if (txFifoTick)
1618        txWire();
1619
1620
1621    if (rxTick || txTick || txFifoTick)
1622        schedule(tickEvent, curTick + ticks(1));
1623}
1624
1625void
1626IGbE::ethTxDone()
1627{
1628    // restart the tx state machines if they are stopped
1629    // fifo to send another packet
1630    // tx sm to put more data into the fifo
1631    txFifoTick = true && !drainEvent;
1632    if (txDescCache.descLeft() != 0 && !drainEvent)
1633        txTick = true;
1634
1635    restartClock();
1636    txWire();
1637    DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
1638}
1639
1640void
1641IGbE::serialize(std::ostream &os)
1642{
1643    PciDev::serialize(os);
1644
1645    regs.serialize(os);
1646    SERIALIZE_SCALAR(eeOpBits);
1647    SERIALIZE_SCALAR(eeAddrBits);
1648    SERIALIZE_SCALAR(eeDataBits);
1649    SERIALIZE_SCALAR(eeOpcode);
1650    SERIALIZE_SCALAR(eeAddr);
1651    SERIALIZE_SCALAR(lastInterrupt);
1652    SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
1653
1654    rxFifo.serialize("rxfifo", os);
1655    txFifo.serialize("txfifo", os);
1656
1657    bool txPktExists = txPacket;
1658    SERIALIZE_SCALAR(txPktExists);
1659    if (txPktExists)
1660        txPacket->serialize("txpacket", os);
1661
1662    Tick rdtr_time = 0, radv_time = 0, tidv_time = 0, tadv_time = 0,
1663         inter_time = 0;
1664
1665    if (rdtrEvent.scheduled())
1666       rdtr_time = rdtrEvent.when();
1667    SERIALIZE_SCALAR(rdtr_time);
1668
1669    if (radvEvent.scheduled())
1670       radv_time = radvEvent.when();
1671    SERIALIZE_SCALAR(radv_time);
1672
1673    if (tidvEvent.scheduled())
1674       tidv_time = tidvEvent.when();
1675    SERIALIZE_SCALAR(tidv_time);
1676
1677    if (tadvEvent.scheduled())
1678       tadv_time = tadvEvent.when();
1679    SERIALIZE_SCALAR(tadv_time);
1680
1681    if (interEvent.scheduled())
1682       inter_time = interEvent.when();
1683    SERIALIZE_SCALAR(inter_time);
1684
1685    nameOut(os, csprintf("%s.TxDescCache", name()));
1686    txDescCache.serialize(os);
1687
1688    nameOut(os, csprintf("%s.RxDescCache", name()));
1689    rxDescCache.serialize(os);
1690}
1691
1692void
1693IGbE::unserialize(Checkpoint *cp, const std::string &section)
1694{
1695    PciDev::unserialize(cp, section);
1696
1697    regs.unserialize(cp, section);
1698    UNSERIALIZE_SCALAR(eeOpBits);
1699    UNSERIALIZE_SCALAR(eeAddrBits);
1700    UNSERIALIZE_SCALAR(eeDataBits);
1701    UNSERIALIZE_SCALAR(eeOpcode);
1702    UNSERIALIZE_SCALAR(eeAddr);
1703    UNSERIALIZE_SCALAR(lastInterrupt);
1704    UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
1705
1706    rxFifo.unserialize("rxfifo", cp, section);
1707    txFifo.unserialize("txfifo", cp, section);
1708
1709    bool txPktExists;
1710    UNSERIALIZE_SCALAR(txPktExists);
1711    if (txPktExists) {
1712        txPacket = new EthPacketData(16384);
1713        txPacket->unserialize("txpacket", cp, section);
1714    }
1715
1716    rxTick = true;
1717    txTick = true;
1718    txFifoTick = true;
1719
1720    Tick rdtr_time, radv_time, tidv_time, tadv_time, inter_time;
1721    UNSERIALIZE_SCALAR(rdtr_time);
1722    UNSERIALIZE_SCALAR(radv_time);
1723    UNSERIALIZE_SCALAR(tidv_time);
1724    UNSERIALIZE_SCALAR(tadv_time);
1725    UNSERIALIZE_SCALAR(inter_time);
1726
1727    if (rdtr_time)
1728        schedule(rdtrEvent, rdtr_time);
1729
1730    if (radv_time)
1731        schedule(radvEvent, radv_time);
1732
1733    if (tidv_time)
1734        schedule(tidvEvent, tidv_time);
1735
1736    if (tadv_time)
1737        schedule(tadvEvent, tadv_time);
1738
1739    if (inter_time)
1740        schedule(interEvent, inter_time);
1741
1742    txDescCache.unserialize(cp, csprintf("%s.TxDescCache", section));
1743
1744    rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
1745}
1746
1747IGbE *
1748IGbEParams::create()
1749{
1750    return new IGbE(this);
1751}
1752