i8254xGBe.cc revision 4291 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
34 * fewest workarounds in the driver. It will probably work with most of the
35 * other MACs with slight modifications.
36 */
37
38
39/*
40 * @todo really there are multiple dma engines.. we should implement them.
41 */
42
43#include "base/inet.hh"
44#include "base/trace.hh"
45#include "dev/i8254xGBe.hh"
46#include "mem/packet.hh"
47#include "mem/packet_access.hh"
48#include "sim/builder.hh"
49#include "sim/stats.hh"
50#include "sim/system.hh"
51
52#include <algorithm>
53
54using namespace iGbReg;
55using namespace Net;
56
57IGbE::IGbE(Params *p)
58    : PciDev(p), etherInt(NULL),  useFlowControl(p->use_flow_control),
59      rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
60      txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this),
61      tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
62      rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
63      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
64{
65    // Initialized internal registers per Intel documentation
66    // All registers intialized to 0 by per register constructor
67    regs.ctrl.fd(1);
68    regs.ctrl.lrst(1);
69    regs.ctrl.speed(2);
70    regs.ctrl.frcspd(1);
71    regs.sts.speed(3); // Say we're 1000Mbps
72    regs.sts.fd(1); // full duplex
73    regs.sts.lu(1); // link up
74    regs.eecd.fwe(1);
75    regs.eecd.ee_type(1);
76    regs.imr = 0;
77    regs.iam = 0;
78    regs.rxdctl.gran(1);
79    regs.rxdctl.wthresh(1);
80    regs.fcrth(1);
81
82    regs.pba.rxa(0x30);
83    regs.pba.txa(0x10);
84
85    eeOpBits            = 0;
86    eeAddrBits          = 0;
87    eeDataBits          = 0;
88    eeOpcode            = 0;
89
90    // clear all 64 16 bit words of the eeprom
91    memset(&flash, 0, EEPROM_SIZE*2);
92
93    // Set the MAC address
94    memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN);
95    for (int x = 0; x < ETH_ADDR_LEN/2; x++)
96        flash[x] = htobe(flash[x]);
97
98    uint16_t csum = 0;
99    for (int x = 0; x < EEPROM_SIZE; x++)
100        csum += htobe(flash[x]);
101
102
103    // Magic happy checksum value
104    flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum));
105
106    rxFifo.clear();
107    txFifo.clear();
108}
109
110
111Tick
112IGbE::writeConfig(PacketPtr pkt)
113{
114    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
115    if (offset < PCI_DEVICE_SPECIFIC)
116        PciDev::writeConfig(pkt);
117    else
118        panic("Device specific PCI config space not implemented.\n");
119
120    ///
121    /// Some work may need to be done here based for the pci COMMAND bits.
122    ///
123
124    return pioDelay;
125}
126
127Tick
128IGbE::read(PacketPtr pkt)
129{
130    int bar;
131    Addr daddr;
132
133    if (!getBAR(pkt->getAddr(), bar, daddr))
134        panic("Invalid PCI memory access to unmapped memory.\n");
135
136    // Only Memory register BAR is allowed
137    assert(bar == 0);
138
139    // Only 32bit accesses allowed
140    assert(pkt->getSize() == 4);
141
142    DPRINTF(Ethernet, "Read device register %#X\n", daddr);
143
144    pkt->allocate();
145
146    ///
147    /// Handle read of register here
148    ///
149
150
151    switch (daddr) {
152      case REG_CTRL:
153        pkt->set<uint32_t>(regs.ctrl());
154        break;
155      case REG_STATUS:
156        pkt->set<uint32_t>(regs.sts());
157        break;
158      case REG_EECD:
159        pkt->set<uint32_t>(regs.eecd());
160        break;
161      case REG_EERD:
162        pkt->set<uint32_t>(regs.eerd());
163        break;
164      case REG_CTRL_EXT:
165        pkt->set<uint32_t>(regs.ctrl_ext());
166        break;
167      case REG_MDIC:
168        pkt->set<uint32_t>(regs.mdic());
169        break;
170      case REG_ICR:
171        DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(),
172                regs.imr, regs.iam, regs.ctrl_ext.iame());
173        pkt->set<uint32_t>(regs.icr());
174        if (regs.icr.int_assert() || regs.imr == 0) {
175            regs.icr = regs.icr() & ~mask(30);
176            DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
177        }
178        if (regs.ctrl_ext.iame() && regs.icr.int_assert())
179            regs.imr &= ~regs.iam;
180        chkInterrupt();
181        break;
182      case REG_ITR:
183        pkt->set<uint32_t>(regs.itr());
184        break;
185      case REG_RCTL:
186        pkt->set<uint32_t>(regs.rctl());
187        break;
188      case REG_FCTTV:
189        pkt->set<uint32_t>(regs.fcttv());
190        break;
191      case REG_TCTL:
192        pkt->set<uint32_t>(regs.tctl());
193        break;
194      case REG_PBA:
195        pkt->set<uint32_t>(regs.pba());
196        break;
197      case REG_WUC:
198      case REG_LEDCTL:
199        pkt->set<uint32_t>(0); // We don't care, so just return 0
200        break;
201      case REG_FCRTL:
202        pkt->set<uint32_t>(regs.fcrtl());
203        break;
204      case REG_FCRTH:
205        pkt->set<uint32_t>(regs.fcrth());
206        break;
207      case REG_RDBAL:
208        pkt->set<uint32_t>(regs.rdba.rdbal());
209        break;
210      case REG_RDBAH:
211        pkt->set<uint32_t>(regs.rdba.rdbah());
212        break;
213      case REG_RDLEN:
214        pkt->set<uint32_t>(regs.rdlen());
215        break;
216      case REG_RDH:
217        pkt->set<uint32_t>(regs.rdh());
218        break;
219      case REG_RDT:
220        pkt->set<uint32_t>(regs.rdt());
221        break;
222      case REG_RDTR:
223        pkt->set<uint32_t>(regs.rdtr());
224        if (regs.rdtr.fpd()) {
225            rxDescCache.writeback(0);
226            DPRINTF(EthernetIntr, "Posting interrupt because of RDTR.FPD write\n");
227            postInterrupt(IT_RXT);
228            regs.rdtr.fpd(0);
229        }
230        break;
231      case REG_RADV:
232        pkt->set<uint32_t>(regs.radv());
233        break;
234      case REG_TDBAL:
235        pkt->set<uint32_t>(regs.tdba.tdbal());
236        break;
237      case REG_TDBAH:
238        pkt->set<uint32_t>(regs.tdba.tdbah());
239        break;
240      case REG_TDLEN:
241        pkt->set<uint32_t>(regs.tdlen());
242        break;
243      case REG_TDH:
244        pkt->set<uint32_t>(regs.tdh());
245        break;
246      case REG_TDT:
247        pkt->set<uint32_t>(regs.tdt());
248        break;
249      case REG_TIDV:
250        pkt->set<uint32_t>(regs.tidv());
251        break;
252      case REG_TXDCTL:
253        pkt->set<uint32_t>(regs.txdctl());
254        break;
255      case REG_TADV:
256        pkt->set<uint32_t>(regs.tadv());
257        break;
258      case REG_RXCSUM:
259        pkt->set<uint32_t>(regs.rxcsum());
260        break;
261      case REG_MANC:
262        pkt->set<uint32_t>(regs.manc());
263        break;
264      default:
265        if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) &&
266            !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) &&
267            !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)) &&
268            !(daddr >= REG_CRCERRS && daddr < (REG_CRCERRS + STATS_REGS_SIZE)))
269            panic("Read request to unknown register number: %#x\n", daddr);
270        else
271            pkt->set<uint32_t>(0);
272    };
273
274    pkt->result = Packet::Success;
275    return pioDelay;
276}
277
278Tick
279IGbE::write(PacketPtr pkt)
280{
281    int bar;
282    Addr daddr;
283
284
285    if (!getBAR(pkt->getAddr(), bar, daddr))
286        panic("Invalid PCI memory access to unmapped memory.\n");
287
288    // Only Memory register BAR is allowed
289    assert(bar == 0);
290
291    // Only 32bit accesses allowed
292    assert(pkt->getSize() == sizeof(uint32_t));
293
294    DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>());
295
296    ///
297    /// Handle write of register here
298    ///
299    uint32_t val = pkt->get<uint32_t>();
300
301    Regs::RCTL oldrctl;
302    Regs::TCTL oldtctl;
303
304    switch (daddr) {
305      case REG_CTRL:
306        regs.ctrl = val;
307        if (regs.ctrl.tfce())
308            warn("TX Flow control enabled, should implement\n");
309        if (regs.ctrl.rfce())
310            warn("RX Flow control enabled, should implement\n");
311        break;
312      case REG_CTRL_EXT:
313        regs.ctrl_ext = val;
314        break;
315      case REG_STATUS:
316        regs.sts = val;
317        break;
318      case REG_EECD:
319        int oldClk;
320        oldClk = regs.eecd.sk();
321        regs.eecd = val;
322        // See if this is a eeprom access and emulate accordingly
323        if (!oldClk && regs.eecd.sk()) {
324            if (eeOpBits < 8) {
325                eeOpcode = eeOpcode << 1 | regs.eecd.din();
326                eeOpBits++;
327            } else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
328                eeAddr = eeAddr << 1 | regs.eecd.din();
329                eeAddrBits++;
330            } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
331                assert(eeAddr>>1 < EEPROM_SIZE);
332                DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n",
333                        flash[eeAddr>>1] >> eeDataBits & 0x1, flash[eeAddr>>1]);
334                regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1);
335                eeDataBits++;
336            } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) {
337                regs.eecd.dout(0);
338                eeDataBits++;
339            } else
340                panic("What's going on with eeprom interface? opcode:"
341                       " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
342                       (uint32_t)eeOpBits, (uint32_t)eeAddr,
343                       (uint32_t)eeAddrBits, (uint32_t)eeDataBits);
344
345            // Reset everything for the next command
346            if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) ||
347               (eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
348                eeOpBits = 0;
349                eeAddrBits = 0;
350                eeDataBits = 0;
351               eeOpcode = 0;
352                eeAddr = 0;
353            }
354
355           DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
356                    (uint32_t)eeOpcode, (uint32_t) eeOpBits,
357                    (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits);
358           if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
359                                   eeOpcode == EEPROM_RDSR_OPCODE_SPI ))
360                panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode,
361                        (uint32_t)eeOpBits);
362
363
364        }
365        // If driver requests eeprom access, immediately give it to it
366        regs.eecd.ee_gnt(regs.eecd.ee_req());
367        break;
368      case REG_EERD:
369        regs.eerd = val;
370        break;
371      case REG_MDIC:
372        regs.mdic = val;
373        if (regs.mdic.i())
374            panic("No support for interrupt on mdic complete\n");
375        if (regs.mdic.phyadd() != 1)
376            panic("No support for reading anything but phy\n");
377        DPRINTF(Ethernet, "%s phy address %x\n", regs.mdic.op() == 1 ? "Writing"
378                : "Reading", regs.mdic.regadd());
379        switch (regs.mdic.regadd()) {
380            case PHY_PSTATUS:
381                regs.mdic.data(0x796D); // link up
382                break;
383            case PHY_PID:
384                regs.mdic.data(0x02A8);
385                break;
386            case PHY_EPID:
387                regs.mdic.data(0x0380);
388                break;
389            case PHY_GSTATUS:
390                regs.mdic.data(0x7C00);
391                break;
392            case PHY_EPSTATUS:
393                regs.mdic.data(0x3000);
394                break;
395            case PHY_AGC:
396                regs.mdic.data(0x180); // some random length
397                break;
398            default:
399                regs.mdic.data(0);
400        }
401        regs.mdic.r(1);
402        break;
403      case REG_ICR:
404        DPRINTF(Ethernet, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs.icr(),
405                regs.imr, regs.iam, regs.ctrl_ext.iame());
406        if (regs.ctrl_ext.iame())
407            regs.imr &= ~regs.iam;
408        regs.icr = ~bits(val,30,0) & regs.icr();
409        chkInterrupt();
410        break;
411      case REG_ITR:
412        regs.itr = val;
413        break;
414      case REG_ICS:
415        DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n");
416        postInterrupt((IntTypes)val);
417        break;
418       case REG_IMS:
419        regs.imr |= val;
420        chkInterrupt();
421        break;
422      case REG_IMC:
423        regs.imr &= ~val;
424        chkInterrupt();
425        break;
426      case REG_IAM:
427        regs.iam = val;
428        break;
429      case REG_RCTL:
430        oldrctl = regs.rctl;
431        regs.rctl = val;
432        if (regs.rctl.rst()) {
433            rxDescCache.reset();
434            DPRINTF(EthernetSM, "RXS: Got RESET!\n");
435            rxFifo.clear();
436            regs.rctl.rst(0);
437        }
438        if (regs.rctl.en())
439            rxTick = true;
440        restartClock();
441        break;
442      case REG_FCTTV:
443        regs.fcttv = val;
444        break;
445      case REG_TCTL:
446        regs.tctl = val;
447        oldtctl = regs.tctl;
448        regs.tctl = val;
449        if (regs.tctl.en())
450           txTick = true;
451        restartClock();
452        if (regs.tctl.en() && !oldtctl.en()) {
453            txDescCache.reset();
454        }
455         break;
456      case REG_PBA:
457        regs.pba.rxa(val);
458        regs.pba.txa(64 - regs.pba.rxa());
459        break;
460      case REG_WUC:
461      case REG_LEDCTL:
462      case REG_FCAL:
463      case REG_FCAH:
464      case REG_FCT:
465      case REG_VET:
466      case REG_AIFS:
467      case REG_TIPG:
468        ; // We don't care, so don't store anything
469        break;
470      case REG_FCRTL:
471        regs.fcrtl = val;
472        break;
473      case REG_FCRTH:
474        regs.fcrth = val;
475        break;
476      case REG_RDBAL:
477        regs.rdba.rdbal( val & ~mask(4));
478        rxDescCache.areaChanged();
479        break;
480      case REG_RDBAH:
481        regs.rdba.rdbah(val);
482        rxDescCache.areaChanged();
483        break;
484      case REG_RDLEN:
485        regs.rdlen = val & ~mask(7);
486        rxDescCache.areaChanged();
487        break;
488      case REG_RDH:
489        regs.rdh = val;
490        rxDescCache.areaChanged();
491        break;
492      case REG_RDT:
493        regs.rdt = val;
494        rxTick = true;
495        restartClock();
496        break;
497      case REG_RDTR:
498        regs.rdtr = val;
499        break;
500      case REG_RADV:
501        regs.radv = val;
502        break;
503      case REG_TDBAL:
504        regs.tdba.tdbal( val & ~mask(4));
505        txDescCache.areaChanged();
506        break;
507      case REG_TDBAH:
508        regs.tdba.tdbah(val);
509        txDescCache.areaChanged();
510        break;
511      case REG_TDLEN:
512        regs.tdlen = val & ~mask(7);
513        txDescCache.areaChanged();
514        break;
515      case REG_TDH:
516        regs.tdh = val;
517        txDescCache.areaChanged();
518        break;
519      case REG_TDT:
520        regs.tdt = val;
521        txTick = true;
522        restartClock();
523        break;
524      case REG_TIDV:
525        regs.tidv = val;
526        break;
527      case REG_TXDCTL:
528        regs.txdctl = val;
529        break;
530      case REG_TADV:
531        regs.tadv = val;
532        break;
533      case REG_RXCSUM:
534        regs.rxcsum = val;
535        break;
536      case REG_MANC:
537        regs.manc = val;
538        break;
539      default:
540       if (!(daddr >= REG_VFTA && daddr < (REG_VFTA + VLAN_FILTER_TABLE_SIZE*4)) &&
541           !(daddr >= REG_RAL && daddr < (REG_RAL + RCV_ADDRESS_TABLE_SIZE*8)) &&
542           !(daddr >= REG_MTA && daddr < (REG_MTA + MULTICAST_TABLE_SIZE*4)))
543           panic("Write request to unknown register number: %#x\n", daddr);
544    };
545
546    pkt->result = Packet::Success;
547    return pioDelay;
548}
549
550void
551IGbE::postInterrupt(IntTypes t, bool now)
552{
553    assert(t);
554
555    // Interrupt is already pending
556    if (t & regs.icr())
557        return;
558
559    if (regs.icr() & regs.imr)
560    {
561        regs.icr = regs.icr() | t;
562        if (!interEvent.scheduled())
563            interEvent.schedule(curTick + Clock::Int::ns * 256 *
564                    regs.itr.interval());
565    } else {
566        regs.icr = regs.icr() | t;
567        if (regs.itr.interval() == 0 || now) {
568            if (interEvent.scheduled())
569                interEvent.deschedule();
570            cpuPostInt();
571        } else {
572           DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
573                    Clock::Int::ns * 256 * regs.itr.interval());
574           if (!interEvent.scheduled())
575               interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
576        }
577    }
578}
579
580void
581IGbE::cpuPostInt()
582{
583    if (rdtrEvent.scheduled()) {
584        regs.icr.rxt0(1);
585        rdtrEvent.deschedule();
586    }
587    if (radvEvent.scheduled()) {
588        regs.icr.rxt0(1);
589        radvEvent.deschedule();
590    }
591    if (tadvEvent.scheduled()) {
592        regs.icr.txdw(1);
593        tadvEvent.deschedule();
594    }
595    if (tidvEvent.scheduled()) {
596        regs.icr.txdw(1);
597        tidvEvent.deschedule();
598    }
599
600    regs.icr.int_assert(1);
601    DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
602            regs.icr());
603    intrPost();
604}
605
606void
607IGbE::cpuClearInt()
608{
609    if (regs.icr.int_assert()) {
610        regs.icr.int_assert(0);
611        DPRINTF(EthernetIntr, "EINT: Clearing interrupt to CPU now. Vector %#x\n",
612                regs.icr());
613        intrClear();
614    }
615}
616
617void
618IGbE::chkInterrupt()
619{
620    // Check if we need to clear the cpu interrupt
621    if (!(regs.icr() & regs.imr)) {
622        if (interEvent.scheduled())
623           interEvent.deschedule();
624        if (regs.icr.int_assert())
625            cpuClearInt();
626    }
627
628    if (regs.icr() & regs.imr) {
629        if (regs.itr.interval() == 0)  {
630            cpuPostInt();
631        } else {
632            if (!interEvent.scheduled())
633               interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
634        }
635    }
636
637
638}
639
640
641IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s)
642    : DescCache<RxDesc>(i, n, s), pktDone(false), pktEvent(this)
643
644{
645}
646
647bool
648IGbE::RxDescCache::writePacket(EthPacketPtr packet)
649{
650    // We shouldn't have to deal with any of these yet
651    DPRINTF(EthernetDesc, "Packet Length: %d Desc Size: %d\n",
652            packet->length, igbe->regs.rctl.descSize());
653    assert(packet->length < igbe->regs.rctl.descSize());
654
655    if (!unusedCache.size())
656        return false;
657
658    pktPtr = packet;
659
660    igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
661            packet->length, &pktEvent, packet->data);
662    return true;
663}
664
665void
666IGbE::RxDescCache::pktComplete()
667{
668    assert(unusedCache.size());
669    RxDesc *desc;
670    desc = unusedCache.front();
671
672    uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
673    desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
674    DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
675            pktPtr->length, crcfixup,
676            htole((uint16_t)(pktPtr->length + crcfixup)),
677            (uint16_t)(pktPtr->length + crcfixup));
678
679    // no support for anything but starting at 0
680    assert(igbe->regs.rxcsum.pcss() == 0);
681
682    DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n");
683
684    uint8_t status = RXDS_DD | RXDS_EOP;
685    uint8_t err = 0;
686    IpPtr ip(pktPtr);
687    if (ip) {
688        if (igbe->regs.rxcsum.ipofld()) {
689            DPRINTF(EthernetDesc, "Checking IP checksum\n");
690            status |= RXDS_IPCS;
691            desc->csum = htole(cksum(ip));
692            if (cksum(ip) != 0) {
693                err |= RXDE_IPE;
694                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
695            }
696        }
697        TcpPtr tcp(ip);
698        if (tcp && igbe->regs.rxcsum.tuofld()) {
699            DPRINTF(EthernetDesc, "Checking TCP checksum\n");
700            status |= RXDS_TCPCS;
701            desc->csum = htole(cksum(tcp));
702            if (cksum(tcp) != 0) {
703                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
704                err |= RXDE_TCPE;
705            }
706        }
707
708        UdpPtr udp(ip);
709        if (udp && igbe->regs.rxcsum.tuofld()) {
710            DPRINTF(EthernetDesc, "Checking UDP checksum\n");
711            status |= RXDS_UDPCS;
712            desc->csum = htole(cksum(udp));
713            if (cksum(tcp) != 0) {
714                DPRINTF(EthernetDesc, "Checksum is bad!!\n");
715                err |= RXDE_TCPE;
716            }
717        }
718    } // if ip
719
720    desc->status = htole(status);
721    desc->errors = htole(err);
722
723    // No vlan support at this point... just set it to 0
724    desc->vlan = 0;
725
726    // Deal with the rx timer interrupts
727    if (igbe->regs.rdtr.delay()) {
728        DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
729                igbe->regs.rdtr.delay() * igbe->intClock());
730        if (igbe->rdtrEvent.scheduled())
731            igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
732                    igbe->intClock());
733        else
734            igbe->rdtrEvent.schedule(curTick + igbe->regs.rdtr.delay() *
735                    igbe->intClock());
736    }
737
738    if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
739        DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
740                igbe->regs.radv.idv() * igbe->intClock());
741        if (!igbe->radvEvent.scheduled())
742            igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
743                    igbe->intClock());
744    }
745
746    // if neither radv or rdtr, maybe itr is set...
747    if (!igbe->regs.rdtr.delay()) {
748        DPRINTF(EthernetSM, "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
749        igbe->postInterrupt(IT_RXT);
750    }
751
752    // If the packet is small enough, interrupt appropriately
753    // I wonder if this is delayed or not?!
754    if (pktPtr->length <= igbe->regs.rsrpd.idv()) {
755        DPRINTF(EthernetSM, "RXS: Posting IT_SRPD beacuse small packet received\n");
756        igbe->postInterrupt(IT_SRPD);
757    }
758
759    DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
760    unusedCache.pop_front();
761    usedCache.push_back(desc);
762    pktPtr = NULL;
763    enableSm();
764    pktDone = true;
765}
766
767void
768IGbE::RxDescCache::enableSm()
769{
770    igbe->rxTick = true;
771    igbe->restartClock();
772}
773
774bool
775IGbE::RxDescCache::packetDone()
776{
777    if (pktDone) {
778        pktDone = false;
779        return true;
780    }
781    return false;
782}
783
784///////////////////////////////////// IGbE::TxDesc /////////////////////////////////
785
786IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s)
787    : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), pktWaiting(false),
788      hLen(0), pktEvent(this)
789
790{
791}
792
793int
794IGbE::TxDescCache::getPacketSize()
795{
796    assert(unusedCache.size());
797
798    TxDesc *desc;
799
800    DPRINTF(EthernetDesc, "Starting processing of descriptor\n");
801
802    while (unusedCache.size() && TxdOp::isContext(unusedCache.front())) {
803        DPRINTF(EthernetDesc, "Got context descriptor type... skipping\n");
804
805        // I think we can just ignore these for now?
806        desc = unusedCache.front();
807        // is this going to be a tcp or udp packet?
808        isTcp = TxdOp::tcp(desc) ? true : false;
809
810        // make sure it's ipv4
811        assert(TxdOp::ip(desc));
812
813        TxdOp::setDd(desc);
814        unusedCache.pop_front();
815        usedCache.push_back(desc);
816    }
817
818    if (!unusedCache.size())
819        return -1;
820
821    DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n",
822            TxdOp::getLen(unusedCache.front()));
823
824    return TxdOp::getLen(unusedCache.front());
825}
826
827void
828IGbE::TxDescCache::getPacketData(EthPacketPtr p)
829{
830    assert(unusedCache.size());
831
832    TxDesc *desc;
833    desc = unusedCache.front();
834
835    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
836
837    pktPtr = p;
838
839    pktWaiting = true;
840
841    DPRINTF(EthernetDesc, "Starting DMA of packet\n");
842    igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
843            TxdOp::getLen(desc), &pktEvent, p->data + hLen);
844
845
846}
847
848void
849IGbE::TxDescCache::pktComplete()
850{
851
852    TxDesc *desc;
853    assert(unusedCache.size());
854    assert(pktPtr);
855
856    DPRINTF(EthernetDesc, "DMA of packet complete\n");
857
858
859    desc = unusedCache.front();
860    assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
861
862    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
863
864    if (!TxdOp::eop(desc)) {
865        assert(hLen == 0);
866        hLen = TxdOp::getLen(desc);
867        unusedCache.pop_front();
868        usedCache.push_back(desc);
869        pktDone = true;
870        pktWaiting = false;
871        pktPtr = NULL;
872
873        DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n");
874        return;
875    }
876
877    // Set the length of the data in the EtherPacket
878    pktPtr->length = TxdOp::getLen(desc) + hLen;
879
880    // no support for vlans
881    assert(!TxdOp::vle(desc));
882
883    // we alway report status
884    assert(TxdOp::rs(desc));
885
886    // we only support single packet descriptors at this point
887    assert(TxdOp::eop(desc));
888
889    // set that this packet is done
890    TxdOp::setDd(desc);
891
892    DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
893
894    // Checksums are only ofloaded for new descriptor types
895    if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
896        DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
897        IpPtr ip(pktPtr);
898        if (TxdOp::ixsm(desc)) {
899            ip->sum(0);
900            ip->sum(cksum(ip));
901            DPRINTF(EthernetDesc, "Calculated IP checksum\n");
902        }
903       if (TxdOp::txsm(desc)) {
904           if (isTcp) {
905                TcpPtr tcp(ip);
906                tcp->sum(0);
907                tcp->sum(cksum(tcp));
908                DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
909           } else {
910                UdpPtr udp(ip);
911                udp->sum(0);
912                udp->sum(cksum(udp));
913                DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
914           }
915        }
916    }
917
918    if (TxdOp::ide(desc)) {
919        // Deal with the rx timer interrupts
920        DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
921        if (igbe->regs.tidv.idv()) {
922            DPRINTF(EthernetDesc, "setting tidv\n");
923            if (igbe->tidvEvent.scheduled())
924                igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
925                        igbe->intClock());
926            else
927                igbe->tidvEvent.schedule(curTick + igbe->regs.tidv.idv() *
928                        igbe->intClock());
929        }
930
931        if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
932            DPRINTF(EthernetDesc, "setting tadv\n");
933            if (!igbe->tadvEvent.scheduled())
934                igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
935                        igbe->intClock());
936        }
937    }
938
939
940
941    unusedCache.pop_front();
942    usedCache.push_back(desc);
943    pktDone = true;
944    pktWaiting = false;
945    pktPtr = NULL;
946
947    hLen = 0;
948    DPRINTF(EthernetDesc, "Descriptor Done\n");
949
950    if (igbe->regs.txdctl.wthresh() == 0) {
951        DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n");
952        writeback(0);
953    } else if (igbe->regs.txdctl.wthresh() >= usedCache.size()) {
954        DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
955        writeback((igbe->cacheBlockSize()-1)>>4);
956    }
957
958}
959
960bool
961IGbE::TxDescCache::packetAvailable()
962{
963    if (pktDone) {
964        pktDone = false;
965        return true;
966    }
967    return false;
968}
969
970void
971IGbE::TxDescCache::enableSm()
972{
973    igbe->txTick = true;
974    igbe->restartClock();
975}
976
977
978
979
980///////////////////////////////////// IGbE /////////////////////////////////
981
982void
983IGbE::restartClock()
984{
985    if (!tickEvent.scheduled() && (rxTick || txTick))
986        tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1));
987}
988
989
990void
991IGbE::txStateMachine()
992{
993    if (!regs.tctl.en()) {
994        txTick = false;
995        DPRINTF(EthernetSM, "TXS: TX disabled, stopping ticking\n");
996        return;
997    }
998
999    // If we have a packet available and it's length is not 0 (meaning it's not
1000    // a multidescriptor packet) put it in the fifo, otherwise an the next
1001    // iteration we'll get the rest of the data
1002    if (txPacket && txDescCache.packetAvailable() && txPacket->length) {
1003        bool success;
1004        DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
1005        success = txFifo.push(txPacket);
1006        txFifoTick = true;
1007        assert(success);
1008        txPacket = NULL;
1009        txDescCache.writeback((cacheBlockSize()-1)>>4);
1010        return;
1011    }
1012
1013    // Only support descriptor granularity
1014    assert(regs.txdctl.gran());
1015    if (regs.txdctl.lwthresh() && txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) {
1016        DPRINTF(EthernetSM, "TXS: LWTHRESH caused posting of TXDLOW\n");
1017        postInterrupt(IT_TXDLOW);
1018    }
1019
1020    if (!txPacket) {
1021        txPacket = new EthPacketData(16384);
1022    }
1023
1024    if (!txDescCache.packetWaiting()) {
1025        if (txDescCache.descLeft() == 0) {
1026            DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
1027                    "writeback stopping ticking and posting TXQE\n");
1028            txDescCache.writeback(0);
1029            txTick = false;
1030            postInterrupt(IT_TXQE, true);
1031            return;
1032        }
1033
1034
1035        if (!(txDescCache.descUnused())) {
1036            DPRINTF(EthernetSM, "TXS: No descriptors available in cache, fetching and stopping ticking\n");
1037            txTick = false;
1038            txDescCache.fetchDescriptors();
1039            return;
1040        }
1041
1042        int size;
1043        size = txDescCache.getPacketSize();
1044        if (size > 0 && txFifo.avail() > size) {
1045            DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and begining "
1046                    "DMA of next packet\n", size);
1047            txFifo.reserve(size);
1048            txDescCache.getPacketData(txPacket);
1049        } else if (size <= 0) {
1050            DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
1051            txDescCache.writeback(0);
1052        } else {
1053            DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
1054                    "available in FIFO\n");
1055            txDescCache.writeback((cacheBlockSize()-1)>>4);
1056            txTick = false;
1057        }
1058
1059
1060        return;
1061    }
1062}
1063
1064bool
1065IGbE::ethRxPkt(EthPacketPtr pkt)
1066{
1067    DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
1068    if (!regs.rctl.en()) {
1069        DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
1070        return true;
1071    }
1072
1073    // restart the state machines if they are stopped
1074    rxTick = true;
1075    if ((rxTick || txTick) && !tickEvent.scheduled()) {
1076        DPRINTF(EthernetSM, "RXS: received packet into fifo, starting ticking\n");
1077        restartClock();
1078    }
1079
1080    if (!rxFifo.push(pkt)) {
1081        DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n");
1082        postInterrupt(IT_RXO, true);
1083        return false;
1084    }
1085    return true;
1086}
1087
1088
1089void
1090IGbE::rxStateMachine()
1091{
1092    if (!regs.rctl.en()) {
1093        rxTick = false;
1094        DPRINTF(EthernetSM, "RXS: RX disabled, stopping ticking\n");
1095        return;
1096    }
1097
1098    // If the packet is done check for interrupts/descriptors/etc
1099    if (rxDescCache.packetDone()) {
1100        DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n");
1101        int descLeft = rxDescCache.descLeft();
1102        switch (regs.rctl.rdmts()) {
1103            case 2: if (descLeft > .125 * regs.rdlen()) break;
1104            case 1: if (descLeft > .250 * regs.rdlen()) break;
1105            case 0: if (descLeft > .500 * regs.rdlen())  break;
1106                DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) because of descriptors left\n");
1107                postInterrupt(IT_RXDMT);
1108                break;
1109        }
1110
1111        if (descLeft == 0) {
1112            DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
1113                    " writeback and stopping ticking\n");
1114            rxDescCache.writeback(0);
1115            rxTick = false;
1116        }
1117
1118        // only support descriptor granulaties
1119        assert(regs.rxdctl.gran());
1120
1121        if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) {
1122            DPRINTF(EthernetSM, "RXS: Writing back because WTHRESH >= descUsed\n");
1123            if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4))
1124                rxDescCache.writeback(regs.rxdctl.wthresh()-1);
1125            else
1126                rxDescCache.writeback((cacheBlockSize()-1)>>4);
1127        }
1128
1129        if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) &&
1130             ((rxDescCache.descLeft() - rxDescCache.descUnused()) > regs.rxdctl.hthresh())) {
1131            DPRINTF(EthernetSM, "RXS: Fetching descriptors because descUnused < PTHRESH\n");
1132            rxDescCache.fetchDescriptors();
1133        }
1134
1135        if (rxDescCache.descUnused() == 0) {
1136            DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
1137                    "fetching descriptors and stopping ticking\n");
1138            rxTick = false;
1139            rxDescCache.fetchDescriptors();
1140        }
1141        return;
1142    }
1143
1144    if (!rxDescCache.descUnused()) {
1145        DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n");
1146        rxTick = false;
1147        DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n");
1148        rxDescCache.fetchDescriptors();
1149        return;
1150    }
1151
1152    if (rxFifo.empty()) {
1153        DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n");
1154        rxTick = false;
1155        return;
1156    }
1157
1158    EthPacketPtr pkt;
1159    pkt = rxFifo.front();
1160
1161    DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
1162    if (!rxDescCache.writePacket(pkt)) {
1163        return;
1164    }
1165
1166    DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
1167    rxFifo.pop();
1168    DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
1169    rxTick = false;
1170}
1171
1172void
1173IGbE::txWire()
1174{
1175    if (txFifo.empty()) {
1176        txFifoTick = false;
1177        return;
1178    }
1179
1180
1181    if (etherInt->sendPacket(txFifo.front())) {
1182        DPRINTF(Ethernet, "TxFIFO: Successful transmit, bytes in fifo: %d\n",
1183                txFifo.avail());
1184        txFifo.pop();
1185    } else {
1186        // We'll get woken up when the packet ethTxDone() gets called
1187        txFifoTick = false;
1188    }
1189
1190}
1191
1192void
1193IGbE::tick()
1194{
1195    DPRINTF(EthernetSM, "IGbE: -------------- Cycle --------------\n");
1196
1197    if (rxTick)
1198        rxStateMachine();
1199
1200    if (txTick)
1201        txStateMachine();
1202
1203    if (txFifoTick)
1204        txWire();
1205
1206
1207    if (rxTick || txTick || txFifoTick)
1208        tickEvent.schedule(curTick + cycles(1));
1209}
1210
1211void
1212IGbE::ethTxDone()
1213{
1214    // restart the tx state machines if they are stopped
1215    // fifo to send another packet
1216    // tx sm to put more data into the fifo
1217    txFifoTick = true;
1218    txTick = true;
1219
1220    restartClock();
1221    DPRINTF(Ethernet, "TxFIFO: Transmission complete\n");
1222}
1223
1224void
1225IGbE::serialize(std::ostream &os)
1226{
1227    panic("Need to implemenet\n");
1228}
1229
1230void
1231IGbE::unserialize(Checkpoint *cp, const std::string &section)
1232{
1233    panic("Need to implemenet\n");
1234}
1235
1236
1237BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
1238
1239    SimObjectParam<EtherInt *> peer;
1240    SimObjectParam<IGbE *> device;
1241
1242END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
1243
1244BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
1245
1246    INIT_PARAM_DFLT(peer, "peer interface", NULL),
1247    INIT_PARAM(device, "Ethernet device of this interface")
1248
1249END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
1250
1251CREATE_SIM_OBJECT(IGbEInt)
1252{
1253    IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
1254
1255    EtherInt *p = (EtherInt *)peer;
1256    if (p) {
1257        dev_int->setPeer(p);
1258        p->setPeer(dev_int);
1259    }
1260
1261    return dev_int;
1262}
1263
1264REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
1265
1266
1267BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
1268
1269    SimObjectParam<System *> system;
1270    SimObjectParam<Platform *> platform;
1271    SimObjectParam<PciConfigData *> configdata;
1272    Param<uint32_t> pci_bus;
1273    Param<uint32_t> pci_dev;
1274    Param<uint32_t> pci_func;
1275    Param<Tick> pio_latency;
1276    Param<Tick> config_latency;
1277    Param<std::string> hardware_address;
1278    Param<bool> use_flow_control;
1279    Param<int> rx_fifo_size;
1280    Param<int> tx_fifo_size;
1281    Param<int> rx_desc_cache_size;
1282    Param<int> tx_desc_cache_size;
1283    Param<Tick> clock;
1284
1285
1286END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
1287
1288BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
1289
1290    INIT_PARAM(system, "System pointer"),
1291    INIT_PARAM(platform, "Platform pointer"),
1292    INIT_PARAM(configdata, "PCI Config data"),
1293    INIT_PARAM(pci_bus, "PCI bus ID"),
1294    INIT_PARAM(pci_dev, "PCI device number"),
1295    INIT_PARAM(pci_func, "PCI function code"),
1296    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
1297    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
1298    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
1299    INIT_PARAM(use_flow_control,"Should the device use xon/off packets"),
1300    INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"),
1301    INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"),
1302    INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"),
1303    INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"),
1304    INIT_PARAM(clock,"Clock rate for the device to tick at")
1305
1306END_INIT_SIM_OBJECT_PARAMS(IGbE)
1307
1308
1309CREATE_SIM_OBJECT(IGbE)
1310{
1311    IGbE::Params *params = new IGbE::Params;
1312
1313    params->name = getInstanceName();
1314    params->platform = platform;
1315    params->system = system;
1316    params->configData = configdata;
1317    params->busNum = pci_bus;
1318    params->deviceNum = pci_dev;
1319    params->functionNum = pci_func;
1320    params->pio_delay = pio_latency;
1321    params->config_delay = config_latency;
1322    params->hardware_address = hardware_address;
1323    params->use_flow_control = use_flow_control;
1324    params->rx_fifo_size = rx_fifo_size;
1325    params->tx_fifo_size = tx_fifo_size;
1326    params->rx_desc_cache_size = rx_desc_cache_size;
1327    params->tx_desc_cache_size = tx_desc_cache_size;
1328    params->clock = clock;
1329
1330
1331    return new IGbE(params);
1332}
1333
1334REGISTER_SIM_OBJECT("IGbE", IGbE)
1335