i8254xGBe.cc revision 3116 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 */
34
35#include "base/inet.hh"
36#include "dev/i8254xGBe.hh"
37#include "mem/packet.hh"
38#include "sim/builder.hh"
39#include "sim/stats.hh"
40#include "sim/system.hh"
41
42IGbE::IGbE(Params *p)
43    : PciDev(p), etherInt(NULL)
44{
45
46}
47
48
49Tick
50IGbE::writeConfig(Packet *pkt)
51{
52    int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
53    if (offset < PCI_DEVICE_SPECIFIC)
54        PciDev::writeConfig(pkt);
55    else
56        panic("Device specific PCI config space not implemented.\n");
57
58    ///
59    /// Some work may need to be done here based for the pci COMMAND bits.
60    ///
61
62    return pioDelay;
63}
64
65Tick
66IGbE::read(Packet *pkt)
67{
68    int bar;
69    Addr daddr;
70
71    if (!getBAR(pkt->getAddr(), bar, daddr))
72        panic("Invalid PCI memory access to unmapped memory.\n");
73
74    // Only Memory register BAR is allowed
75    assert(bar == 0);
76
77    DPRINTF(Ethernet, "Accessed devie register %#X\n", daddr);
78
79    pkt->allocate();
80
81
82    ///
83    /// Handle read of register here
84    ///
85
86    pkt->result = Packet::Success;
87    return pioDelay;
88}
89
90Tick
91IGbE::write(Packet *pkt)
92{
93    int bar;
94    Addr daddr;
95
96    if (!getBAR(pkt->getAddr(), bar, daddr))
97        panic("Invalid PCI memory access to unmapped memory.\n");
98
99    // Only Memory register BAR is allowed
100    assert(bar == 0);
101
102    DPRINTF(Ethernet, "Accessed devie register %#X\n", daddr);
103
104    ///
105    /// Handle write of register here
106    ///
107
108    pkt->result = Packet::Success;
109    return pioDelay;
110}
111
112
113bool
114IGbE::ethRxPkt(EthPacketPtr packet)
115{
116    panic("Need to implemenet\n");
117}
118
119
120void
121IGbE::ethTxDone()
122{
123    panic("Need to implemenet\n");
124}
125
126void
127IGbE::serialize(std::ostream &os)
128{
129    panic("Need to implemenet\n");
130}
131
132void
133IGbE::unserialize(Checkpoint *cp, const std::string &section)
134{
135    panic("Need to implemenet\n");
136}
137
138
139BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
140
141    SimObjectParam<EtherInt *> peer;
142    SimObjectParam<IGbE *> device;
143
144END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
145
146BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
147
148    INIT_PARAM_DFLT(peer, "peer interface", NULL),
149    INIT_PARAM(device, "Ethernet device of this interface")
150
151END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
152
153CREATE_SIM_OBJECT(IGbEInt)
154{
155    IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
156
157    EtherInt *p = (EtherInt *)peer;
158    if (p) {
159        dev_int->setPeer(p);
160        p->setPeer(dev_int);
161    }
162
163    return dev_int;
164}
165
166REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
167
168
169BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
170
171    SimObjectParam<System *> system;
172    SimObjectParam<Platform *> platform;
173    SimObjectParam<PciConfigData *> configdata;
174    Param<uint32_t> pci_bus;
175    Param<uint32_t> pci_dev;
176    Param<uint32_t> pci_func;
177    Param<Tick> pio_latency;
178    Param<Tick> config_latency;
179
180END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
181
182BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
183
184    INIT_PARAM(system, "System pointer"),
185    INIT_PARAM(platform, "Platform pointer"),
186    INIT_PARAM(configdata, "PCI Config data"),
187    INIT_PARAM(pci_bus, "PCI bus ID"),
188    INIT_PARAM(pci_dev, "PCI device number"),
189    INIT_PARAM(pci_func, "PCI function code"),
190    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
191    INIT_PARAM(config_latency, "Number of cycles for a config read or write")
192
193END_INIT_SIM_OBJECT_PARAMS(IGbE)
194
195
196CREATE_SIM_OBJECT(IGbE)
197{
198    IGbE::Params *params = new IGbE::Params;
199
200    params->name = getInstanceName();
201    params->platform = platform;
202    params->system = system;
203    params->configData = configdata;
204    params->busNum = pci_bus;
205    params->deviceNum = pci_dev;
206    params->functionNum = pci_func;
207    params->pio_delay = pio_latency;
208    params->config_delay = config_latency;
209
210    return new IGbE(params);
211}
212
213REGISTER_SIM_OBJECT("IGbE", IGbE)
214