maltareg.h revision 5222
15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35222Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145222Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Ali Saidi 295222Sksewell@umich.edu */ 305222Sksewell@umich.edu 315222Sksewell@umich.edu/** @file 325222Sksewell@umich.edu * List of Tsunami CSRs 335222Sksewell@umich.edu */ 345222Sksewell@umich.edu 355222Sksewell@umich.edu// NEEDS TO BE ADJUSTED FOR MALTA BOARD 365222Sksewell@umich.edu 375222Sksewell@umich.edu#ifndef __MALTAREG_H__ 385222Sksewell@umich.edu#define __MALTAREG_H__ 395222Sksewell@umich.edu 405222Sksewell@umich.edu#define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000) 415222Sksewell@umich.edu 425222Sksewell@umich.edu// CChip Registers 435222Sksewell@umich.edu#define TSDEV_CC_CSR 0x00 445222Sksewell@umich.edu#define TSDEV_CC_MTR 0x01 455222Sksewell@umich.edu#define TSDEV_CC_MISC 0x02 465222Sksewell@umich.edu 475222Sksewell@umich.edu#define TSDEV_CC_AAR0 0x04 485222Sksewell@umich.edu#define TSDEV_CC_AAR1 0x05 495222Sksewell@umich.edu#define TSDEV_CC_AAR2 0x06 505222Sksewell@umich.edu#define TSDEV_CC_AAR3 0x07 515222Sksewell@umich.edu#define TSDEV_CC_DIM0 0x08 525222Sksewell@umich.edu#define TSDEV_CC_DIM1 0x09 535222Sksewell@umich.edu#define TSDEV_CC_DIR0 0x0A 545222Sksewell@umich.edu#define TSDEV_CC_DIR1 0x0B 555222Sksewell@umich.edu#define TSDEV_CC_DRIR 0x0C 565222Sksewell@umich.edu#define TSDEV_CC_PRBEN 0x0D 575222Sksewell@umich.edu#define TSDEV_CC_IIC0 0x0E 585222Sksewell@umich.edu#define TSDEV_CC_IIC1 0x0F 595222Sksewell@umich.edu#define TSDEV_CC_MPR0 0x10 605222Sksewell@umich.edu#define TSDEV_CC_MPR1 0x11 615222Sksewell@umich.edu#define TSDEV_CC_MPR2 0x12 625222Sksewell@umich.edu#define TSDEV_CC_MPR3 0x13 635222Sksewell@umich.edu 645222Sksewell@umich.edu#define TSDEV_CC_DIM2 0x18 655222Sksewell@umich.edu#define TSDEV_CC_DIM3 0x19 665222Sksewell@umich.edu#define TSDEV_CC_DIR2 0x1A 675222Sksewell@umich.edu#define TSDEV_CC_DIR3 0x1B 685222Sksewell@umich.edu#define TSDEV_CC_IIC2 0x1C 695222Sksewell@umich.edu#define TSDEV_CC_IIC3 0x1D 705222Sksewell@umich.edu 715222Sksewell@umich.edu// BigTsunami Registers 725222Sksewell@umich.edu#define TSDEV_CC_BDIMS 0x1000000 735222Sksewell@umich.edu#define TSDEV_CC_BDIRS 0x2000000 745222Sksewell@umich.edu#define TSDEV_CC_IPIQ 0x20 //0xf01a000800 755222Sksewell@umich.edu#define TSDEV_CC_IPIR 0x21 //0xf01a000840 765222Sksewell@umich.edu#define TSDEV_CC_ITIR 0x22 //0xf01a000880 775222Sksewell@umich.edu 785222Sksewell@umich.edu 795222Sksewell@umich.edu// PChip Registers 805222Sksewell@umich.edu#define TSDEV_PC_WSBA0 0x00 815222Sksewell@umich.edu#define TSDEV_PC_WSBA1 0x01 825222Sksewell@umich.edu#define TSDEV_PC_WSBA2 0x02 835222Sksewell@umich.edu#define TSDEV_PC_WSBA3 0x03 845222Sksewell@umich.edu#define TSDEV_PC_WSM0 0x04 855222Sksewell@umich.edu#define TSDEV_PC_WSM1 0x05 865222Sksewell@umich.edu#define TSDEV_PC_WSM2 0x06 875222Sksewell@umich.edu#define TSDEV_PC_WSM3 0x07 885222Sksewell@umich.edu#define TSDEV_PC_TBA0 0x08 895222Sksewell@umich.edu#define TSDEV_PC_TBA1 0x09 905222Sksewell@umich.edu#define TSDEV_PC_TBA2 0x0A 915222Sksewell@umich.edu#define TSDEV_PC_TBA3 0x0B 925222Sksewell@umich.edu#define TSDEV_PC_PCTL 0x0C 935222Sksewell@umich.edu#define TSDEV_PC_PLAT 0x0D 945222Sksewell@umich.edu#define TSDEV_PC_RES 0x0E 955222Sksewell@umich.edu#define TSDEV_PC_PERROR 0x0F 965222Sksewell@umich.edu#define TSDEV_PC_PERRMASK 0x10 975222Sksewell@umich.edu#define TSDEV_PC_PERRSET 0x11 985222Sksewell@umich.edu#define TSDEV_PC_TLBIV 0x12 995222Sksewell@umich.edu#define TSDEV_PC_TLBIA 0x13 1005222Sksewell@umich.edu#define TSDEV_PC_PMONCTL 0x14 1015222Sksewell@umich.edu#define TSDEV_PC_PMONCNT 0x15 1025222Sksewell@umich.edu 1035222Sksewell@umich.edu#define TSDEV_PC_SPST 0x20 1045222Sksewell@umich.edu 1055222Sksewell@umich.edu 1065222Sksewell@umich.edu// DChip Registers 1075222Sksewell@umich.edu#define TSDEV_DC_DSC 0x20 1085222Sksewell@umich.edu#define TSDEV_DC_STR 0x21 1095222Sksewell@umich.edu#define TSDEV_DC_DREV 0x22 1105222Sksewell@umich.edu#define TSDEV_DC_DSC2 0x23 1115222Sksewell@umich.edu 1125222Sksewell@umich.edu// I/O Ports 1135222Sksewell@umich.edu#define TSDEV_PIC1_MASK 0x21 1145222Sksewell@umich.edu#define TSDEV_PIC2_MASK 0xA1 1155222Sksewell@umich.edu#define TSDEV_PIC1_ISR 0x20 1165222Sksewell@umich.edu#define TSDEV_PIC2_ISR 0xA0 1175222Sksewell@umich.edu#define TSDEV_PIC1_ACK 0x20 1185222Sksewell@umich.edu#define TSDEV_PIC2_ACK 0xA0 1195222Sksewell@umich.edu#define TSDEV_DMA1_RESET 0x0D 1205222Sksewell@umich.edu#define TSDEV_DMA2_RESET 0xDA 1215222Sksewell@umich.edu#define TSDEV_DMA1_MODE 0x0B 1225222Sksewell@umich.edu#define TSDEV_DMA2_MODE 0xD6 1235222Sksewell@umich.edu#define TSDEV_DMA1_MASK 0x0A 1245222Sksewell@umich.edu#define TSDEV_DMA2_MASK 0xD4 1255222Sksewell@umich.edu#define TSDEV_CTRL_PORTB 0x61 1265222Sksewell@umich.edu#define TSDEV_TMR0_DATA 0x40 1275222Sksewell@umich.edu#define TSDEV_TMR1_DATA 0x41 1285222Sksewell@umich.edu#define TSDEV_TMR2_DATA 0x42 1295222Sksewell@umich.edu#define TSDEV_TMR_CTRL 0x43 1305222Sksewell@umich.edu#define TSDEV_KBD 0x64 1315222Sksewell@umich.edu#define TSDEV_DMA1_CMND 0x08 1325222Sksewell@umich.edu#define TSDEV_DMA1_STAT TSDEV_DMA1_CMND 1335222Sksewell@umich.edu#define TSDEV_DMA2_CMND 0xD0 1345222Sksewell@umich.edu#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND 1355222Sksewell@umich.edu#define TSDEV_DMA1_MMASK 0x0F 1365222Sksewell@umich.edu#define TSDEV_DMA2_MMASK 0xDE 1375222Sksewell@umich.edu 1385222Sksewell@umich.edu// Added for keyboard accesses / 1395222Sksewell@umich.edu#define TSDEV_KBD 0x64 1405222Sksewell@umich.edu 1415222Sksewell@umich.edu// Added for ATA PCI DMA / 1425222Sksewell@umich.edu#define ATA_PCI_DMA 0x00 1435222Sksewell@umich.edu#define ATA_PCI_DMA2 0x02 1445222Sksewell@umich.edu#define ATA_PCI_DMA3 0x16 1455222Sksewell@umich.edu#define ATA_PCI_DMA4 0x17 1465222Sksewell@umich.edu#define ATA_PCI_DMA5 0x1a 1475222Sksewell@umich.edu#define ATA_PCI_DMA6 0x11 1485222Sksewell@umich.edu#define ATA_PCI_DMA7 0x14 1495222Sksewell@umich.edu 1505222Sksewell@umich.edu#define TSDEV_RTC_ADDR 0x70 1515222Sksewell@umich.edu#define TSDEV_RTC_DATA 0x71 1525222Sksewell@umich.edu 1535222Sksewell@umich.edu#define PCHIP_PCI0_MEMORY ULL(0x00000000000) 1545222Sksewell@umich.edu#define PCHIP_PCI0_IO ULL(0x001FC000000) 1555222Sksewell@umich.edu#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) 1565222Sksewell@umich.edu#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY 1575222Sksewell@umich.edu#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO 1585222Sksewell@umich.edu 1595222Sksewell@umich.edu 1605222Sksewell@umich.edu// UART Defines 1615222Sksewell@umich.edu//Relates to whether the kernel wants an interrupt when data is available 1625222Sksewell@umich.edu#define UART_IER_RDI 0x01 1635222Sksewell@umich.edu#define UART_IER_THRI 0x02 1645222Sksewell@umich.edu#define UART_IER_RLSI 0x04 1655222Sksewell@umich.edu 1665222Sksewell@umich.edu 1675222Sksewell@umich.edu#define UART_LSR_TEMT 0x40 1685222Sksewell@umich.edu#define UART_LSR_THRE 0x20 1695222Sksewell@umich.edu#define UART_LSR_DR 0x01 1705222Sksewell@umich.edu 1715222Sksewell@umich.edu#define UART_MCR_LOOP 0x10 1725222Sksewell@umich.edu 1735222Sksewell@umich.edu// System Control PortB Status Bits 1745222Sksewell@umich.edu#define PORTB_SPKR_HIGH 0x20 1755222Sksewell@umich.edu 1765222Sksewell@umich.edu#endif // __MALTAREG_H__ 177