malta_cchip.cc revision 8739:925f15f96322
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Rick Strong 30 */ 31 32/** @file 33 * Emulation of the Malta CChip CSRs 34 */ 35 36#include <deque> 37#include <string> 38#include <vector> 39 40#include "arch/mips/mips_core_specific.hh" 41#include "base/trace.hh" 42#include "config/the_isa.hh" 43#include "cpu/intr_control.hh" 44#include "cpu/thread_context.hh" 45#include "debug/Malta.hh" 46#include "dev/mips/malta.hh" 47#include "dev/mips/malta_cchip.hh" 48#include "dev/mips/maltareg.h" 49#include "mem/packet.hh" 50#include "mem/packet_access.hh" 51#include "mem/port.hh" 52#include "params/MaltaCChip.hh" 53#include "sim/system.hh" 54 55using namespace std; 56using namespace TheISA; 57 58MaltaCChip::MaltaCChip(Params *p) 59 : BasicPioDevice(p), malta(p->malta) 60{ 61 warn("MaltaCCHIP::MaltaCChip() not implemented."); 62 63 pioSize = 0xfffffff; 64 //Put back pointer in malta 65 malta->cchip = this; 66 67} 68 69Tick 70MaltaCChip::read(PacketPtr pkt) 71{ 72 panic("MaltaCCHIP::read() not implemented."); 73 return pioDelay; 74 /* 75 DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 76 77 assert(pkt->result == Packet::Unknown); 78 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 79 80 Addr regnum = (pkt->getAddr() - pioAddr) >> 6; 81 Addr daddr = (pkt->getAddr() - pioAddr); 82 83 pkt->allocate(); 84 switch (pkt->getSize()) { 85 86 case sizeof(uint64_t): 87 if (daddr & TSDEV_CC_BDIMS) 88 { 89 pkt->set(dim[(daddr >> 4) & 0x3F]); 90 break; 91 } 92 93 if (daddr & TSDEV_CC_BDIRS) 94 { 95 pkt->set(dir[(daddr >> 4) & 0x3F]); 96 break; 97 } 98 99 switch(regnum) { 100 case TSDEV_CC_CSR: 101 pkt->set(0x0); 102 break; 103 case TSDEV_CC_MTR: 104 panic("TSDEV_CC_MTR not implemeted\n"); 105 break; 106 case TSDEV_CC_MISC: 107 pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF | 108 (pkt->req->contextId() & 0x3)); 109 break; 110 case TSDEV_CC_AAR0: 111 case TSDEV_CC_AAR1: 112 case TSDEV_CC_AAR2: 113 case TSDEV_CC_AAR3: 114 pkt->set(0); 115 break; 116 case TSDEV_CC_DIM0: 117 pkt->set(dim[0]); 118 break; 119 case TSDEV_CC_DIM1: 120 pkt->set(dim[1]); 121 break; 122 case TSDEV_CC_DIM2: 123 pkt->set(dim[2]); 124 break; 125 case TSDEV_CC_DIM3: 126 pkt->set(dim[3]); 127 break; 128 case TSDEV_CC_DIR0: 129 pkt->set(dir[0]); 130 break; 131 case TSDEV_CC_DIR1: 132 pkt->set(dir[1]); 133 break; 134 case TSDEV_CC_DIR2: 135 pkt->set(dir[2]); 136 break; 137 case TSDEV_CC_DIR3: 138 pkt->set(dir[3]); 139 break; 140 case TSDEV_CC_DRIR: 141 pkt->set(drir); 142 break; 143 case TSDEV_CC_PRBEN: 144 panic("TSDEV_CC_PRBEN not implemented\n"); 145 break; 146 case TSDEV_CC_IIC0: 147 case TSDEV_CC_IIC1: 148 case TSDEV_CC_IIC2: 149 case TSDEV_CC_IIC3: 150 panic("TSDEV_CC_IICx not implemented\n"); 151 break; 152 case TSDEV_CC_MPR0: 153 case TSDEV_CC_MPR1: 154 case TSDEV_CC_MPR2: 155 case TSDEV_CC_MPR3: 156 panic("TSDEV_CC_MPRx not implemented\n"); 157 break; 158 case TSDEV_CC_IPIR: 159 pkt->set(ipint); 160 break; 161 case TSDEV_CC_ITIR: 162 pkt->set(itint); 163 break; 164 default: 165 panic("default in cchip read reached, accessing 0x%x\n"); 166 } // uint64_t 167 168 break; 169 case sizeof(uint32_t): 170 case sizeof(uint16_t): 171 case sizeof(uint8_t): 172 default: 173 panic("invalid access size(?) for malta register!\n"); 174 } 175 DPRINTF(Malta, "Malta CChip: read regnum=%#x size=%d data=%lld\n", 176 regnum, pkt->getSize(), pkt->get<uint64_t>()); 177 178 pkt->result = Packet::Success; 179 return pioDelay; 180 */ 181} 182 183Tick 184MaltaCChip::write(PacketPtr pkt) 185{ 186 panic("MaltaCCHIP::write() not implemented."); 187 return pioDelay; 188 /* 189 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 190 Addr daddr = pkt->getAddr() - pioAddr; 191 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; 192 193 194 assert(pkt->getSize() == sizeof(uint64_t)); 195 196 DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>()); 197 198 bool supportedWrite = false; 199 200 201 if (daddr & TSDEV_CC_BDIMS) 202 { 203 int number = (daddr >> 4) & 0x3F; 204 205 uint64_t bitvector; 206 uint64_t olddim; 207 uint64_t olddir; 208 209 olddim = dim[number]; 210 olddir = dir[number]; 211 dim[number] = pkt->get<uint64_t>(); 212 dir[number] = dim[number] & drir; 213 for(int x = 0; x < Malta::Max_CPUs; x++) 214 { 215 bitvector = ULL(1) << x; 216 // Figure out which bits have changed 217 if ((dim[number] & bitvector) != (olddim & bitvector)) 218 { 219 // The bit is now set and it wasn't before (set) 220 if((dim[number] & bitvector) && (dir[number] & bitvector)) 221 { 222 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 223 DPRINTF(Malta, "dim write resulting in posting dir" 224 " interrupt to cpu %d\n", number); 225 } 226 else if ((olddir & bitvector) && 227 !(dir[number] & bitvector)) 228 { 229 // The bit was set and now its now clear and 230 // we were interrupting on that bit before 231 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 232 DPRINTF(Malta, "dim write resulting in clear" 233 " dir interrupt to cpu %d\n", number); 234 235 } 236 237 238 } 239 } 240 } else { 241 switch(regnum) { 242 case TSDEV_CC_CSR: 243 panic("TSDEV_CC_CSR write\n"); 244 case TSDEV_CC_MTR: 245 panic("TSDEV_CC_MTR write not implemented\n"); 246 case TSDEV_CC_MISC: 247 uint64_t ipreq; 248 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; 249 //If it is bit 12-15, this is an IPI post 250 if (ipreq) { 251 reqIPI(ipreq); 252 supportedWrite = true; 253 } 254 255 //If it is bit 8-11, this is an IPI clear 256 uint64_t ipintr; 257 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; 258 if (ipintr) { 259 clearIPI(ipintr); 260 supportedWrite = true; 261 } 262 263 //If it is the 4-7th bit, clear the RTC interrupt 264 uint64_t itintr; 265 itintr = (pkt->get<uint64_t>() >> 4) & 0xF; 266 if (itintr) { 267 clearITI(itintr); 268 supportedWrite = true; 269 } 270 271 // ignore NXMs 272 if (pkt->get<uint64_t>() & 0x10000000) 273 supportedWrite = true; 274 275 if(!supportedWrite) 276 panic("TSDEV_CC_MISC write not implemented\n"); 277 278 break; 279 case TSDEV_CC_AAR0: 280 case TSDEV_CC_AAR1: 281 case TSDEV_CC_AAR2: 282 case TSDEV_CC_AAR3: 283 panic("TSDEV_CC_AARx write not implemeted\n"); 284 case TSDEV_CC_DIM0: 285 case TSDEV_CC_DIM1: 286 case TSDEV_CC_DIM2: 287 case TSDEV_CC_DIM3: 288 int number; 289 if(regnum == TSDEV_CC_DIM0) 290 number = 0; 291 else if(regnum == TSDEV_CC_DIM1) 292 number = 1; 293 else if(regnum == TSDEV_CC_DIM2) 294 number = 2; 295 else 296 number = 3; 297 298 uint64_t bitvector; 299 uint64_t olddim; 300 uint64_t olddir; 301 302 olddim = dim[number]; 303 olddir = dir[number]; 304 dim[number] = pkt->get<uint64_t>(); 305 dir[number] = dim[number] & drir; 306 for(int x = 0; x < 64; x++) 307 { 308 bitvector = ULL(1) << x; 309 // Figure out which bits have changed 310 if ((dim[number] & bitvector) != (olddim & bitvector)) 311 { 312 // The bit is now set and it wasn't before (set) 313 if((dim[number] & bitvector) && (dir[number] & bitvector)) 314 { 315 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 316 DPRINTF(Malta, "posting dir interrupt to cpu 0\n"); 317 } 318 else if ((olddir & bitvector) && 319 !(dir[number] & bitvector)) 320 { 321 // The bit was set and now its now clear and 322 // we were interrupting on that bit before 323 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 324 DPRINTF(Malta, "dim write resulting in clear" 325 " dir interrupt to cpu %d\n", 326 x); 327 328 } 329 330 331 } 332 } 333 break; 334 case TSDEV_CC_DIR0: 335 case TSDEV_CC_DIR1: 336 case TSDEV_CC_DIR2: 337 case TSDEV_CC_DIR3: 338 panic("TSDEV_CC_DIR write not implemented\n"); 339 case TSDEV_CC_DRIR: 340 panic("TSDEV_CC_DRIR write not implemented\n"); 341 case TSDEV_CC_PRBEN: 342 panic("TSDEV_CC_PRBEN write not implemented\n"); 343 case TSDEV_CC_IIC0: 344 case TSDEV_CC_IIC1: 345 case TSDEV_CC_IIC2: 346 case TSDEV_CC_IIC3: 347 panic("TSDEV_CC_IICx write not implemented\n"); 348 case TSDEV_CC_MPR0: 349 case TSDEV_CC_MPR1: 350 case TSDEV_CC_MPR2: 351 case TSDEV_CC_MPR3: 352 panic("TSDEV_CC_MPRx write not implemented\n"); 353 case TSDEV_CC_IPIR: 354 clearIPI(pkt->get<uint64_t>()); 355 break; 356 case TSDEV_CC_ITIR: 357 clearITI(pkt->get<uint64_t>()); 358 break; 359 case TSDEV_CC_IPIQ: 360 reqIPI(pkt->get<uint64_t>()); 361 break; 362 default: 363 panic("default in cchip read reached, accessing 0x%x\n"); 364 } // swtich(regnum) 365 } // not BIG_TSUNAMI write 366 pkt->result = Packet::Success; 367 return pioDelay; 368 */ 369} 370 371void 372MaltaCChip::clearIPI(uint64_t ipintr) 373{ 374 panic("MaltaCCHIP::clear() not implemented."); 375 /* 376 int numcpus = malta->intrctrl->cpu->system->threadContexts.size(); 377 assert(numcpus <= Malta::Max_CPUs); 378 379 if (ipintr) { 380 for (int cpunum=0; cpunum < numcpus; cpunum++) { 381 // Check each cpu bit 382 uint64_t cpumask = ULL(1) << cpunum; 383 if (ipintr & cpumask) { 384 // Check if there is a pending ipi 385 if (ipint & cpumask) { 386 ipint &= ~cpumask; 387 malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 388 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 389 } 390 else 391 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 392 } 393 } 394 } 395 else 396 panic("Big IPI Clear, but not processors indicated\n"); 397 */ 398} 399 400void 401MaltaCChip::clearITI(uint64_t itintr) 402{ 403 panic("MaltaCCHIP::clearITI() not implemented."); 404 /* 405 int numcpus = malta->intrctrl->cpu->system->threadContexts.size(); 406 assert(numcpus <= Malta::Max_CPUs); 407 408 if (itintr) { 409 for (int i=0; i < numcpus; i++) { 410 uint64_t cpumask = ULL(1) << i; 411 if (itintr & cpumask & itint) { 412 malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 413 itint &= ~cpumask; 414 DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i); 415 } 416 } 417 } 418 else 419 panic("Big ITI Clear, but not processors indicated\n"); 420 */ 421} 422 423void 424MaltaCChip::reqIPI(uint64_t ipreq) 425{ 426 panic("MaltaCCHIP::reqIPI() not implemented."); 427 428 /* 429 int numcpus = malta->intrctrl->cpu->system->threadContexts.size(); 430 assert(numcpus <= Malta::Max_CPUs); 431 432 if (ipreq) { 433 for (int cpunum=0; cpunum < numcpus; cpunum++) { 434 // Check each cpu bit 435 uint64_t cpumask = ULL(1) << cpunum; 436 if (ipreq & cpumask) { 437 // Check if there is already an ipi (bits 8:11) 438 if (!(ipint & cpumask)) { 439 ipint |= cpumask; 440 malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 441 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 442 } 443 else 444 warn("post IPI for CPU=%d, but IPI already\n", cpunum); 445 } 446 } 447 } 448 else 449 panic("Big IPI Request, but not processors indicated\n"); 450 */ 451 452} 453 454 455void 456MaltaCChip::postRTC() 457{ 458 panic("MaltaCCHIP::postRTC() not implemented."); 459 460 /* 461 int size = malta->intrctrl->cpu->system->threadContexts.size(); 462 assert(size <= Malta::Max_CPUs); 463 464 for (int i = 0; i < size; i++) { 465 uint64_t cpumask = ULL(1) << i; 466 if (!(cpumask & itint)) { 467 itint |= cpumask; 468 malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 469 DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i); 470 } 471 } 472 */ 473 474} 475 476void 477MaltaCChip::postIntr(uint32_t interrupt) 478{ 479 uint64_t size = sys->threadContexts.size(); 480 assert(size <= Malta::Max_CPUs); 481 482 for(int i=0; i < size; i++) { 483 //Note: Malta does not use index, but this was added to use the pre-existing implementation 484 malta->intrctrl->post(i, interrupt, 0); 485 DPRINTF(Malta, "posting interrupt to cpu %d," 486 "interrupt %d\n",i, interrupt); 487 } 488 489} 490 491void 492MaltaCChip::clearIntr(uint32_t interrupt) 493{ 494 uint64_t size = sys->threadContexts.size(); 495 assert(size <= Malta::Max_CPUs); 496 497 for(int i=0; i < size; i++) { 498 //Note: Malta does not use index, but this was added to use the pre-existing implementation 499 malta->intrctrl->clear(i, interrupt, 0); 500 DPRINTF(Malta, "clearing interrupt to cpu %d," 501 "interrupt %d\n",i, interrupt); 502 } 503} 504 505 506void 507MaltaCChip::serialize(std::ostream &os) 508{ 509 // SERIALIZE_ARRAY(dim, Malta::Max_CPUs); 510 //SERIALIZE_ARRAY(dir, Malta::Max_CPUs); 511 //SERIALIZE_SCALAR(ipint); 512 //SERIALIZE_SCALAR(itint); 513 //SERIALIZE_SCALAR(drir); 514} 515 516void 517MaltaCChip::unserialize(Checkpoint *cp, const std::string §ion) 518{ 519 //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs); 520 //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs); 521 //UNSERIALIZE_SCALAR(ipint); 522 //UNSERIALIZE_SCALAR(itint); 523 //UNSERIALIZE_SCALAR(drir); 524} 525 526MaltaCChip * 527MaltaCChipParams::create() 528{ 529 return new MaltaCChip(this); 530} 531 532