malta.hh revision 6379
15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35222Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145222Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Ali Saidi 295222Sksewell@umich.edu * Rick Strong 305222Sksewell@umich.edu */ 315222Sksewell@umich.edu 325222Sksewell@umich.edu/** 335222Sksewell@umich.edu * @file 345222Sksewell@umich.edu * Declaration of top level class for the Malta chipset. This class just 355222Sksewell@umich.edu * retains pointers to all its children so the children can communicate. 365222Sksewell@umich.edu */ 375222Sksewell@umich.edu 385222Sksewell@umich.edu#ifndef __DEV_MALTA_HH__ 395222Sksewell@umich.edu#define __DEV_MALTA_HH__ 405222Sksewell@umich.edu 415222Sksewell@umich.edu#include "dev/platform.hh" 425222Sksewell@umich.edu#include "params/Malta.hh" 435222Sksewell@umich.edu 445222Sksewell@umich.educlass IdeController; 455222Sksewell@umich.educlass MaltaCChip; 465222Sksewell@umich.educlass MaltaPChip; 475222Sksewell@umich.educlass MaltaIO; 485222Sksewell@umich.educlass System; 495222Sksewell@umich.edu 505222Sksewell@umich.edu/** 515222Sksewell@umich.edu * Top level class for Malta Chipset emulation. 525222Sksewell@umich.edu * This structure just contains pointers to all the 535222Sksewell@umich.edu * children so the children can commnicate to do the 545222Sksewell@umich.edu * read work 555222Sksewell@umich.edu */ 565222Sksewell@umich.edu 575222Sksewell@umich.educlass Malta : public Platform 585222Sksewell@umich.edu{ 595222Sksewell@umich.edu public: 605222Sksewell@umich.edu /** Max number of CPUs in a Malta */ 615222Sksewell@umich.edu static const int Max_CPUs = 64; 625222Sksewell@umich.edu 635222Sksewell@umich.edu /** Pointer to the system */ 645222Sksewell@umich.edu System *system; 655222Sksewell@umich.edu 665222Sksewell@umich.edu /** Pointer to the MaltaIO device which has the RTC */ 675222Sksewell@umich.edu MaltaIO *io; 685222Sksewell@umich.edu 695222Sksewell@umich.edu /** Pointer to the Malta CChip. 705222Sksewell@umich.edu * The chip contains some configuration information and 715222Sksewell@umich.edu * all the interrupt mask and status registers 725222Sksewell@umich.edu */ 735222Sksewell@umich.edu MaltaCChip *cchip; 745222Sksewell@umich.edu 755222Sksewell@umich.edu /** Pointer to the Malta PChip. 765222Sksewell@umich.edu * The pchip is the interface to the PCI bus, in our case 775222Sksewell@umich.edu * it does not have to do much. 785222Sksewell@umich.edu */ 795222Sksewell@umich.edu MaltaPChip *pchip; 805222Sksewell@umich.edu 815222Sksewell@umich.edu int intr_sum_type[Malta::Max_CPUs]; 825222Sksewell@umich.edu int ipi_pending[Malta::Max_CPUs]; 835222Sksewell@umich.edu 845222Sksewell@umich.edu public: 855222Sksewell@umich.edu /** 865222Sksewell@umich.edu * Constructor for the Malta Class. 875222Sksewell@umich.edu * @param name name of the object 885222Sksewell@umich.edu * @param s system the object belongs to 895222Sksewell@umich.edu * @param intctrl pointer to the interrupt controller 905222Sksewell@umich.edu */ 915222Sksewell@umich.edu typedef MaltaParams Params; 925222Sksewell@umich.edu Malta(const Params *p); 935222Sksewell@umich.edu 945222Sksewell@umich.edu /** 955222Sksewell@umich.edu * Return the interrupting frequency to MipsAccess 965222Sksewell@umich.edu * @return frequency of RTC interrupts 975222Sksewell@umich.edu */ 985222Sksewell@umich.edu virtual Tick intrFrequency(); 995222Sksewell@umich.edu 1005222Sksewell@umich.edu /** 1015222Sksewell@umich.edu * Cause the cpu to post a serial interrupt to the CPU. 1025222Sksewell@umich.edu */ 1035222Sksewell@umich.edu virtual void postConsoleInt(); 1045222Sksewell@umich.edu 1055222Sksewell@umich.edu /** 1065222Sksewell@umich.edu * Clear a posted CPU interrupt (id=55) 1075222Sksewell@umich.edu */ 1085222Sksewell@umich.edu virtual void clearConsoleInt(); 1095222Sksewell@umich.edu 1105222Sksewell@umich.edu /** 1115222Sksewell@umich.edu * Cause the chipset to post a cpi interrupt to the CPU. 1125222Sksewell@umich.edu */ 1135222Sksewell@umich.edu virtual void postPciInt(int line); 1145222Sksewell@umich.edu 1155222Sksewell@umich.edu /** 1165222Sksewell@umich.edu * Clear a posted PCI->CPU interrupt 1175222Sksewell@umich.edu */ 1185222Sksewell@umich.edu virtual void clearPciInt(int line); 1195222Sksewell@umich.edu 1205222Sksewell@umich.edu 1215222Sksewell@umich.edu virtual Addr pciToDma(Addr pciAddr) const; 1225222Sksewell@umich.edu 1236379Sgblack@eecs.umich.edu Addr 1246379Sgblack@eecs.umich.edu calcPciConfigAddr(int bus, int dev, int func) 1256379Sgblack@eecs.umich.edu { 1266379Sgblack@eecs.umich.edu panic("Need implementation\n"); 1276379Sgblack@eecs.umich.edu M5_DUMMY_RETURN 1286379Sgblack@eecs.umich.edu } 1296379Sgblack@eecs.umich.edu 1306379Sgblack@eecs.umich.edu Addr 1316379Sgblack@eecs.umich.edu calcPciIOAddr(Addr addr) 1326379Sgblack@eecs.umich.edu { 1336379Sgblack@eecs.umich.edu panic("Need implementation\n"); 1346379Sgblack@eecs.umich.edu M5_DUMMY_RETURN 1356379Sgblack@eecs.umich.edu } 1366379Sgblack@eecs.umich.edu 1376379Sgblack@eecs.umich.edu Addr 1386379Sgblack@eecs.umich.edu calcPciMemAddr(Addr addr) 1396379Sgblack@eecs.umich.edu { 1406379Sgblack@eecs.umich.edu panic("Need implementation\n"); 1416379Sgblack@eecs.umich.edu M5_DUMMY_RETURN 1426379Sgblack@eecs.umich.edu } 1435222Sksewell@umich.edu 1445222Sksewell@umich.edu /** 1455222Sksewell@umich.edu * Serialize this object to the given output stream. 1465222Sksewell@umich.edu * @param os The stream to serialize to. 1475222Sksewell@umich.edu */ 1485222Sksewell@umich.edu virtual void serialize(std::ostream &os); 1495222Sksewell@umich.edu 1505222Sksewell@umich.edu /** 1515222Sksewell@umich.edu * Reconstruct the state of this object from a checkpoint. 1525222Sksewell@umich.edu * @param cp The checkpoint use. 1535222Sksewell@umich.edu * @param section The section name of this object 1545222Sksewell@umich.edu */ 1555222Sksewell@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1565222Sksewell@umich.edu}; 1575222Sksewell@umich.edu 1585222Sksewell@umich.edu#endif // __DEV_MALTA_HH__ 159