malta.cc revision 6379:75d4aaf7dd54
110388SAndreas.Sandberg@ARM.com/*
210388SAndreas.Sandberg@ARM.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
310388SAndreas.Sandberg@ARM.com * All rights reserved.
410388SAndreas.Sandberg@ARM.com *
510388SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without
610388SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are
710388SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright
810388SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer;
910388SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright
1010388SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the
1110388SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution;
1210388SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its
1310388SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from
1410388SAndreas.Sandberg@ARM.com * this software without specific prior written permission.
1510388SAndreas.Sandberg@ARM.com *
1610388SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1710388SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1810388SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1910388SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2010388SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2110388SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2210388SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2310388SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2410388SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2510388SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2610388SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2710388SAndreas.Sandberg@ARM.com *
2810388SAndreas.Sandberg@ARM.com * Authors: Ali Saidi
2910388SAndreas.Sandberg@ARM.com *          Rick Strong
3010388SAndreas.Sandberg@ARM.com */
3110388SAndreas.Sandberg@ARM.com
3210388SAndreas.Sandberg@ARM.com/** @file
3310388SAndreas.Sandberg@ARM.com * Implementation of Malta platform.
3410388SAndreas.Sandberg@ARM.com */
3510388SAndreas.Sandberg@ARM.com
3610388SAndreas.Sandberg@ARM.com#include <deque>
3710388SAndreas.Sandberg@ARM.com#include <string>
3810388SAndreas.Sandberg@ARM.com#include <vector>
3910388SAndreas.Sandberg@ARM.com
4010388SAndreas.Sandberg@ARM.com#include "cpu/intr_control.hh"
4110388SAndreas.Sandberg@ARM.com#include "dev/mips/malta_cchip.hh"
4210388SAndreas.Sandberg@ARM.com#include "dev/mips/malta_pchip.hh"
4310388SAndreas.Sandberg@ARM.com#include "dev/mips/malta_io.hh"
4410388SAndreas.Sandberg@ARM.com#include "dev/mips/malta.hh"
4510388SAndreas.Sandberg@ARM.com#include "dev/terminal.hh"
4610388SAndreas.Sandberg@ARM.com#include "params/Malta.hh"
4710388SAndreas.Sandberg@ARM.com#include "sim/system.hh"
4810388SAndreas.Sandberg@ARM.com
4910388SAndreas.Sandberg@ARM.com
5010388SAndreas.Sandberg@ARM.comusing namespace std;
5110388SAndreas.Sandberg@ARM.comusing namespace TheISA;
5210388SAndreas.Sandberg@ARM.com
5310388SAndreas.Sandberg@ARM.comMalta::Malta(const Params *p)
5410388SAndreas.Sandberg@ARM.com    : Platform(p), system(p->system)
5510388SAndreas.Sandberg@ARM.com{
5610388SAndreas.Sandberg@ARM.com    // set the back pointer from the system to myself
5710388SAndreas.Sandberg@ARM.com    system->platform = this;
5810388SAndreas.Sandberg@ARM.com
5910388SAndreas.Sandberg@ARM.com    for (int i = 0; i < Malta::Max_CPUs; i++)
6010388SAndreas.Sandberg@ARM.com        intr_sum_type[i] = 0;
6110388SAndreas.Sandberg@ARM.com}
6210388SAndreas.Sandberg@ARM.com
6310388SAndreas.Sandberg@ARM.comTick
6410388SAndreas.Sandberg@ARM.comMalta::intrFrequency()
6510388SAndreas.Sandberg@ARM.com{
6610388SAndreas.Sandberg@ARM.com    return io->frequency();
6710388SAndreas.Sandberg@ARM.com}
6810388SAndreas.Sandberg@ARM.com
6910388SAndreas.Sandberg@ARM.comvoid
7010388SAndreas.Sandberg@ARM.comMalta::postConsoleInt()
7110388SAndreas.Sandberg@ARM.com{
7210388SAndreas.Sandberg@ARM.com    //see {Linux-src}/arch/mips/mips-boards/sim/sim_setup.c
7310388SAndreas.Sandberg@ARM.com    io->postIntr(0x10/*HW4*/);
7410388SAndreas.Sandberg@ARM.com}
7510388SAndreas.Sandberg@ARM.com
7610388SAndreas.Sandberg@ARM.comvoid
7710388SAndreas.Sandberg@ARM.comMalta::clearConsoleInt()
7810388SAndreas.Sandberg@ARM.com{
7910388SAndreas.Sandberg@ARM.com    //FIXME: implement clearConsoleInt()
8010388SAndreas.Sandberg@ARM.com    io->clearIntr(0x10/*HW4*/);
8110388SAndreas.Sandberg@ARM.com}
8210388SAndreas.Sandberg@ARM.com
8310388SAndreas.Sandberg@ARM.comvoid
8410388SAndreas.Sandberg@ARM.comMalta::postPciInt(int line)
8510388SAndreas.Sandberg@ARM.com{
8610388SAndreas.Sandberg@ARM.com    panic("Malta::postPciInt() has not been implemented.");
8710388SAndreas.Sandberg@ARM.com}
8810388SAndreas.Sandberg@ARM.com
8910388SAndreas.Sandberg@ARM.comvoid
9010388SAndreas.Sandberg@ARM.comMalta::clearPciInt(int line)
9110388SAndreas.Sandberg@ARM.com{
9210388SAndreas.Sandberg@ARM.com    panic("Malta::clearPciInt() has not been implemented.");
9310388SAndreas.Sandberg@ARM.com}
9410388SAndreas.Sandberg@ARM.com
9510388SAndreas.Sandberg@ARM.comAddr
9610388SAndreas.Sandberg@ARM.comMalta::pciToDma(Addr pciAddr) const
9710388SAndreas.Sandberg@ARM.com{
9810388SAndreas.Sandberg@ARM.com    panic("Malta::pciToDma() has not been implemented.");
9910388SAndreas.Sandberg@ARM.com}
10010388SAndreas.Sandberg@ARM.com
10110388SAndreas.Sandberg@ARM.comvoid
10210388SAndreas.Sandberg@ARM.comMalta::serialize(std::ostream &os)
10310388SAndreas.Sandberg@ARM.com{
10410388SAndreas.Sandberg@ARM.com    SERIALIZE_ARRAY(intr_sum_type, Malta::Max_CPUs);
10510388SAndreas.Sandberg@ARM.com}
10610388SAndreas.Sandberg@ARM.com
10710388SAndreas.Sandberg@ARM.comvoid
10810388SAndreas.Sandberg@ARM.comMalta::unserialize(Checkpoint *cp, const std::string &section)
10910388SAndreas.Sandberg@ARM.com{
11010388SAndreas.Sandberg@ARM.com    UNSERIALIZE_ARRAY(intr_sum_type, Malta::Max_CPUs);
11110388SAndreas.Sandberg@ARM.com}
11210388SAndreas.Sandberg@ARM.com
11310388SAndreas.Sandberg@ARM.comMalta *
11410388SAndreas.Sandberg@ARM.comMaltaParams::create()
11510388SAndreas.Sandberg@ARM.com{
11610388SAndreas.Sandberg@ARM.com    return new Malta(this);
11710388SAndreas.Sandberg@ARM.com}
11810388SAndreas.Sandberg@ARM.com