isa_fake.hh revision 3814
14486Sbinkertn@umich.edu/* 27897Shestness@cs.utexas.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 34486Sbinkertn@umich.edu * All rights reserved. 44486Sbinkertn@umich.edu * 54486Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 64486Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 74486Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94486Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 104486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 114486Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124486Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134486Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144486Sbinkertn@umich.edu * this software without specific prior written permission. 154486Sbinkertn@umich.edu * 164486Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486Sbinkertn@umich.edu * 284486Sbinkertn@umich.edu * Authors: Ali Saidi 297897Shestness@cs.utexas.edu */ 304486Sbinkertn@umich.edu 313102SN/A/** @file 326654Snate@binkert.org * Declaration of a fake device. 333102SN/A */ 343102SN/A 356654Snate@binkert.org#ifndef __ISA_FAKE_HH__ 368931Sandreas.hansson@arm.com#define __ISA_FAKE_HH__ 372212SN/A 389524SAndreas.Sandberg@ARM.com#include "base/range.hh" 399524SAndreas.Sandberg@ARM.com#include "dev/io_device.hh" 402902SN/A#include "dev/alpha/tsunami.hh" 418703Sandreas.hansson@arm.com#include "mem/packet.hh" 421783SN/A 439338SAndreas.Sandberg@arm.com#include <string> 448839Sandreas.hansson@arm.com 457673Snate@binkert.org/** 467673Snate@binkert.org * IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and 478597Ssteve.reinhardt@amd.com * rites. It is meant to be placed at an address range 488597Ssteve.reinhardt@amd.com * so that an mcheck doesn't occur when an os probes a piece of hw 498597Ssteve.reinhardt@amd.com * that doesn't exist (e.g. UARTs1-3), or catch requests in the memory system 508597Ssteve.reinhardt@amd.com * that have no responders.. 518597Ssteve.reinhardt@amd.com */ 528597Ssteve.reinhardt@amd.comclass IsaFake : public BasicPioDevice 539524SAndreas.Sandberg@ARM.com{ 548597Ssteve.reinhardt@amd.com public: 558597Ssteve.reinhardt@amd.com struct Params : public BasicPioDevice::Params 564859Snate@binkert.org { 578931Sandreas.hansson@arm.com Addr pio_size; 588931Sandreas.hansson@arm.com bool retBadAddr; 592902SN/A bool updateData; 609408Sandreas.hansson@arm.com uint8_t retData8; 619408Sandreas.hansson@arm.com uint16_t retData16; 629408Sandreas.hansson@arm.com uint32_t retData32; 639408Sandreas.hansson@arm.com uint64_t retData64; 649408Sandreas.hansson@arm.com std::string warnAccess; 659408Sandreas.hansson@arm.com }; 669814Sandreas.hansson@arm.com protected: 679814Sandreas.hansson@arm.com const Params *params() const { return (const Params*)_params; } 687914SBrad.Beckmann@amd.com uint8_t retData8; 698666SPrakash.Ramrakhyani@arm.com uint16_t retData16; 707914SBrad.Beckmann@amd.com uint32_t retData32; 717914SBrad.Beckmann@amd.com uint64_t retData64; 727914SBrad.Beckmann@amd.com 737914SBrad.Beckmann@amd.com 747914SBrad.Beckmann@amd.com public: 757914SBrad.Beckmann@amd.com /** 767914SBrad.Beckmann@amd.com * The constructor for Tsunmami Fake just registers itself with the MMU. 777914SBrad.Beckmann@amd.com * @param p params structure 787914SBrad.Beckmann@amd.com */ 797914SBrad.Beckmann@amd.com IsaFake(Params *p); 807914SBrad.Beckmann@amd.com 817914SBrad.Beckmann@amd.com /** 827914SBrad.Beckmann@amd.com * This read always returns -1. 838769Sgblack@eecs.umich.edu * @param pkt The memory request. 848769Sgblack@eecs.umich.edu * @param data Where to put the data. 858769Sgblack@eecs.umich.edu */ 868769Sgblack@eecs.umich.edu virtual Tick read(PacketPtr pkt); 878769Sgblack@eecs.umich.edu 888769Sgblack@eecs.umich.edu /** 8910037SARM gem5 Developers * All writes are simply ignored. 9010037SARM gem5 Developers * @param pkt The memory request. 91 * @param data the data to not write. 92 */ 93 virtual Tick write(PacketPtr pkt); 94}; 95 96#endif // __ISA_FAKE_HH__ 97