io_device.cc revision 2626
112653Sandreas.sandberg@arm.com/*
212653Sandreas.sandberg@arm.com * Copyright (c) 2006 The Regents of The University of Michigan
312653Sandreas.sandberg@arm.com * All rights reserved.
412653Sandreas.sandberg@arm.com *
512653Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without
612653Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are
712653Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright
812653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer;
912653Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright
1012653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the
1112653Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution;
1212653Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its
1312653Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from
1412653Sandreas.sandberg@arm.com * this software without specific prior written permission.
1512653Sandreas.sandberg@arm.com *
1612653Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1712653Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1812653Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1912653Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2012653Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2112653Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2212653Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2312653Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2412653Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2512653Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2612653Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2712653Sandreas.sandberg@arm.com */
2812653Sandreas.sandberg@arm.com
2912653Sandreas.sandberg@arm.com#include "dev/io_device.hh"
3012653Sandreas.sandberg@arm.com#include "sim/builder.hh"
3112653Sandreas.sandberg@arm.com
3212653Sandreas.sandberg@arm.com
3312653Sandreas.sandberg@arm.comPioPort::PioPort(PioDevice *dev, Platform *p)
3412653Sandreas.sandberg@arm.com        : device(dev), platform(p)
3512653Sandreas.sandberg@arm.com{ }
3612653Sandreas.sandberg@arm.com
3712653Sandreas.sandberg@arm.com
3812653Sandreas.sandberg@arm.comTick
3912653Sandreas.sandberg@arm.comPioPort::recvAtomic(Packet &pkt)
4012653Sandreas.sandberg@arm.com{
4112653Sandreas.sandberg@arm.com    return device->recvAtomic(pkt);
4212653Sandreas.sandberg@arm.com}
4312653Sandreas.sandberg@arm.com
4412653Sandreas.sandberg@arm.comvoid
4512653Sandreas.sandberg@arm.comPioPort::recvFunctional(Packet &pkt)
4612653Sandreas.sandberg@arm.com{
4712654Sandreas.sandberg@arm.com    device->recvAtomic(pkt);
4812653Sandreas.sandberg@arm.com}
4912653Sandreas.sandberg@arm.com
5012653Sandreas.sandberg@arm.comvoid
5112653Sandreas.sandberg@arm.comPioPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
5212654Sandreas.sandberg@arm.com{
5312653Sandreas.sandberg@arm.com    snoop.clear();
5412653Sandreas.sandberg@arm.com    device->addressRanges(resp);
5512654Sandreas.sandberg@arm.com}
5612654Sandreas.sandberg@arm.com
5712654Sandreas.sandberg@arm.com
5812654Sandreas.sandberg@arm.comPacket *
5912654Sandreas.sandberg@arm.comPioPort::recvRetry()
6012654Sandreas.sandberg@arm.com{
6112653Sandreas.sandberg@arm.com    Packet* pkt = transmitList.front();
6212653Sandreas.sandberg@arm.com    transmitList.pop_front();
6312653Sandreas.sandberg@arm.com    return pkt;
6412653Sandreas.sandberg@arm.com}
6512653Sandreas.sandberg@arm.com
6612653Sandreas.sandberg@arm.com
6712653Sandreas.sandberg@arm.comvoid
6812656Sandreas.sandberg@arm.comPioPort::SendEvent::process()
6912654Sandreas.sandberg@arm.com{
7012654Sandreas.sandberg@arm.com    if (port->Port::sendTiming(packet) == Success)
7112654Sandreas.sandberg@arm.com        return;
7212653Sandreas.sandberg@arm.com
7312653Sandreas.sandberg@arm.com    port->transmitList.push_back(&packet);
7412653Sandreas.sandberg@arm.com}
7512653Sandreas.sandberg@arm.com
76
77bool
78PioPort::recvTiming(Packet &pkt)
79{
80    device->recvAtomic(pkt);
81    sendTiming(pkt, pkt.time-pkt.req->getTime());
82    return Success;
83}
84
85PioDevice::~PioDevice()
86{
87    if (pioPort)
88        delete pioPort;
89}
90
91void
92PioDevice::init()
93{
94    if (!pioPort)
95        panic("Pio port not connected to anything!");
96    pioPort->sendStatusChange(Port::RangeChange);
97}
98
99void
100BasicPioDevice::addressRanges(AddrRangeList &range_list)
101{
102    assert(pioSize != 0);
103    range_list.clear();
104    range_list.push_back(RangeSize(pioAddr, pioSize));
105}
106
107
108DmaPort::DmaPort(DmaDevice *dev, Platform *p)
109        : device(dev), platform(p), pendingCount(0)
110{ }
111
112bool
113DmaPort::recvTiming(Packet &pkt)
114{
115    if (pkt.senderState) {
116        DmaReqState *state;
117        state = (DmaReqState*)pkt.senderState;
118        state->completionEvent->schedule(pkt.time - pkt.req->getTime());
119        delete pkt.req;
120        delete &pkt;
121    }  else {
122        delete pkt.req;
123        delete &pkt;
124    }
125
126    return Success;
127}
128
129DmaDevice::DmaDevice(Params *p)
130    : PioDevice(p), dmaPort(NULL)
131{ }
132
133void
134DmaPort::SendEvent::process()
135{
136    if (port->Port::sendTiming(packet) == Success)
137        return;
138
139    port->transmitList.push_back(&packet);
140}
141
142Packet *
143DmaPort::recvRetry()
144{
145    Packet* pkt = transmitList.front();
146    transmitList.pop_front();
147    return pkt;
148}
149void
150DmaPort::dmaAction(Command cmd, Addr addr, int size, Event *event,
151        uint8_t *data)
152{
153
154    assert(event);
155
156    int prevSize = 0;
157    Packet basePkt;
158    Request baseReq(false);
159
160    basePkt.flags = 0;
161    basePkt.coherence = NULL;
162    basePkt.senderState = NULL;
163    basePkt.dest = Packet::Broadcast;
164    basePkt.cmd = cmd;
165    basePkt.result = Unknown;
166    basePkt.req = NULL;
167//    baseReq.nicReq = true;
168    baseReq.setTime(curTick);
169
170    for (ChunkGenerator gen(addr, size, peerBlockSize());
171         !gen.done(); gen.next()) {
172            Packet *pkt = new Packet(basePkt);
173            Request *req = new Request(baseReq);
174            pkt->addr = gen.addr();
175            pkt->size = gen.size();
176            pkt->req = req;
177            pkt->req->setPaddr(pkt->addr);
178            pkt->req->setSize(pkt->size);
179            // Increment the data pointer on a write
180            if (data)
181                pkt->dataStatic(data + prevSize) ;
182            prevSize += pkt->size;
183            // Set the last bit of the dma as the final packet for this dma
184            // and set it's completion event.
185            if (prevSize == size) {
186                DmaReqState *state = new DmaReqState(event, true);
187
188                pkt->senderState = (void*)state;
189            }
190            assert(pendingCount >= 0);
191            pendingCount++;
192            sendDma(pkt);
193    }
194    // since this isn't getting used and we want a check to make sure that all
195    // packets had data in them at some point.
196    basePkt.dataStatic((uint8_t*)NULL);
197}
198
199
200void
201DmaPort::sendDma(Packet *pkt)
202{
203   // some kind of selction between access methods
204   // more work is going to have to be done to make
205   // switching actually work
206  /* MemState state = device->platform->system->memState;
207
208   if (state == Timing) {
209       if (sendTiming(pkt) == Failure)
210           transmitList.push_back(&packet);
211    } else if (state == Atomic) {*/
212       sendAtomic(*pkt);
213       if (pkt->senderState) {
214           DmaReqState *state = (DmaReqState*)pkt->senderState;
215           state->completionEvent->schedule(curTick + (pkt->time - pkt->req->getTime()) +1);
216       }
217       pendingCount--;
218       assert(pendingCount >= 0);
219       delete pkt->req;
220       delete pkt;
221
222/*   } else if (state == Functional) {
223       sendFunctional(pkt);
224       // Is this correct???
225       completionEvent->schedule(pkt.req->responseTime - pkt.req->requestTime);
226       completionEvent == NULL;
227   } else
228       panic("Unknown memory command state.");
229  */
230}
231
232DmaDevice::~DmaDevice()
233{
234    if (dmaPort)
235        delete dmaPort;
236}
237
238
239