intel_8254_timer.hh revision 5606
1/* 2 * Copyright (c) 2004, 2005 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator. 7 * 8 * Permission is granted to use, copy, create derivative works and 9 * redistribute this software and such derivative works for any 10 * purpose, so long as the copyright notice above, this grant of 11 * permission, and the disclaimer below appear in all copies made; and 12 * so long as the name of The University of Michigan is not used in 13 * any advertising or publicity pertaining to the use or distribution 14 * of this software without specific, written prior authorization. 15 * 16 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 17 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND 18 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER 19 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE 22 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 23 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 24 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 25 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 26 * DAMAGES. 27 * 28 * Authors: Ali G. Saidi 29 * Andrew L. Schultz 30 * Miguel J. Serrano 31 */ 32 33#ifndef __DEV_8254_HH__ 34#define __DEV_8254_HH__ 35 36#include <string> 37#include <iostream> 38 39#include "base/bitunion.hh" 40#include "sim/eventq.hh" 41#include "sim/host.hh" 42#include "sim/serialize.hh" 43 44/** Programmable Interval Timer (Intel 8254) */ 45class Intel8254Timer : public EventManager 46{ 47 BitUnion8(CtrlReg) 48 Bitfield<7, 6> sel; 49 Bitfield<5, 4> rw; 50 Bitfield<3, 1> mode; 51 Bitfield<0> bcd; 52 EndBitUnion(CtrlReg) 53 54 enum SelectVal { 55 SelectCounter0, 56 SelectCounter1, 57 SelectCounter2, 58 ReadBackCommand 59 }; 60 61 enum ReadWriteVal { 62 LatchCommand, 63 LsbOnly, 64 MsbOnly, 65 TwoPhase 66 }; 67 68 enum ModeVal { 69 InitTc, 70 OneShot, 71 RateGen, 72 SquareWave, 73 SoftwareStrobe, 74 HardwareStrobe 75 }; 76 77 /** Counter element for PIT */ 78 class Counter 79 { 80 /** Event for counter interrupt */ 81 class CounterEvent : public Event 82 { 83 private: 84 /** Pointer back to Counter */ 85 Counter* counter; 86 Tick interval; 87 88 public: 89 CounterEvent(Counter*); 90 91 /** Event process */ 92 virtual void process(); 93 94 /** Event description */ 95 virtual const char *description() const; 96 97 friend class Counter; 98 99 void setTo(int clocks); 100 }; 101 102 private: 103 std::string _name; 104 const std::string &name() const { return _name; } 105 106 CounterEvent event; 107 108 /** Current count value */ 109 uint16_t count; 110 111 /** Latched count */ 112 uint16_t latched_count; 113 114 /** Interrupt period */ 115 uint16_t period; 116 117 /** Current mode of operation */ 118 uint8_t mode; 119 120 /** Output goes high when the counter reaches zero */ 121 bool output_high; 122 123 /** State of the count latch */ 124 bool latch_on; 125 126 /** Set of values for read_byte and write_byte */ 127 enum {LSB, MSB}; 128 129 /** Determine which byte of a 16-bit count value to read/write */ 130 uint8_t read_byte, write_byte; 131 132 /** Pointer to container */ 133 Intel8254Timer *parent; 134 135 public: 136 Counter(Intel8254Timer *p, const std::string &name); 137 138 /** Latch the current count (if one is not already latched) */ 139 void latchCount(); 140 141 /** Set the read/write mode */ 142 void setRW(int rw_val); 143 144 /** Set operational mode */ 145 void setMode(int mode_val); 146 147 /** Set count encoding */ 148 void setBCD(int bcd_val); 149 150 /** Read a count byte */ 151 uint8_t read(); 152 153 /** Write a count byte */ 154 void write(const uint8_t data); 155 156 /** Is the output high? */ 157 bool outputHigh(); 158 159 /** 160 * Serialize this object to the given output stream. 161 * @param base The base name of the counter object. 162 * @param os The stream to serialize to. 163 */ 164 void serialize(const std::string &base, std::ostream &os); 165 166 /** 167 * Reconstruct the state of this object from a checkpoint. 168 * @param base The base name of the counter object. 169 * @param cp The checkpoint use. 170 * @param section The section name of this object 171 */ 172 void unserialize(const std::string &base, Checkpoint *cp, 173 const std::string §ion); 174 }; 175 176 private: 177 std::string _name; 178 const std::string &name() const { return _name; } 179 180 /** PIT has three seperate counters */ 181 Counter *counter[3]; 182 183 public: 184 /** Public way to access individual counters (avoid array accesses) */ 185 Counter counter0; 186 Counter counter1; 187 Counter counter2; 188 189 Intel8254Timer(EventManager *em, const std::string &name); 190 191 /** Write control word */ 192 void writeControl(const CtrlReg data); 193 194 /** 195 * Serialize this object to the given output stream. 196 * @param base The base name of the counter object. 197 * @param os The stream to serialize to. 198 */ 199 void serialize(const std::string &base, std::ostream &os); 200 201 /** 202 * Reconstruct the state of this object from a checkpoint. 203 * @param base The base name of the counter object. 204 * @param cp The checkpoint use. 205 * @param section The section name of this object 206 */ 207 void unserialize(const std::string &base, Checkpoint *cp, 208 const std::string §ion); 209}; 210 211#endif // __DEV_8254_HH__ 212