intel_8254_timer.hh revision 5642
16657SN/A/* 26657SN/A * Copyright (c) 2004, 2005 37567SBrad.Beckmann@amd.com * The Regents of The University of Michigan 46657SN/A * All Rights Reserved 56657SN/A * 66657SN/A * This code is part of the M5 simulator. 76657SN/A * 86657SN/A * Permission is granted to use, copy, create derivative works and 96657SN/A * redistribute this software and such derivative works for any 106657SN/A * purpose, so long as the copyright notice above, this grant of 116657SN/A * permission, and the disclaimer below appear in all copies made; and 126657SN/A * so long as the name of The University of Michigan is not used in 136657SN/A * any advertising or publicity pertaining to the use or distribution 146657SN/A * of this software without specific, written prior authorization. 156657SN/A * 166657SN/A * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 176657SN/A * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND 186657SN/A * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER 196657SN/A * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED 206657SN/A * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 216657SN/A * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE 226657SN/A * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 236657SN/A * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 246657SN/A * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 256657SN/A * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 266657SN/A * DAMAGES. 276657SN/A * 286657SN/A * Authors: Ali G. Saidi 296657SN/A * Andrew L. Schultz 306657SN/A * Miguel J. Serrano 317567SBrad.Beckmann@amd.com */ 327567SBrad.Beckmann@amd.com 336657SN/A#ifndef __DEV_8254_HH__ 347567SBrad.Beckmann@amd.com#define __DEV_8254_HH__ 357567SBrad.Beckmann@amd.com 367567SBrad.Beckmann@amd.com#include <string> 376657SN/A#include <iostream> 3810308Snilay@cs.wisc.edu 396657SN/A#include "base/bitunion.hh" 406657SN/A#include "sim/eventq.hh" 417567SBrad.Beckmann@amd.com#include "sim/host.hh" 4211025Snilay@cs.wisc.edu#include "sim/serialize.hh" 436657SN/A 447567SBrad.Beckmann@amd.com/** Programmable Interval Timer (Intel 8254) */ 457567SBrad.Beckmann@amd.comclass Intel8254Timer : public EventManager 467567SBrad.Beckmann@amd.com{ 477567SBrad.Beckmann@amd.com protected: 4811111Snilay@cs.wisc.edu BitUnion8(CtrlReg) 497567SBrad.Beckmann@amd.com Bitfield<7, 6> sel; 50 Bitfield<5, 4> rw; 51 Bitfield<3, 1> mode; 52 Bitfield<0> bcd; 53 EndBitUnion(CtrlReg) 54 55 enum SelectVal { 56 SelectCounter0, 57 SelectCounter1, 58 SelectCounter2, 59 ReadBackCommand 60 }; 61 62 enum ReadWriteVal { 63 LatchCommand, 64 LsbOnly, 65 MsbOnly, 66 TwoPhase 67 }; 68 69 enum ModeVal { 70 InitTc, 71 OneShot, 72 RateGen, 73 SquareWave, 74 SoftwareStrobe, 75 HardwareStrobe 76 }; 77 78 /** Counter element for PIT */ 79 class Counter 80 { 81 /** Event for counter interrupt */ 82 class CounterEvent : public Event 83 { 84 private: 85 /** Pointer back to Counter */ 86 Counter* counter; 87 Tick interval; 88 89 public: 90 CounterEvent(Counter*); 91 92 /** Event process */ 93 void process(); 94 95 /** Event description */ 96 virtual const char *description() const; 97 98 friend class Counter; 99 100 void setTo(int clocks); 101 }; 102 103 private: 104 std::string _name; 105 const std::string &name() const { return _name; } 106 107 unsigned int num; 108 109 CounterEvent event; 110 111 /** Current count value */ 112 uint16_t count; 113 114 /** Latched count */ 115 uint16_t latched_count; 116 117 /** Interrupt period */ 118 uint16_t period; 119 120 /** Current mode of operation */ 121 uint8_t mode; 122 123 /** Output goes high when the counter reaches zero */ 124 bool output_high; 125 126 /** State of the count latch */ 127 bool latch_on; 128 129 /** Set of values for read_byte and write_byte */ 130 enum {LSB, MSB}; 131 132 /** Determine which byte of a 16-bit count value to read/write */ 133 uint8_t read_byte, write_byte; 134 135 /** Pointer to container */ 136 Intel8254Timer *parent; 137 138 public: 139 Counter(Intel8254Timer *p, const std::string &name, unsigned int num); 140 141 /** Latch the current count (if one is not already latched) */ 142 void latchCount(); 143 144 /** Set the read/write mode */ 145 void setRW(int rw_val); 146 147 /** Set operational mode */ 148 void setMode(int mode_val); 149 150 /** Set count encoding */ 151 void setBCD(int bcd_val); 152 153 /** Read a count byte */ 154 uint8_t read(); 155 156 /** Write a count byte */ 157 void write(const uint8_t data); 158 159 /** Is the output high? */ 160 bool outputHigh(); 161 162 /** 163 * Serialize this object to the given output stream. 164 * @param base The base name of the counter object. 165 * @param os The stream to serialize to. 166 */ 167 void serialize(const std::string &base, std::ostream &os); 168 169 /** 170 * Reconstruct the state of this object from a checkpoint. 171 * @param base The base name of the counter object. 172 * @param cp The checkpoint use. 173 * @param section The section name of this object 174 */ 175 void unserialize(const std::string &base, Checkpoint *cp, 176 const std::string §ion); 177 }; 178 179 protected: 180 std::string _name; 181 const std::string &name() const { return _name; } 182 183 /** PIT has three seperate counters */ 184 Counter *counter[3]; 185 186 virtual void 187 counterInterrupt(unsigned int num) 188 { 189 DPRINTF(Intel8254Timer, "Timer interrupt from counter %d.\n", num); 190 } 191 192 public: 193 194 virtual 195 ~Intel8254Timer() 196 {} 197 198 Intel8254Timer(EventManager *em, const std::string &name, 199 Counter *counter0, Counter *counter1, Counter *counter2); 200 201 Intel8254Timer(EventManager *em, const std::string &name); 202 203 /** Write control word */ 204 void writeControl(const CtrlReg data); 205 206 uint8_t 207 readCounter(unsigned int num) 208 { 209 assert(num < 3); 210 return counter[num]->read(); 211 } 212 213 void 214 writeCounter(unsigned int num, const uint8_t data) 215 { 216 assert(num < 3); 217 counter[num]->write(data); 218 } 219 220 bool 221 outputHigh(unsigned int num) 222 { 223 assert(num < 3); 224 return counter[num]->outputHigh(); 225 } 226 227 /** 228 * Serialize this object to the given output stream. 229 * @param base The base name of the counter object. 230 * @param os The stream to serialize to. 231 */ 232 void serialize(const std::string &base, std::ostream &os); 233 234 /** 235 * Reconstruct the state of this object from a checkpoint. 236 * @param base The base name of the counter object. 237 * @param cp The checkpoint use. 238 * @param section The section name of this object 239 */ 240 void unserialize(const std::string &base, Checkpoint *cp, 241 const std::string §ion); 242}; 243 244#endif // __DEV_8254_HH__ 245