baddev.hh revision 909
12SN/A/*
21762SN/A * Copyright (c) 2004 The Regents of The University of Michigan
37534Ssteve.reinhardt@amd.com * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272SN/A */
282665Ssaidi@eecs.umich.edu
292665Ssaidi@eecs.umich.edu/* @file
302665Ssaidi@eecs.umich.edu * This devices just panics when touched. For example if you have a
312SN/A * kernel that touches the frame buffer which isn't allowed.
322SN/A */
332SN/A
342SN/A#ifndef __BADDEV_HH__
352SN/A#define __BADDEV_HH__
362SN/A
372SN/A#include "base/range.hh"
382SN/A#include "dev/io_device.hh"
392SN/A
405491Sgblack@eecs.umich.edu/**
415491Sgblack@eecs.umich.edu * BadDevice
422SN/A * This device just panics when accessed. It is supposed to warn
435491Sgblack@eecs.umich.edu * the user that the kernel they are running has unsupported
442SN/A * options (i.e. frame buffer)
452SN/A */
468737Skoansin.tan@gmail.comclass BadDevice : public PioDevice
474762Snate@binkert.org{
489342SAndreas.Sandberg@arm.com  private:
499356Snilay@cs.wisc.edu    Addr addr;
5056SN/A    static const Addr size = 0xf;
512SN/A
522797Sktlim@umich.edu    std::string devname;
532797Sktlim@umich.edu
542609SN/A  public:
559196SAndreas.Sandberg@arm.com     /**
562SN/A      * Constructor for the Baddev Class.
572SN/A      * @param name name of the object
582SN/A      * @param a base address of the write
599196SAndreas.Sandberg@arm.com      * @param mmu the memory controller
609196SAndreas.Sandberg@arm.com      * @param hier object to store parameters universal the device hierarchy
619196SAndreas.Sandberg@arm.com      * @param bus The bus that this device is attached to
629196SAndreas.Sandberg@arm.com      * @param devicename device that is not implemented
639196SAndreas.Sandberg@arm.com      */
649196SAndreas.Sandberg@arm.com    BadDevice(const std::string &name, Addr a, MemoryController *mmu,
659196SAndreas.Sandberg@arm.com              HierParams *hier, Bus *bus, const std::string &devicename);
669196SAndreas.Sandberg@arm.com
679196SAndreas.Sandberg@arm.com    /**
689196SAndreas.Sandberg@arm.com      * On a read event we just panic aand hopefully print a
699196SAndreas.Sandberg@arm.com      * meaningful error message.
709196SAndreas.Sandberg@arm.com      * @param req Contains the address to read from.
719196SAndreas.Sandberg@arm.com      * @param data A pointer to write the read data to.
729196SAndreas.Sandberg@arm.com      * @return The fault condition of the access.
739196SAndreas.Sandberg@arm.com      */
749196SAndreas.Sandberg@arm.com    virtual Fault read(MemReqPtr &req, uint8_t *data);
759196SAndreas.Sandberg@arm.com
769342SAndreas.Sandberg@arm.com    /**
779196SAndreas.Sandberg@arm.com      * On a write event we just panic aand hopefully print a
789196SAndreas.Sandberg@arm.com      * meaningful error message.
799196SAndreas.Sandberg@arm.com      * @param req Contains the address to write to.
809196SAndreas.Sandberg@arm.com      * @param data The data to write.
819196SAndreas.Sandberg@arm.com      * @return The fault condition of the access.
829196SAndreas.Sandberg@arm.com      */
839196SAndreas.Sandberg@arm.com    virtual Fault write(MemReqPtr &req, const uint8_t *data);
842SN/A
859342SAndreas.Sandberg@arm.com    /**
862SN/A     * Return how long this access will take.
872SN/A     * @param req the memory request to calcuate
882SN/A     * @return Tick when the request is done
892SN/A     */
909196SAndreas.Sandberg@arm.com    Tick cacheAccess(MemReqPtr &req);
912SN/A};
922SN/A
934762Snate@binkert.org#endif // __BADDEV_HH__
949196SAndreas.Sandberg@arm.com