vgic.hh revision 11174:5a9019db4a08 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Matt Evans
38 */
39
40
41/** @file
42 * Implementiation of a GIC-400 List Register-based VGIC interface.
43 * The VGIC is, in this implementation, completely separate from the GIC itself.
44 * Only a VIRQ line to the CPU and a PPI line to the GIC (for a HV maintenance IRQ)
45 * is required.
46 *
47 * The mode in which the List Registers may flag (via LR.HW) that a hardware EOI
48 * is to be performed is NOT supported.  (This requires tighter integration with
49 * the GIC.)
50 */
51
52#ifndef __DEV_ARM_VGIC_H__
53#define __DEV_ARM_VGIC_H__
54
55#include <algorithm>
56#include <array>
57
58#include "base/addr_range.hh"
59#include "base/bitunion.hh"
60#include "cpu/intr_control.hh"
61#include "dev/io_device.hh"
62#include "dev/platform.hh"
63#include "params/VGic.hh"
64
65class VGic : public PioDevice
66{
67  private:
68    static const int VGIC_CPU_MAX       = 256;
69    static const int NUM_LR             = 4;
70
71    static const int GICH_SIZE          = 0x200;
72    static const int GICH_REG_SIZE      = 0x2000;
73
74    static const int GICH_HCR           = 0x000;
75    static const int GICH_VTR           = 0x004;
76    static const int GICH_VMCR          = 0x008;
77    static const int GICH_MISR          = 0x010;
78    static const int GICH_EISR0         = 0x020;
79    static const int GICH_EISR1         = 0x024;
80    static const int GICH_ELSR0         = 0x030;
81    static const int GICH_ELSR1         = 0x034;
82    static const int GICH_APR0          = 0x0f0;
83    static const int GICH_LR0           = 0x100;
84    static const int GICH_LR1           = 0x104;
85    static const int GICH_LR2           = 0x108;
86    static const int GICH_LR3           = 0x10c;
87
88    static const int GICV_SIZE          = 0x2000;
89    static const int GICV_CTLR          = 0x000;
90    static const int GICV_PMR           = 0x004;
91    static const int GICV_BPR           = 0x008;
92    static const int GICV_IAR           = 0x00c;
93    static const int GICV_EOIR          = 0x010;
94    static const int GICV_RPR           = 0x014;
95    static const int GICV_HPPIR         = 0x018;
96    static const int GICV_ABPR          = 0x01c;
97    static const int GICV_AIAR          = 0x020;
98    static const int GICV_AEOIR         = 0x024;
99    static const int GICV_AHPPIR        = 0x028;
100    static const int GICV_APR0          = 0x0d0;
101    static const int GICV_IIDR          = 0x0fc;
102    static const int GICV_DIR           = 0x1000;
103
104    static const uint32_t LR_PENDING    = 1;
105    static const uint32_t LR_ACTIVE     = 2;
106
107    /** Event definition to post interrupt to CPU after a delay
108    */
109    class PostVIntEvent : public Event
110    {
111      private:
112        uint32_t cpu;
113        Platform *platform;
114      public:
115        PostVIntEvent( uint32_t c, Platform* p)
116            : cpu(c), platform(p)
117        { }
118        void process() { platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);}
119        const char *description() const { return "Post VInterrupt to CPU"; }
120    };
121
122    PostVIntEvent *postVIntEvent[VGIC_CPU_MAX];
123    bool        maintIntPosted[VGIC_CPU_MAX];
124    bool        vIntPosted[VGIC_CPU_MAX];
125
126    Platform *platform;
127    BaseGic *gic;
128
129    Addr vcpuAddr;
130    Addr hvAddr;
131    Tick pioDelay;
132    int maintInt;
133
134    BitUnion32(ListReg)
135    Bitfield<31> HW;
136    Bitfield<30> Grp1;
137    Bitfield<29,28> State;
138    Bitfield<27,23> Priority;
139    Bitfield<19> EOI;
140    Bitfield<12,10> CpuID;
141    Bitfield<9,0> VirtualID;
142    EndBitUnion(ListReg)
143
144    BitUnion32(HCR)
145    Bitfield<31,27> EOICount;
146    Bitfield<7> VGrp1DIE;
147    Bitfield<6> VGrp1EIE;
148    Bitfield<5> VGrp0DIE;
149    Bitfield<4> VGrp0EIE;
150    Bitfield<3> NPIE;
151    Bitfield<2> LRENPIE;
152    Bitfield<1> UIE;
153    Bitfield<0> En;
154    EndBitUnion(HCR)
155
156    BitUnion32(VCTLR)
157    Bitfield<9> EOImode;
158    Bitfield<4> CPBR;
159    Bitfield<3> FIQEn;
160    Bitfield<2> AckCtl;
161    Bitfield<1> EnGrp1;
162    Bitfield<0> En;     // This gets written to enable, not group 1.
163    EndBitUnion(VCTLR)
164
165    /* State per CPU.  EVERYTHING should be in this struct and simply replicated
166     * N times.
167     */
168    struct vcpuIntData : public Serializable {
169        vcpuIntData()
170            : vctrl(0), hcr(0), eisr(0), VMGrp0En(0), VMGrp1En(0),
171              VMAckCtl(0), VMFiqEn(0), VMCBPR(0), VEM(0), VMABP(0), VMBP(0),
172              VMPriMask(0)
173        {
174            std::fill(LR.begin(), LR.end(), 0);
175        }
176        virtual ~vcpuIntData() {}
177
178        std::array<ListReg, NUM_LR> LR;
179        VCTLR vctrl;
180
181        HCR hcr;
182        uint64_t eisr;
183
184        /* Host info, guest info (should be 100% accessible via GICH_* regs!) */
185        uint8_t VMGrp0En;
186        uint8_t VMGrp1En;
187        uint8_t VMAckCtl;
188        uint8_t VMFiqEn;
189        uint8_t VMCBPR;
190        uint8_t VEM;
191        uint8_t VMABP;
192        uint8_t VMBP;
193        uint8_t VMPriMask;
194
195        void serialize(CheckpointOut &cp) const override;
196        void unserialize(CheckpointIn &cp) override;
197    };
198
199    struct std::array<vcpuIntData, VGIC_CPU_MAX>  vcpuData;
200
201  public:
202   typedef VGicParams Params;
203   const Params *
204    params() const
205    {
206        return dynamic_cast<const Params *>(_params);
207    }
208    VGic(const Params *p);
209
210    AddrRangeList getAddrRanges() const override;
211
212    Tick read(PacketPtr pkt) override;
213    Tick write(PacketPtr pkt) override;
214
215    void serialize(CheckpointOut &cp) const override;
216    void unserialize(CheckpointIn &cp) override;
217
218  private:
219    Tick readVCpu(PacketPtr pkt);
220    Tick readCtrl(PacketPtr pkt);
221
222    Tick writeVCpu(PacketPtr pkt);
223    Tick writeCtrl(PacketPtr pkt);
224
225    void updateIntState(ContextID ctx_id);
226    uint32_t getMISR(struct vcpuIntData *vid);
227    void postVInt(uint32_t cpu, Tick when);
228    void unPostVInt(uint32_t cpu);
229    void postMaintInt(uint32_t cpu);
230    void unPostMaintInt(uint32_t cpu);
231
232    unsigned int lrPending(struct vcpuIntData *vid)
233    {
234        unsigned int pend = 0;
235        for (int i = 0; i < NUM_LR; i++) {
236            if (vid->LR[i].State & LR_PENDING)
237                pend++;
238        }
239        return pend;
240    }
241    unsigned int lrValid(struct vcpuIntData *vid)
242    {
243        unsigned int valid = 0;
244        for (int i = 0; i < NUM_LR; i++) {
245            if (vid->LR[i].State)
246                valid++;
247        }
248        return valid;
249    }
250
251    /** Returns LR index or -1 if none pending */
252    int findHighestPendingLR(struct vcpuIntData *vid)
253    {
254        unsigned int prio = 0xff;
255        int p = -1;
256        for (int i = 0; i < NUM_LR; i++) {
257            if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) {
258                p = i;
259                prio = vid->LR[i].Priority;
260            }
261        }
262        return p;
263    }
264
265    int findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu)
266    {
267        for (int i = 0; i < NUM_LR; i++) {
268            if (vid->LR[i].State &&
269                vid->LR[i].VirtualID == virq &&
270                vid->LR[i].CpuID == vcpu)
271                return i;
272        }
273        return -1;
274    }
275};
276
277#endif
278