vgic.hh revision 10037
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2013 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Matt Evans 3810037SARM gem5 Developers */ 3910037SARM gem5 Developers 4010037SARM gem5 Developers 4110037SARM gem5 Developers/** @file 4210037SARM gem5 Developers * Implementiation of a GIC-400 List Register-based VGIC interface. 4310037SARM gem5 Developers * The VGIC is, in this implementation, completely separate from the GIC itself. 4410037SARM gem5 Developers * Only a VIRQ line to the CPU and a PPI line to the GIC (for a HV maintenance IRQ) 4510037SARM gem5 Developers * is required. 4610037SARM gem5 Developers * 4710037SARM gem5 Developers * The mode in which the List Registers may flag (via LR.HW) that a hardware EOI 4810037SARM gem5 Developers * is to be performed is NOT supported. (This requires tighter integration with 4910037SARM gem5 Developers * the GIC.) 5010037SARM gem5 Developers */ 5110037SARM gem5 Developers 5210037SARM gem5 Developers#ifndef __DEV_ARM_VGIC_H__ 5310037SARM gem5 Developers#define __DEV_ARM_VGIC_H__ 5410037SARM gem5 Developers 5510037SARM gem5 Developers#include "base/addr_range.hh" 5610037SARM gem5 Developers#include "base/bitunion.hh" 5710037SARM gem5 Developers#include "cpu/intr_control.hh" 5810037SARM gem5 Developers#include "dev/io_device.hh" 5910037SARM gem5 Developers#include "dev/platform.hh" 6010037SARM gem5 Developers#include "params/VGic.hh" 6110037SARM gem5 Developers 6210037SARM gem5 Developersclass VGic : public PioDevice 6310037SARM gem5 Developers{ 6410037SARM gem5 Developers private: 6510037SARM gem5 Developers static const int VGIC_CPU_MAX = 256; 6610037SARM gem5 Developers static const int NUM_LR = 4; 6710037SARM gem5 Developers 6810037SARM gem5 Developers static const int GICH_SIZE = 0x200; 6910037SARM gem5 Developers static const int GICH_REG_SIZE = 0x2000; 7010037SARM gem5 Developers 7110037SARM gem5 Developers static const int GICH_HCR = 0x000; 7210037SARM gem5 Developers static const int GICH_VTR = 0x004; 7310037SARM gem5 Developers static const int GICH_VMCR = 0x008; 7410037SARM gem5 Developers static const int GICH_MISR = 0x010; 7510037SARM gem5 Developers static const int GICH_EISR0 = 0x020; 7610037SARM gem5 Developers static const int GICH_EISR1 = 0x024; 7710037SARM gem5 Developers static const int GICH_ELSR0 = 0x030; 7810037SARM gem5 Developers static const int GICH_ELSR1 = 0x034; 7910037SARM gem5 Developers static const int GICH_APR0 = 0x0f0; 8010037SARM gem5 Developers static const int GICH_LR0 = 0x100; 8110037SARM gem5 Developers static const int GICH_LR1 = 0x104; 8210037SARM gem5 Developers static const int GICH_LR2 = 0x108; 8310037SARM gem5 Developers static const int GICH_LR3 = 0x10c; 8410037SARM gem5 Developers 8510037SARM gem5 Developers static const int GICV_SIZE = 0x2000; 8610037SARM gem5 Developers static const int GICV_CTLR = 0x000; 8710037SARM gem5 Developers static const int GICV_PMR = 0x004; 8810037SARM gem5 Developers static const int GICV_BPR = 0x008; 8910037SARM gem5 Developers static const int GICV_IAR = 0x00c; 9010037SARM gem5 Developers static const int GICV_EOIR = 0x010; 9110037SARM gem5 Developers static const int GICV_RPR = 0x014; 9210037SARM gem5 Developers static const int GICV_HPPIR = 0x018; 9310037SARM gem5 Developers static const int GICV_ABPR = 0x01c; 9410037SARM gem5 Developers static const int GICV_AIAR = 0x020; 9510037SARM gem5 Developers static const int GICV_AEOIR = 0x024; 9610037SARM gem5 Developers static const int GICV_AHPPIR = 0x028; 9710037SARM gem5 Developers static const int GICV_APR0 = 0x0d0; 9810037SARM gem5 Developers static const int GICV_IIDR = 0x0fc; 9910037SARM gem5 Developers static const int GICV_DIR = 0x1000; 10010037SARM gem5 Developers 10110037SARM gem5 Developers static const uint32_t LR_PENDING = 1; 10210037SARM gem5 Developers static const uint32_t LR_ACTIVE = 2; 10310037SARM gem5 Developers 10410037SARM gem5 Developers /** Event definition to post interrupt to CPU after a delay 10510037SARM gem5 Developers */ 10610037SARM gem5 Developers class PostVIntEvent : public Event 10710037SARM gem5 Developers { 10810037SARM gem5 Developers private: 10910037SARM gem5 Developers uint32_t cpu; 11010037SARM gem5 Developers Platform *platform; 11110037SARM gem5 Developers public: 11210037SARM gem5 Developers PostVIntEvent( uint32_t c, Platform* p) 11310037SARM gem5 Developers : cpu(c), platform(p) 11410037SARM gem5 Developers { } 11510037SARM gem5 Developers void process() { platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);} 11610037SARM gem5 Developers const char *description() const { return "Post VInterrupt to CPU"; } 11710037SARM gem5 Developers }; 11810037SARM gem5 Developers 11910037SARM gem5 Developers PostVIntEvent *postVIntEvent[VGIC_CPU_MAX]; 12010037SARM gem5 Developers bool maintIntPosted[VGIC_CPU_MAX]; 12110037SARM gem5 Developers bool vIntPosted[VGIC_CPU_MAX]; 12210037SARM gem5 Developers 12310037SARM gem5 Developers Platform *platform; 12410037SARM gem5 Developers BaseGic *gic; 12510037SARM gem5 Developers 12610037SARM gem5 Developers Addr vcpuAddr; 12710037SARM gem5 Developers Addr hvAddr; 12810037SARM gem5 Developers Tick pioDelay; 12910037SARM gem5 Developers int maintInt; 13010037SARM gem5 Developers 13110037SARM gem5 Developers BitUnion32(ListReg) 13210037SARM gem5 Developers Bitfield<31> HW; 13310037SARM gem5 Developers Bitfield<30> Grp1; 13410037SARM gem5 Developers Bitfield<29,28> State; 13510037SARM gem5 Developers Bitfield<27,23> Priority; 13610037SARM gem5 Developers Bitfield<19> EOI; 13710037SARM gem5 Developers Bitfield<12,10> CpuID; 13810037SARM gem5 Developers Bitfield<9,0> VirtualID; 13910037SARM gem5 Developers EndBitUnion(ListReg) 14010037SARM gem5 Developers 14110037SARM gem5 Developers BitUnion32(HCR) 14210037SARM gem5 Developers Bitfield<31,27> EOICount; 14310037SARM gem5 Developers Bitfield<7> VGrp1DIE; 14410037SARM gem5 Developers Bitfield<6> VGrp1EIE; 14510037SARM gem5 Developers Bitfield<5> VGrp0DIE; 14610037SARM gem5 Developers Bitfield<4> VGrp0EIE; 14710037SARM gem5 Developers Bitfield<3> NPIE; 14810037SARM gem5 Developers Bitfield<2> LRENPIE; 14910037SARM gem5 Developers Bitfield<1> UIE; 15010037SARM gem5 Developers Bitfield<0> En; 15110037SARM gem5 Developers EndBitUnion(HCR) 15210037SARM gem5 Developers 15310037SARM gem5 Developers BitUnion32(VCTLR) 15410037SARM gem5 Developers Bitfield<9> EOImode; 15510037SARM gem5 Developers Bitfield<4> CPBR; 15610037SARM gem5 Developers Bitfield<3> FIQEn; 15710037SARM gem5 Developers Bitfield<2> AckCtl; 15810037SARM gem5 Developers Bitfield<1> EnGrp1; 15910037SARM gem5 Developers Bitfield<0> En; // This gets written to enable, not group 1. 16010037SARM gem5 Developers EndBitUnion(VCTLR) 16110037SARM gem5 Developers 16210037SARM gem5 Developers /* State per CPU. EVERYTHING should be in this struct and simply replicated 16310037SARM gem5 Developers * N times. 16410037SARM gem5 Developers */ 16510037SARM gem5 Developers struct vcpuIntData { 16610037SARM gem5 Developers ListReg LR[NUM_LR]; 16710037SARM gem5 Developers VCTLR vctrl; 16810037SARM gem5 Developers 16910037SARM gem5 Developers HCR hcr; 17010037SARM gem5 Developers uint64_t eisr; 17110037SARM gem5 Developers 17210037SARM gem5 Developers /* Host info, guest info (should be 100% accessible via GICH_* regs!) */ 17310037SARM gem5 Developers uint8_t VMGrp0En; 17410037SARM gem5 Developers uint8_t VMGrp1En; 17510037SARM gem5 Developers uint8_t VMAckCtl; 17610037SARM gem5 Developers uint8_t VMFiqEn; 17710037SARM gem5 Developers uint8_t VMCBPR; 17810037SARM gem5 Developers uint8_t VEM; 17910037SARM gem5 Developers uint8_t VMABP; 18010037SARM gem5 Developers uint8_t VMBP; 18110037SARM gem5 Developers uint8_t VMPriMask; 18210037SARM gem5 Developers }; 18310037SARM gem5 Developers 18410037SARM gem5 Developers struct vcpuIntData vcpuData[VGIC_CPU_MAX]; 18510037SARM gem5 Developers 18610037SARM gem5 Developers public: 18710037SARM gem5 Developers typedef VGicParams Params; 18810037SARM gem5 Developers const Params * 18910037SARM gem5 Developers params() const 19010037SARM gem5 Developers { 19110037SARM gem5 Developers return dynamic_cast<const Params *>(_params); 19210037SARM gem5 Developers } 19310037SARM gem5 Developers VGic(const Params *p); 19410037SARM gem5 Developers 19510037SARM gem5 Developers virtual AddrRangeList getAddrRanges() const; 19610037SARM gem5 Developers 19710037SARM gem5 Developers virtual Tick read(PacketPtr pkt); 19810037SARM gem5 Developers virtual Tick write(PacketPtr pkt); 19910037SARM gem5 Developers 20010037SARM gem5 Developers virtual void serialize(std::ostream &os); 20110037SARM gem5 Developers virtual void unserialize(Checkpoint *cp, const std::string §ion); 20210037SARM gem5 Developers 20310037SARM gem5 Developers private: 20410037SARM gem5 Developers Tick readVCpu(PacketPtr pkt); 20510037SARM gem5 Developers Tick readCtrl(PacketPtr pkt); 20610037SARM gem5 Developers 20710037SARM gem5 Developers Tick writeVCpu(PacketPtr pkt); 20810037SARM gem5 Developers Tick writeCtrl(PacketPtr pkt); 20910037SARM gem5 Developers 21010037SARM gem5 Developers void updateIntState(int ctx_id); 21110037SARM gem5 Developers uint32_t getMISR(struct vcpuIntData *vid); 21210037SARM gem5 Developers void postVInt(uint32_t cpu, Tick when); 21310037SARM gem5 Developers void unPostVInt(uint32_t cpu); 21410037SARM gem5 Developers void postMaintInt(uint32_t cpu); 21510037SARM gem5 Developers void unPostMaintInt(uint32_t cpu); 21610037SARM gem5 Developers 21710037SARM gem5 Developers unsigned int lrPending(struct vcpuIntData *vid) 21810037SARM gem5 Developers { 21910037SARM gem5 Developers unsigned int pend = 0; 22010037SARM gem5 Developers for (int i = 0; i < NUM_LR; i++) { 22110037SARM gem5 Developers if (vid->LR[i].State & LR_PENDING) 22210037SARM gem5 Developers pend++; 22310037SARM gem5 Developers } 22410037SARM gem5 Developers return pend; 22510037SARM gem5 Developers } 22610037SARM gem5 Developers unsigned int lrValid(struct vcpuIntData *vid) 22710037SARM gem5 Developers { 22810037SARM gem5 Developers unsigned int valid = 0; 22910037SARM gem5 Developers for (int i = 0; i < NUM_LR; i++) { 23010037SARM gem5 Developers if (vid->LR[i].State) 23110037SARM gem5 Developers valid++; 23210037SARM gem5 Developers } 23310037SARM gem5 Developers return valid; 23410037SARM gem5 Developers } 23510037SARM gem5 Developers 23610037SARM gem5 Developers /** Returns LR index or -1 if none pending */ 23710037SARM gem5 Developers int findHighestPendingLR(struct vcpuIntData *vid) 23810037SARM gem5 Developers { 23910037SARM gem5 Developers unsigned int prio = 0xff; 24010037SARM gem5 Developers int p = -1; 24110037SARM gem5 Developers for (int i = 0; i < NUM_LR; i++) { 24210037SARM gem5 Developers if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) { 24310037SARM gem5 Developers p = i; 24410037SARM gem5 Developers prio = vid->LR[i].Priority; 24510037SARM gem5 Developers } 24610037SARM gem5 Developers } 24710037SARM gem5 Developers return p; 24810037SARM gem5 Developers } 24910037SARM gem5 Developers 25010037SARM gem5 Developers int findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu) 25110037SARM gem5 Developers { 25210037SARM gem5 Developers for (int i = 0; i < NUM_LR; i++) { 25310037SARM gem5 Developers if (vid->LR[i].State && 25410037SARM gem5 Developers vid->LR[i].VirtualID == virq && 25510037SARM gem5 Developers vid->LR[i].CpuID == vcpu) 25610037SARM gem5 Developers return i; 25710037SARM gem5 Developers } 25810037SARM gem5 Developers return -1; 25910037SARM gem5 Developers } 26010037SARM gem5 Developers}; 26110037SARM gem5 Developers 26210037SARM gem5 Developers#endif 263