vgic.cc revision 10905
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2013 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Matt Evans 3810037SARM gem5 Developers */ 3910037SARM gem5 Developers 4010037SARM gem5 Developers#include "base/trace.hh" 4110037SARM gem5 Developers#include "debug/Checkpoint.hh" 4210037SARM gem5 Developers#include "debug/VGIC.hh" 4310037SARM gem5 Developers#include "dev/arm/base_gic.hh" 4410037SARM gem5 Developers#include "dev/arm/vgic.hh" 4510037SARM gem5 Developers#include "dev/terminal.hh" 4610037SARM gem5 Developers#include "mem/packet.hh" 4710037SARM gem5 Developers#include "mem/packet_access.hh" 4810037SARM gem5 Developers 4910037SARM gem5 DevelopersVGic::VGic(const Params *p) 5010037SARM gem5 Developers : PioDevice(p), platform(p->platform), gic(p->gic), vcpuAddr(p->vcpu_addr), 5110037SARM gem5 Developers hvAddr(p->hv_addr), pioDelay(p->pio_delay), 5210037SARM gem5 Developers maintInt(p->ppint) 5310037SARM gem5 Developers{ 5410037SARM gem5 Developers for (int x = 0; x < VGIC_CPU_MAX; x++) { 5510037SARM gem5 Developers postVIntEvent[x] = new PostVIntEvent(x, p->platform); 5610037SARM gem5 Developers maintIntPosted[x] = false; 5710037SARM gem5 Developers vIntPosted[x] = false; 5810037SARM gem5 Developers } 5910037SARM gem5 Developers assert(sys->numRunningContexts() <= VGIC_CPU_MAX); 6010037SARM gem5 Developers} 6110037SARM gem5 Developers 6210037SARM gem5 DevelopersTick 6310037SARM gem5 DevelopersVGic::read(PacketPtr pkt) 6410037SARM gem5 Developers{ 6510037SARM gem5 Developers Addr addr = pkt->getAddr(); 6610037SARM gem5 Developers 6710037SARM gem5 Developers if (addr >= vcpuAddr && addr < vcpuAddr + GICV_SIZE) 6810037SARM gem5 Developers return readVCpu(pkt); 6910037SARM gem5 Developers else if (addr >= hvAddr && addr < hvAddr + GICH_REG_SIZE) 7010037SARM gem5 Developers return readCtrl(pkt); 7110037SARM gem5 Developers else 7210037SARM gem5 Developers panic("Read to unknown address %#x\n", pkt->getAddr()); 7310037SARM gem5 Developers} 7410037SARM gem5 Developers 7510037SARM gem5 DevelopersTick 7610037SARM gem5 DevelopersVGic::write(PacketPtr pkt) 7710037SARM gem5 Developers{ 7810037SARM gem5 Developers Addr addr = pkt->getAddr(); 7910037SARM gem5 Developers 8010037SARM gem5 Developers if (addr >= vcpuAddr && addr < vcpuAddr + GICV_SIZE) 8110037SARM gem5 Developers return writeVCpu(pkt); 8210037SARM gem5 Developers else if (addr >= hvAddr && addr < hvAddr + GICH_REG_SIZE) 8310037SARM gem5 Developers return writeCtrl(pkt); 8410037SARM gem5 Developers else 8510037SARM gem5 Developers panic("Write to unknown address %#x\n", pkt->getAddr()); 8610037SARM gem5 Developers} 8710037SARM gem5 Developers 8810037SARM gem5 DevelopersTick 8910037SARM gem5 DevelopersVGic::readVCpu(PacketPtr pkt) 9010037SARM gem5 Developers{ 9110037SARM gem5 Developers Addr daddr = pkt->getAddr() - vcpuAddr; 9210037SARM gem5 Developers 9310037SARM gem5 Developers int ctx_id = pkt->req->contextId(); 9410037SARM gem5 Developers assert(ctx_id < VGIC_CPU_MAX); 9510037SARM gem5 Developers struct vcpuIntData *vid = &vcpuData[ctx_id]; 9610037SARM gem5 Developers 9710037SARM gem5 Developers DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr); 9810037SARM gem5 Developers 9910037SARM gem5 Developers switch (daddr) { 10010037SARM gem5 Developers case GICV_CTLR: 10110037SARM gem5 Developers pkt->set<uint32_t>(vid->vctrl); 10210037SARM gem5 Developers break; 10310037SARM gem5 Developers case GICV_IAR: { 10410037SARM gem5 Developers int i = findHighestPendingLR(vid); 10510037SARM gem5 Developers if (i < 0 || !vid->vctrl.En) { 10610037SARM gem5 Developers pkt->set<uint32_t>(1023); // "No int" marker 10710037SARM gem5 Developers } else { 10810037SARM gem5 Developers ListReg *lr = &vid->LR[i]; 10910037SARM gem5 Developers 11010037SARM gem5 Developers pkt->set<uint32_t>(lr->VirtualID | 11110037SARM gem5 Developers (((int)lr->CpuID) << 10)); 11210037SARM gem5 Developers // We don't support auto-EOI of HW interrupts via real GIC! 11310037SARM gem5 Developers // Fortunately, KVM doesn't use this. How about Xen...? Ulp! 11410037SARM gem5 Developers if (lr->HW) 11510037SARM gem5 Developers panic("VGIC does not support 'HW' List Register feature (LR %#x)!\n", 11610037SARM gem5 Developers *lr); 11710037SARM gem5 Developers lr->State = LR_ACTIVE; 11810037SARM gem5 Developers DPRINTF(VGIC, "Consumed interrupt %d (cpu%d) from LR%d (EOI%d)\n", 11910037SARM gem5 Developers lr->VirtualID, lr->CpuID, i, lr->EOI); 12010037SARM gem5 Developers } 12110037SARM gem5 Developers } break; 12210037SARM gem5 Developers default: 12310037SARM gem5 Developers panic("VGIC VCPU read of bad address %#x\n", daddr); 12410037SARM gem5 Developers } 12510037SARM gem5 Developers 12610037SARM gem5 Developers updateIntState(ctx_id); 12710037SARM gem5 Developers 12810037SARM gem5 Developers pkt->makeAtomicResponse(); 12910037SARM gem5 Developers return pioDelay; 13010037SARM gem5 Developers} 13110037SARM gem5 Developers 13210037SARM gem5 DevelopersTick 13310037SARM gem5 DevelopersVGic::readCtrl(PacketPtr pkt) 13410037SARM gem5 Developers{ 13510037SARM gem5 Developers Addr daddr = pkt->getAddr() - hvAddr; 13610037SARM gem5 Developers 13710037SARM gem5 Developers int ctx_id = pkt->req->contextId(); 13810037SARM gem5 Developers 13910037SARM gem5 Developers DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr); 14010037SARM gem5 Developers 14110037SARM gem5 Developers /* Munge the address: 0-0xfff is the usual space banked by requester CPU. 14210037SARM gem5 Developers * Anything > that is 0x200-sized slices of 'per CPU' regs. 14310037SARM gem5 Developers */ 14410037SARM gem5 Developers if (daddr & ~0x1ff) { 14510037SARM gem5 Developers ctx_id = (daddr >> 9); 14610037SARM gem5 Developers if (ctx_id > 8) 14710037SARM gem5 Developers panic("VGIC: Weird unbanked hv ctrl address %#x!\n", daddr); 14810037SARM gem5 Developers daddr &= ~0x1ff; 14910037SARM gem5 Developers } 15010037SARM gem5 Developers assert(ctx_id < VGIC_CPU_MAX); 15110037SARM gem5 Developers struct vcpuIntData *vid = &vcpuData[ctx_id]; 15210037SARM gem5 Developers 15310037SARM gem5 Developers switch (daddr) { 15410037SARM gem5 Developers case GICH_HCR: 15510037SARM gem5 Developers pkt->set<uint32_t>(vid->hcr); 15610037SARM gem5 Developers break; 15710037SARM gem5 Developers 15810037SARM gem5 Developers case GICH_VTR: 15910037SARM gem5 Developers pkt->set<uint32_t>(0x44000000 | (NUM_LR - 1)); 16010037SARM gem5 Developers break; 16110037SARM gem5 Developers 16210037SARM gem5 Developers case GICH_VMCR: 16310037SARM gem5 Developers pkt->set<uint32_t>( 16410037SARM gem5 Developers ((uint32_t)vid->VMPriMask << 27) | 16510037SARM gem5 Developers ((uint32_t)vid->VMBP << 21) | 16610037SARM gem5 Developers ((uint32_t)vid->VMABP << 18) | 16710037SARM gem5 Developers ((uint32_t)vid->VEM << 9) | 16810037SARM gem5 Developers ((uint32_t)vid->VMCBPR << 4) | 16910037SARM gem5 Developers ((uint32_t)vid->VMFiqEn << 3) | 17010037SARM gem5 Developers ((uint32_t)vid->VMAckCtl << 2) | 17110037SARM gem5 Developers ((uint32_t)vid->VMGrp1En << 1) | 17210037SARM gem5 Developers ((uint32_t)vid->VMGrp0En << 0) 17310037SARM gem5 Developers ); 17410037SARM gem5 Developers break; 17510037SARM gem5 Developers 17610037SARM gem5 Developers case GICH_MISR: 17710037SARM gem5 Developers pkt->set<uint32_t>(getMISR(vid)); 17810037SARM gem5 Developers break; 17910037SARM gem5 Developers 18010037SARM gem5 Developers case GICH_EISR0: 18110037SARM gem5 Developers pkt->set<uint32_t>(vid->eisr & 0xffffffff); 18210037SARM gem5 Developers break; 18310037SARM gem5 Developers 18410037SARM gem5 Developers case GICH_EISR1: 18510037SARM gem5 Developers pkt->set<uint32_t>(vid->eisr >> 32); 18610037SARM gem5 Developers break; 18710037SARM gem5 Developers 18810037SARM gem5 Developers case GICH_ELSR0: { 18910037SARM gem5 Developers uint32_t bm = 0; 19010037SARM gem5 Developers for (int i = 0; i < ((NUM_LR < 32) ? NUM_LR : 32); i++) { 19110037SARM gem5 Developers if (!vid->LR[i].State) 19210037SARM gem5 Developers bm |= 1 << i; 19310037SARM gem5 Developers } 19410037SARM gem5 Developers pkt->set<uint32_t>(bm); 19510037SARM gem5 Developers } break; 19610037SARM gem5 Developers 19710037SARM gem5 Developers case GICH_ELSR1: { 19810037SARM gem5 Developers uint32_t bm = 0; 19910037SARM gem5 Developers for (int i = 32; i < NUM_LR; i++) { 20010037SARM gem5 Developers if (!vid->LR[i].State) 20110037SARM gem5 Developers bm |= 1 << (i-32); 20210037SARM gem5 Developers } 20310037SARM gem5 Developers pkt->set<uint32_t>(bm); 20410037SARM gem5 Developers } break; 20510037SARM gem5 Developers 20610037SARM gem5 Developers case GICH_APR0: 20710037SARM gem5 Developers warn_once("VGIC GICH_APR read!\n"); 20810037SARM gem5 Developers pkt->set<uint32_t>(0); 20910037SARM gem5 Developers break; 21010037SARM gem5 Developers 21110037SARM gem5 Developers case GICH_LR0: 21210037SARM gem5 Developers case GICH_LR1: 21310037SARM gem5 Developers case GICH_LR2: 21410037SARM gem5 Developers case GICH_LR3: 21510037SARM gem5 Developers pkt->set<uint32_t>(vid->LR[(daddr - GICH_LR0) >> 2]); 21610037SARM gem5 Developers break; 21710037SARM gem5 Developers 21810037SARM gem5 Developers default: 21910037SARM gem5 Developers panic("VGIC HVCtrl read of bad address %#x\n", daddr); 22010037SARM gem5 Developers } 22110037SARM gem5 Developers 22210037SARM gem5 Developers pkt->makeAtomicResponse(); 22310037SARM gem5 Developers return pioDelay; 22410037SARM gem5 Developers} 22510037SARM gem5 Developers 22610037SARM gem5 DevelopersTick 22710037SARM gem5 DevelopersVGic::writeVCpu(PacketPtr pkt) 22810037SARM gem5 Developers{ 22910037SARM gem5 Developers Addr daddr = pkt->getAddr() - vcpuAddr; 23010037SARM gem5 Developers 23110037SARM gem5 Developers int ctx_id = pkt->req->contextId(); 23210037SARM gem5 Developers assert(ctx_id < VGIC_CPU_MAX); 23310037SARM gem5 Developers struct vcpuIntData *vid = &vcpuData[ctx_id]; 23410037SARM gem5 Developers 23510037SARM gem5 Developers DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get<uint32_t>()); 23610037SARM gem5 Developers 23710037SARM gem5 Developers switch (daddr) { 23810037SARM gem5 Developers case GICV_CTLR: 23910037SARM gem5 Developers vid->vctrl = pkt->get<uint32_t>(); 24010037SARM gem5 Developers break; 24110037SARM gem5 Developers case GICV_PMR: 24210037SARM gem5 Developers vid->VMPriMask = pkt->get<uint32_t>(); 24310037SARM gem5 Developers break; 24410037SARM gem5 Developers case GICV_EOIR: { 24510037SARM gem5 Developers // We don't handle the split EOI-then-DIR mode. Linux (guest) 24610037SARM gem5 Developers // doesn't need it though. 24710037SARM gem5 Developers assert(!vid->vctrl.EOImode); 24810037SARM gem5 Developers uint32_t w = pkt->get<uint32_t>(); 24910037SARM gem5 Developers unsigned int virq = w & 0x3ff; 25010037SARM gem5 Developers unsigned int vcpu = (w >> 10) & 7; 25110037SARM gem5 Developers int i = findLRForVIRQ(vid, virq, vcpu); 25210037SARM gem5 Developers if (i < 0) { 25310037SARM gem5 Developers DPRINTF(VGIC, "EOIR: No LR for irq %d(cpu%d)\n", virq, vcpu); 25410037SARM gem5 Developers } else { 25510037SARM gem5 Developers DPRINTF(VGIC, "EOIR: Found LR%d for irq %d(cpu%d)\n", i, virq, vcpu); 25610037SARM gem5 Developers ListReg *lr = &vid->LR[i]; 25710037SARM gem5 Developers lr->State = 0; 25810037SARM gem5 Developers // Maintenance interrupt -- via eisr -- is flagged when 25910037SARM gem5 Developers // LRs have EOI=1 and State=INVALID! 26010037SARM gem5 Developers } 26110037SARM gem5 Developers } break; 26210037SARM gem5 Developers default: 26310037SARM gem5 Developers panic("VGIC VCPU write %#x to unk address %#x\n", pkt->get<uint32_t>(), daddr); 26410037SARM gem5 Developers } 26510037SARM gem5 Developers 26610037SARM gem5 Developers // This updates the EISRs and flags IRQs: 26710037SARM gem5 Developers updateIntState(ctx_id); 26810037SARM gem5 Developers 26910037SARM gem5 Developers pkt->makeAtomicResponse(); 27010037SARM gem5 Developers return pioDelay; 27110037SARM gem5 Developers} 27210037SARM gem5 Developers 27310037SARM gem5 DevelopersTick 27410037SARM gem5 DevelopersVGic::writeCtrl(PacketPtr pkt) 27510037SARM gem5 Developers{ 27610037SARM gem5 Developers Addr daddr = pkt->getAddr() - hvAddr; 27710037SARM gem5 Developers 27810037SARM gem5 Developers int ctx_id = pkt->req->contextId(); 27910037SARM gem5 Developers 28010037SARM gem5 Developers DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>()); 28110037SARM gem5 Developers 28210037SARM gem5 Developers /* Munge the address: 0-0xfff is the usual space banked by requester CPU. 28310037SARM gem5 Developers * Anything > that is 0x200-sized slices of 'per CPU' regs. 28410037SARM gem5 Developers */ 28510037SARM gem5 Developers if (daddr & ~0x1ff) { 28610037SARM gem5 Developers ctx_id = (daddr >> 9); 28710037SARM gem5 Developers if (ctx_id > 8) 28810037SARM gem5 Developers panic("VGIC: Weird unbanked hv ctrl address %#x!\n", daddr); 28910037SARM gem5 Developers daddr &= ~0x1ff; 29010037SARM gem5 Developers } 29110037SARM gem5 Developers assert(ctx_id < VGIC_CPU_MAX); 29210037SARM gem5 Developers struct vcpuIntData *vid = &vcpuData[ctx_id]; 29310037SARM gem5 Developers 29410037SARM gem5 Developers switch (daddr) { 29510037SARM gem5 Developers case GICH_HCR: 29610037SARM gem5 Developers vid->hcr = pkt->get<uint32_t>(); 29710037SARM gem5 Developers // update int state 29810037SARM gem5 Developers break; 29910037SARM gem5 Developers 30010037SARM gem5 Developers case GICH_VMCR: { 30110037SARM gem5 Developers uint32_t d = pkt->get<uint32_t>(); 30210037SARM gem5 Developers vid->VMPriMask = d >> 27; 30310037SARM gem5 Developers vid->VMBP = (d >> 21) & 7; 30410037SARM gem5 Developers vid->VMABP = (d >> 18) & 7; 30510037SARM gem5 Developers vid->VEM = (d >> 9) & 1; 30610037SARM gem5 Developers vid->VMCBPR = (d >> 4) & 1; 30710037SARM gem5 Developers vid->VMFiqEn = (d >> 3) & 1; 30810037SARM gem5 Developers vid->VMAckCtl = (d >> 2) & 1; 30910037SARM gem5 Developers vid->VMGrp1En = (d >> 1) & 1; 31010037SARM gem5 Developers vid->VMGrp0En = d & 1; 31110037SARM gem5 Developers } break; 31210037SARM gem5 Developers 31310037SARM gem5 Developers case GICH_APR0: 31410037SARM gem5 Developers warn_once("VGIC GICH_APR0 written, ignored\n"); 31510037SARM gem5 Developers break; 31610037SARM gem5 Developers 31710037SARM gem5 Developers case GICH_LR0: 31810037SARM gem5 Developers case GICH_LR1: 31910037SARM gem5 Developers case GICH_LR2: 32010037SARM gem5 Developers case GICH_LR3: 32110037SARM gem5 Developers vid->LR[(daddr - GICH_LR0) >> 2] = pkt->get<uint32_t>(); 32210037SARM gem5 Developers // update int state 32310037SARM gem5 Developers break; 32410037SARM gem5 Developers 32510037SARM gem5 Developers default: 32610037SARM gem5 Developers panic("VGIC HVCtrl write to bad address %#x\n", daddr); 32710037SARM gem5 Developers } 32810037SARM gem5 Developers 32910037SARM gem5 Developers updateIntState(ctx_id); 33010037SARM gem5 Developers 33110037SARM gem5 Developers pkt->makeAtomicResponse(); 33210037SARM gem5 Developers return pioDelay; 33310037SARM gem5 Developers} 33410037SARM gem5 Developers 33510037SARM gem5 Developers 33610037SARM gem5 Developersuint32_t 33710037SARM gem5 DevelopersVGic::getMISR(struct vcpuIntData *vid) 33810037SARM gem5 Developers{ 33910037SARM gem5 Developers return (!!vid->hcr.VGrp1DIE && !vid->VMGrp1En ? 0x80 : 0) | 34010037SARM gem5 Developers (!!vid->hcr.VGrp1EIE && vid->VMGrp1En ? 0x40 : 0) | 34110037SARM gem5 Developers (!!vid->hcr.VGrp0DIE && !vid->VMGrp0En ? 0x20 : 0) | 34210037SARM gem5 Developers (!!vid->hcr.VGrp0EIE && vid->VMGrp0En ? 0x10 : 0) | 34310037SARM gem5 Developers (!!vid->hcr.NPIE && !lrPending(vid) ? 0x08 : 0) | 34410037SARM gem5 Developers (!!vid->hcr.LRENPIE && vid->hcr.EOICount ? 0x04 : 0) | 34510037SARM gem5 Developers (!!vid->hcr.UIE && lrValid(vid) <= 1 ? 0x02 : 0) | 34610037SARM gem5 Developers (vid->eisr ? 0x01 : 0); 34710037SARM gem5 Developers} 34810037SARM gem5 Developers 34910037SARM gem5 Developersvoid 35010037SARM gem5 DevelopersVGic::postVInt(uint32_t cpu, Tick when) 35110037SARM gem5 Developers{ 35210037SARM gem5 Developers DPRINTF(VGIC, "Posting VIRQ to %d\n", cpu); 35310037SARM gem5 Developers if (!(postVIntEvent[cpu]->scheduled())) 35410037SARM gem5 Developers eventq->schedule(postVIntEvent[cpu], when); 35510037SARM gem5 Developers} 35610037SARM gem5 Developers 35710037SARM gem5 Developersvoid 35810037SARM gem5 DevelopersVGic::unPostVInt(uint32_t cpu) 35910037SARM gem5 Developers{ 36010037SARM gem5 Developers DPRINTF(VGIC, "Unposting VIRQ to %d\n", cpu); 36110037SARM gem5 Developers platform->intrctrl->clear(cpu, ArmISA::INT_VIRT_IRQ, 0); 36210037SARM gem5 Developers} 36310037SARM gem5 Developers 36410037SARM gem5 Developersvoid 36510037SARM gem5 DevelopersVGic::postMaintInt(uint32_t cpu) 36610037SARM gem5 Developers{ 36710037SARM gem5 Developers DPRINTF(VGIC, "Posting maintenance PPI to GIC/cpu%d\n", cpu); 36810037SARM gem5 Developers // Linux DT configures this as Level. 36910037SARM gem5 Developers gic->sendPPInt(maintInt, cpu); 37010037SARM gem5 Developers} 37110037SARM gem5 Developers 37210037SARM gem5 Developersvoid 37310037SARM gem5 DevelopersVGic::unPostMaintInt(uint32_t cpu) 37410037SARM gem5 Developers{ 37510037SARM gem5 Developers DPRINTF(VGIC, "Unposting maintenance PPI to GIC/cpu%d\n", cpu); 37610037SARM gem5 Developers gic->clearPPInt(maintInt, cpu); 37710037SARM gem5 Developers} 37810037SARM gem5 Developers 37910037SARM gem5 Developers/* Update state (in general); something concerned with ctx_id has changed. 38010037SARM gem5 Developers * This may raise a maintenance interrupt. 38110037SARM gem5 Developers */ 38210037SARM gem5 Developersvoid 38310037SARM gem5 DevelopersVGic::updateIntState(int ctx_id) 38410037SARM gem5 Developers{ 38510037SARM gem5 Developers // @todo This should update APRs! 38610037SARM gem5 Developers 38710037SARM gem5 Developers // Build EISR contents: 38810037SARM gem5 Developers // (Cached so that regs can read them without messing about again) 38910037SARM gem5 Developers struct vcpuIntData *tvid = &vcpuData[ctx_id]; 39010037SARM gem5 Developers 39110037SARM gem5 Developers tvid->eisr = 0; 39210037SARM gem5 Developers for (int i = 0; i < NUM_LR; i++) { 39310037SARM gem5 Developers if (!tvid->LR[i].State && tvid->LR[i].EOI) { 39410037SARM gem5 Developers tvid->eisr |= 1 << i; 39510037SARM gem5 Developers } 39610037SARM gem5 Developers } 39710037SARM gem5 Developers 39810037SARM gem5 Developers assert(sys->numRunningContexts() <= VGIC_CPU_MAX); 39910037SARM gem5 Developers for (int i = 0; i < sys->numRunningContexts(); i++) { 40010037SARM gem5 Developers struct vcpuIntData *vid = &vcpuData[i]; 40110037SARM gem5 Developers // Are any LRs active that weren't before? 40210037SARM gem5 Developers if (!vIntPosted[i]) { 40310037SARM gem5 Developers if (lrPending(vid) && vid->vctrl.En) { 40410037SARM gem5 Developers vIntPosted[i] = true; 40510037SARM gem5 Developers postVInt(i, curTick() + 1); 40610037SARM gem5 Developers } 40710037SARM gem5 Developers } else if (!lrPending(vid)) { 40810037SARM gem5 Developers vIntPosted[i] = false; 40910037SARM gem5 Developers unPostVInt(i); 41010037SARM gem5 Developers } 41110037SARM gem5 Developers 41210037SARM gem5 Developers // Any maintenance ints to send? 41310037SARM gem5 Developers if (!maintIntPosted[i]) { 41410037SARM gem5 Developers if (vid->hcr.En && getMISR(vid)) { 41510037SARM gem5 Developers maintIntPosted[i] = true; 41610037SARM gem5 Developers postMaintInt(i); 41710037SARM gem5 Developers } 41810037SARM gem5 Developers } else { 41910037SARM gem5 Developers if (!vid->hcr.En || !getMISR(vid)) { 42010037SARM gem5 Developers unPostMaintInt(i); 42110037SARM gem5 Developers maintIntPosted[i] = false; 42210037SARM gem5 Developers } 42310037SARM gem5 Developers } 42410037SARM gem5 Developers } 42510037SARM gem5 Developers} 42610037SARM gem5 Developers 42710037SARM gem5 DevelopersAddrRangeList 42810037SARM gem5 DevelopersVGic::getAddrRanges() const 42910037SARM gem5 Developers{ 43010037SARM gem5 Developers AddrRangeList ranges; 43110037SARM gem5 Developers ranges.push_back(RangeSize(hvAddr, GICH_REG_SIZE)); 43210037SARM gem5 Developers ranges.push_back(RangeSize(vcpuAddr, GICV_SIZE)); 43310037SARM gem5 Developers return ranges; 43410037SARM gem5 Developers} 43510037SARM gem5 Developers 43610037SARM gem5 Developersvoid 43710905Sandreas.sandberg@arm.comVGic::serialize(CheckpointOut &cp) const 43810037SARM gem5 Developers{ 43910037SARM gem5 Developers Tick interrupt_time[VGIC_CPU_MAX]; 44010037SARM gem5 Developers for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) { 44110037SARM gem5 Developers interrupt_time[cpu] = 0; 44210037SARM gem5 Developers if (postVIntEvent[cpu]->scheduled()) { 44310037SARM gem5 Developers interrupt_time[cpu] = postVIntEvent[cpu]->when(); 44410037SARM gem5 Developers } 44510037SARM gem5 Developers } 44610037SARM gem5 Developers 44710037SARM gem5 Developers DPRINTF(Checkpoint, "Serializing VGIC\n"); 44810037SARM gem5 Developers 44910037SARM gem5 Developers SERIALIZE_ARRAY(interrupt_time, VGIC_CPU_MAX); 45010037SARM gem5 Developers SERIALIZE_ARRAY(maintIntPosted, VGIC_CPU_MAX); 45110037SARM gem5 Developers SERIALIZE_ARRAY(vIntPosted, VGIC_CPU_MAX); 45210037SARM gem5 Developers SERIALIZE_SCALAR(vcpuAddr); 45310037SARM gem5 Developers SERIALIZE_SCALAR(hvAddr); 45410037SARM gem5 Developers SERIALIZE_SCALAR(pioDelay); 45510037SARM gem5 Developers SERIALIZE_SCALAR(maintInt); 45610037SARM gem5 Developers 45710905Sandreas.sandberg@arm.com for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) 45810905Sandreas.sandberg@arm.com vcpuData[cpu].serializeSection(cp, csprintf("vcpuData%d", cpu)); 45910905Sandreas.sandberg@arm.com} 46010037SARM gem5 Developers 46110905Sandreas.sandberg@arm.comvoid 46210905Sandreas.sandberg@arm.comVGic::vcpuIntData::serialize(CheckpointOut &cp) const 46310905Sandreas.sandberg@arm.com{ 46410905Sandreas.sandberg@arm.com uint32_t vctrl_val = vctrl; 46510905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(vctrl_val); 46610905Sandreas.sandberg@arm.com uint32_t hcr_val = hcr; 46710905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(hcr_val); 46810905Sandreas.sandberg@arm.com uint64_t eisr_val = eisr; 46910905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(eisr_val); 47010905Sandreas.sandberg@arm.com uint8_t VMGrp0En_val = VMGrp0En; 47110905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMGrp0En_val); 47210905Sandreas.sandberg@arm.com uint8_t VMGrp1En_val = VMGrp1En; 47310905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMGrp1En_val); 47410905Sandreas.sandberg@arm.com uint8_t VMAckCtl_val = VMAckCtl; 47510905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMAckCtl_val); 47610905Sandreas.sandberg@arm.com uint8_t VMFiqEn_val = VMFiqEn; 47710905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMFiqEn_val); 47810905Sandreas.sandberg@arm.com uint8_t VMCBPR_val = VMCBPR; 47910905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMCBPR_val); 48010905Sandreas.sandberg@arm.com uint8_t VEM_val = VEM; 48110905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VEM_val); 48210905Sandreas.sandberg@arm.com uint8_t VMABP_val = VMABP; 48310905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMABP_val); 48410905Sandreas.sandberg@arm.com uint8_t VMBP_val = VMBP; 48510905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMBP_val); 48610905Sandreas.sandberg@arm.com uint8_t VMPriMask_val = VMPriMask; 48710905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(VMPriMask_val); 48810905Sandreas.sandberg@arm.com 48910905Sandreas.sandberg@arm.com for (int i = 0; i < NUM_LR; i++) { 49010905Sandreas.sandberg@arm.com ScopedCheckpointSection sec_lr(cp, csprintf("LR%d", i)); 49110905Sandreas.sandberg@arm.com paramOut(cp, "lr", LR[i]); 49210037SARM gem5 Developers } 49310037SARM gem5 Developers} 49410037SARM gem5 Developers 49510905Sandreas.sandberg@arm.comvoid VGic::unserialize(CheckpointIn &cp) 49610037SARM gem5 Developers{ 49710037SARM gem5 Developers DPRINTF(Checkpoint, "Unserializing Arm GIC\n"); 49810037SARM gem5 Developers 49910037SARM gem5 Developers Tick interrupt_time[VGIC_CPU_MAX]; 50010037SARM gem5 Developers UNSERIALIZE_ARRAY(interrupt_time, VGIC_CPU_MAX); 50110037SARM gem5 Developers for (uint32_t cpu = 0; cpu < VGIC_CPU_MAX; cpu++) { 50210037SARM gem5 Developers if (interrupt_time[cpu]) 50310037SARM gem5 Developers schedule(postVIntEvent[cpu], interrupt_time[cpu]); 50410037SARM gem5 Developers 50510905Sandreas.sandberg@arm.com vcpuData[cpu].unserializeSection(cp, csprintf("vcpuData%d", cpu)); 50610037SARM gem5 Developers } 50710037SARM gem5 Developers UNSERIALIZE_ARRAY(maintIntPosted, VGIC_CPU_MAX); 50810037SARM gem5 Developers UNSERIALIZE_ARRAY(vIntPosted, VGIC_CPU_MAX); 50910037SARM gem5 Developers UNSERIALIZE_SCALAR(vcpuAddr); 51010037SARM gem5 Developers UNSERIALIZE_SCALAR(hvAddr); 51110037SARM gem5 Developers UNSERIALIZE_SCALAR(pioDelay); 51210037SARM gem5 Developers UNSERIALIZE_SCALAR(maintInt); 51310037SARM gem5 Developers} 51410037SARM gem5 Developers 51510905Sandreas.sandberg@arm.comvoid 51610905Sandreas.sandberg@arm.comVGic::vcpuIntData::unserialize(CheckpointIn &cp) 51710905Sandreas.sandberg@arm.com{ 51810905Sandreas.sandberg@arm.com paramIn(cp, "vctrl_val", vctrl); 51910905Sandreas.sandberg@arm.com paramIn(cp, "hcr_val", hcr); 52010905Sandreas.sandberg@arm.com paramIn(cp, "eisr_val", eisr); 52110905Sandreas.sandberg@arm.com paramIn(cp, "VMGrp0En_val", VMGrp0En); 52210905Sandreas.sandberg@arm.com paramIn(cp, "VMGrp1En_val", VMGrp1En); 52310905Sandreas.sandberg@arm.com paramIn(cp, "VMAckCtl_val", VMAckCtl); 52410905Sandreas.sandberg@arm.com paramIn(cp, "VMFiqEn_val", VMFiqEn); 52510905Sandreas.sandberg@arm.com paramIn(cp, "VMCBPR_val", VMCBPR); 52610905Sandreas.sandberg@arm.com paramIn(cp, "VEM_val", VEM); 52710905Sandreas.sandberg@arm.com paramIn(cp, "VMABP_val", VMABP); 52810905Sandreas.sandberg@arm.com paramIn(cp, "VMPriMask_val", VMPriMask); 52910905Sandreas.sandberg@arm.com 53010905Sandreas.sandberg@arm.com for (int i = 0; i < NUM_LR; i++) { 53110905Sandreas.sandberg@arm.com ScopedCheckpointSection sec_lr(cp, csprintf("LR%d", i)); 53210905Sandreas.sandberg@arm.com paramIn(cp, "lr", LR[i]); 53310905Sandreas.sandberg@arm.com } 53410905Sandreas.sandberg@arm.com} 53510905Sandreas.sandberg@arm.com 53610037SARM gem5 DevelopersVGic * 53710037SARM gem5 DevelopersVGicParams::create() 53810037SARM gem5 Developers{ 53910037SARM gem5 Developers return new VGic(this); 54010037SARM gem5 Developers} 541