timer_cpulocal.cc revision 12086
18512Sgeoffrey.blake@arm.com/* 29545Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 38512Sgeoffrey.blake@arm.com * All rights reserved 48512Sgeoffrey.blake@arm.com * 58512Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68512Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78512Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88512Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98512Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108512Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118512Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128512Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138512Sgeoffrey.blake@arm.com * 148512Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 158512Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 168512Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 178512Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 188512Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 198512Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 208512Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 218512Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 228512Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 238512Sgeoffrey.blake@arm.com * this software without specific prior written permission. 248512Sgeoffrey.blake@arm.com * 258512Sgeoffrey.blake@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 268512Sgeoffrey.blake@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 278512Sgeoffrey.blake@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 288512Sgeoffrey.blake@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 298512Sgeoffrey.blake@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 308512Sgeoffrey.blake@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 318512Sgeoffrey.blake@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 328512Sgeoffrey.blake@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 338512Sgeoffrey.blake@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 348512Sgeoffrey.blake@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 358512Sgeoffrey.blake@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 368512Sgeoffrey.blake@arm.com * 378512Sgeoffrey.blake@arm.com * Authors: Ali Saidi 388512Sgeoffrey.blake@arm.com * Geoffrey Blake 398512Sgeoffrey.blake@arm.com */ 408512Sgeoffrey.blake@arm.com 4111793Sbrandon.potter@amd.com#include "dev/arm/timer_cpulocal.hh" 4211793Sbrandon.potter@amd.com 438512Sgeoffrey.blake@arm.com#include "base/intmath.hh" 448512Sgeoffrey.blake@arm.com#include "base/trace.hh" 458512Sgeoffrey.blake@arm.com#include "debug/Checkpoint.hh" 468512Sgeoffrey.blake@arm.com#include "debug/Timer.hh" 479525SAndreas.Sandberg@ARM.com#include "dev/arm/base_gic.hh" 488512Sgeoffrey.blake@arm.com#include "mem/packet.hh" 498512Sgeoffrey.blake@arm.com#include "mem/packet_access.hh" 508512Sgeoffrey.blake@arm.com 518512Sgeoffrey.blake@arm.comCpuLocalTimer::CpuLocalTimer(Params *p) 529808Sstever@gmail.com : BasicPioDevice(p, 0x38), gic(p->gic) 538512Sgeoffrey.blake@arm.com{ 548512Sgeoffrey.blake@arm.com // Initialize the timer registers for each per cpu timer 558512Sgeoffrey.blake@arm.com for (int i = 0; i < CPU_MAX; i++) { 568512Sgeoffrey.blake@arm.com std::stringstream oss; 578512Sgeoffrey.blake@arm.com oss << name() << ".timer" << i; 588512Sgeoffrey.blake@arm.com localTimer[i]._name = oss.str(); 598512Sgeoffrey.blake@arm.com localTimer[i].parent = this; 608512Sgeoffrey.blake@arm.com localTimer[i].intNumTimer = p->int_num_timer; 618512Sgeoffrey.blake@arm.com localTimer[i].intNumWatchdog = p->int_num_watchdog; 628512Sgeoffrey.blake@arm.com localTimer[i].cpuNum = i; 638512Sgeoffrey.blake@arm.com } 648512Sgeoffrey.blake@arm.com} 658512Sgeoffrey.blake@arm.com 668512Sgeoffrey.blake@arm.comCpuLocalTimer::Timer::Timer() 678512Sgeoffrey.blake@arm.com : timerControl(0x0), watchdogControl(0x0), rawIntTimer(false), rawIntWatchdog(false), 688512Sgeoffrey.blake@arm.com rawResetWatchdog(false), watchdogDisableReg(0x0), pendingIntTimer(false), pendingIntWatchdog(false), 6912086Sspwilson2@wisc.edu timerLoadValue(0x0), watchdogLoadValue(0x0), 7012086Sspwilson2@wisc.edu timerZeroEvent([this]{ timerAtZero(); }, name()), 7112086Sspwilson2@wisc.edu watchdogZeroEvent([this]{ watchdogAtZero(); }, name()) 728512Sgeoffrey.blake@arm.com{ 738512Sgeoffrey.blake@arm.com} 748512Sgeoffrey.blake@arm.com 758512Sgeoffrey.blake@arm.comTick 768512Sgeoffrey.blake@arm.comCpuLocalTimer::read(PacketPtr pkt) 778512Sgeoffrey.blake@arm.com{ 788512Sgeoffrey.blake@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 798512Sgeoffrey.blake@arm.com assert(pkt->getSize() == 4); 808512Sgeoffrey.blake@arm.com Addr daddr = pkt->getAddr() - pioAddr; 8111005Sandreas.sandberg@arm.com ContextID cpu_id = pkt->req->contextId(); 828512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr); 838512Sgeoffrey.blake@arm.com assert(cpu_id >= 0); 848512Sgeoffrey.blake@arm.com assert(cpu_id < CPU_MAX); 858512Sgeoffrey.blake@arm.com 868512Sgeoffrey.blake@arm.com if (daddr < Timer::Size) 878512Sgeoffrey.blake@arm.com localTimer[cpu_id].read(pkt, daddr); 888512Sgeoffrey.blake@arm.com else 898512Sgeoffrey.blake@arm.com panic("Tried to read CpuLocalTimer at offset %#x that doesn't exist\n", daddr); 908512Sgeoffrey.blake@arm.com pkt->makeAtomicResponse(); 918512Sgeoffrey.blake@arm.com return pioDelay; 928512Sgeoffrey.blake@arm.com} 938512Sgeoffrey.blake@arm.com 948512Sgeoffrey.blake@arm.com 958512Sgeoffrey.blake@arm.comvoid 968512Sgeoffrey.blake@arm.comCpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr) 978512Sgeoffrey.blake@arm.com{ 988512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr); 998512Sgeoffrey.blake@arm.com Tick time; 1008512Sgeoffrey.blake@arm.com 1018512Sgeoffrey.blake@arm.com switch(daddr) { 1028512Sgeoffrey.blake@arm.com case TimerLoadReg: 1038512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(timerLoadValue); 1048512Sgeoffrey.blake@arm.com break; 1058512Sgeoffrey.blake@arm.com case TimerCounterReg: 1068512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Event schedule for timer %d, clock=%d, prescale=%d\n", 1079545Sandreas.hansson@arm.com timerZeroEvent.when(), parent->clockPeriod(), 1089545Sandreas.hansson@arm.com timerControl.prescalar); 1098512Sgeoffrey.blake@arm.com time = timerZeroEvent.when() - curTick(); 1109545Sandreas.hansson@arm.com time = time / parent->clockPeriod() / 1119545Sandreas.hansson@arm.com power(16, timerControl.prescalar); 1128512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- returning counter at %d\n", time); 1138512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(time); 1148512Sgeoffrey.blake@arm.com break; 1158512Sgeoffrey.blake@arm.com case TimerControlReg: 1168512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(timerControl); 1178512Sgeoffrey.blake@arm.com break; 1188512Sgeoffrey.blake@arm.com case TimerIntStatusReg: 1198512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(rawIntTimer); 1208512Sgeoffrey.blake@arm.com break; 1218512Sgeoffrey.blake@arm.com case WatchdogLoadReg: 1228512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(watchdogLoadValue); 1238512Sgeoffrey.blake@arm.com break; 1248512Sgeoffrey.blake@arm.com case WatchdogCounterReg: 1259545Sandreas.hansson@arm.com DPRINTF(Timer, 1269545Sandreas.hansson@arm.com "Event schedule for watchdog %d, clock=%d, prescale=%d\n", 1279545Sandreas.hansson@arm.com watchdogZeroEvent.when(), parent->clockPeriod(), 1289545Sandreas.hansson@arm.com watchdogControl.prescalar); 1298512Sgeoffrey.blake@arm.com time = watchdogZeroEvent.when() - curTick(); 1309545Sandreas.hansson@arm.com time = time / parent->clockPeriod() / 1319545Sandreas.hansson@arm.com power(16, watchdogControl.prescalar); 1328512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- returning counter at %d\n", time); 1338512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(time); 1348512Sgeoffrey.blake@arm.com break; 1358512Sgeoffrey.blake@arm.com case WatchdogControlReg: 1368512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(watchdogControl); 1378512Sgeoffrey.blake@arm.com break; 1388512Sgeoffrey.blake@arm.com case WatchdogIntStatusReg: 1398512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(rawIntWatchdog); 1408512Sgeoffrey.blake@arm.com break; 1418512Sgeoffrey.blake@arm.com case WatchdogResetStatusReg: 1428512Sgeoffrey.blake@arm.com pkt->set<uint32_t>(rawResetWatchdog); 1438512Sgeoffrey.blake@arm.com break; 1448512Sgeoffrey.blake@arm.com case WatchdogDisableReg: 1458512Sgeoffrey.blake@arm.com panic("Tried to read from WatchdogDisableRegister\n"); 1468512Sgeoffrey.blake@arm.com break; 1478512Sgeoffrey.blake@arm.com default: 1488512Sgeoffrey.blake@arm.com panic("Tried to read CpuLocalTimer at offset %#x\n", daddr); 1498512Sgeoffrey.blake@arm.com break; 1508512Sgeoffrey.blake@arm.com } 1518512Sgeoffrey.blake@arm.com} 1528512Sgeoffrey.blake@arm.com 1538512Sgeoffrey.blake@arm.comTick 1548512Sgeoffrey.blake@arm.comCpuLocalTimer::write(PacketPtr pkt) 1558512Sgeoffrey.blake@arm.com{ 1568512Sgeoffrey.blake@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1578512Sgeoffrey.blake@arm.com assert(pkt->getSize() == 4); 1588512Sgeoffrey.blake@arm.com Addr daddr = pkt->getAddr() - pioAddr; 15911005Sandreas.sandberg@arm.com ContextID cpu_id = pkt->req->contextId(); 1608512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr); 1618512Sgeoffrey.blake@arm.com assert(cpu_id >= 0); 1628512Sgeoffrey.blake@arm.com assert(cpu_id < CPU_MAX); 1638512Sgeoffrey.blake@arm.com 1648512Sgeoffrey.blake@arm.com if (daddr < Timer::Size) 1658512Sgeoffrey.blake@arm.com localTimer[cpu_id].write(pkt, daddr); 1668512Sgeoffrey.blake@arm.com else 1678512Sgeoffrey.blake@arm.com panic("Tried to write CpuLocalTimer at offset %#x that doesn't exist\n", daddr); 1688512Sgeoffrey.blake@arm.com pkt->makeAtomicResponse(); 1698512Sgeoffrey.blake@arm.com return pioDelay; 1708512Sgeoffrey.blake@arm.com} 1718512Sgeoffrey.blake@arm.com 1728512Sgeoffrey.blake@arm.comvoid 1738512Sgeoffrey.blake@arm.comCpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr) 1748512Sgeoffrey.blake@arm.com{ 1758512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr); 1768512Sgeoffrey.blake@arm.com bool old_enable; 1778512Sgeoffrey.blake@arm.com bool old_wd_mode; 1788512Sgeoffrey.blake@arm.com uint32_t old_val; 1798512Sgeoffrey.blake@arm.com 1808512Sgeoffrey.blake@arm.com switch (daddr) { 1818512Sgeoffrey.blake@arm.com case TimerLoadReg: 1828512Sgeoffrey.blake@arm.com // Writing to this register also resets the counter register and 1838512Sgeoffrey.blake@arm.com // starts decrementing if the counter is enabled. 1848512Sgeoffrey.blake@arm.com timerLoadValue = pkt->get<uint32_t>(); 1858512Sgeoffrey.blake@arm.com restartTimerCounter(timerLoadValue); 1868512Sgeoffrey.blake@arm.com break; 1878512Sgeoffrey.blake@arm.com case TimerCounterReg: 1888512Sgeoffrey.blake@arm.com // Can be written, doesn't start counting unless the timer is enabled 1898512Sgeoffrey.blake@arm.com restartTimerCounter(pkt->get<uint32_t>()); 1908512Sgeoffrey.blake@arm.com break; 1918512Sgeoffrey.blake@arm.com case TimerControlReg: 1928512Sgeoffrey.blake@arm.com old_enable = timerControl.enable; 1938512Sgeoffrey.blake@arm.com timerControl = pkt->get<uint32_t>(); 1948512Sgeoffrey.blake@arm.com if ((old_enable == 0) && timerControl.enable) 1958512Sgeoffrey.blake@arm.com restartTimerCounter(timerLoadValue); 1968512Sgeoffrey.blake@arm.com break; 1978512Sgeoffrey.blake@arm.com case TimerIntStatusReg: 1988512Sgeoffrey.blake@arm.com rawIntTimer = false; 1998512Sgeoffrey.blake@arm.com if (pendingIntTimer) { 2008512Sgeoffrey.blake@arm.com pendingIntTimer = false; 2018512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Clearing interrupt\n"); 2028512Sgeoffrey.blake@arm.com } 2038512Sgeoffrey.blake@arm.com break; 2048512Sgeoffrey.blake@arm.com case WatchdogLoadReg: 2058512Sgeoffrey.blake@arm.com watchdogLoadValue = pkt->get<uint32_t>(); 2068512Sgeoffrey.blake@arm.com restartWatchdogCounter(watchdogLoadValue); 2078512Sgeoffrey.blake@arm.com break; 2088512Sgeoffrey.blake@arm.com case WatchdogCounterReg: 2098512Sgeoffrey.blake@arm.com // Can't be written when in watchdog mode, but can in timer mode 2108512Sgeoffrey.blake@arm.com if (!watchdogControl.watchdogMode) { 2118512Sgeoffrey.blake@arm.com restartWatchdogCounter(pkt->get<uint32_t>()); 2128512Sgeoffrey.blake@arm.com } 2138512Sgeoffrey.blake@arm.com break; 2148512Sgeoffrey.blake@arm.com case WatchdogControlReg: 2158512Sgeoffrey.blake@arm.com old_enable = watchdogControl.enable; 2168512Sgeoffrey.blake@arm.com old_wd_mode = watchdogControl.watchdogMode; 2178512Sgeoffrey.blake@arm.com watchdogControl = pkt->get<uint32_t>(); 2188512Sgeoffrey.blake@arm.com if ((old_enable == 0) && watchdogControl.enable) 2198512Sgeoffrey.blake@arm.com restartWatchdogCounter(watchdogLoadValue); 2208512Sgeoffrey.blake@arm.com // cannot disable watchdog using control register 2218512Sgeoffrey.blake@arm.com if ((old_wd_mode == 1) && watchdogControl.watchdogMode == 0) 2228512Sgeoffrey.blake@arm.com watchdogControl.watchdogMode = 1; 2238512Sgeoffrey.blake@arm.com break; 2248512Sgeoffrey.blake@arm.com case WatchdogIntStatusReg: 2258512Sgeoffrey.blake@arm.com rawIntWatchdog = false; 2268512Sgeoffrey.blake@arm.com if (pendingIntWatchdog) { 2278512Sgeoffrey.blake@arm.com pendingIntWatchdog = false; 2288512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Clearing watchdog interrupt\n"); 2298512Sgeoffrey.blake@arm.com } 2308512Sgeoffrey.blake@arm.com break; 2318512Sgeoffrey.blake@arm.com case WatchdogResetStatusReg: 2328512Sgeoffrey.blake@arm.com rawResetWatchdog = false; 2338512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Clearing watchdog reset flag\n"); 2348512Sgeoffrey.blake@arm.com break; 2358512Sgeoffrey.blake@arm.com case WatchdogDisableReg: 2368512Sgeoffrey.blake@arm.com old_val = watchdogDisableReg; 2378512Sgeoffrey.blake@arm.com watchdogDisableReg = pkt->get<uint32_t>(); 2388512Sgeoffrey.blake@arm.com // if this sequence is observed, turn off watchdog mode 2398512Sgeoffrey.blake@arm.com if (old_val == 0x12345678 && watchdogDisableReg == 0x87654321) 2408512Sgeoffrey.blake@arm.com watchdogControl.watchdogMode = 0; 2418512Sgeoffrey.blake@arm.com break; 2428512Sgeoffrey.blake@arm.com default: 2438512Sgeoffrey.blake@arm.com panic("Tried to write CpuLocalTimer timer at offset %#x\n", daddr); 2448512Sgeoffrey.blake@arm.com break; 2458512Sgeoffrey.blake@arm.com } 2468512Sgeoffrey.blake@arm.com} 2478512Sgeoffrey.blake@arm.com 2488512Sgeoffrey.blake@arm.com//XXX: Two functions are needed because the control registers are different types 2498512Sgeoffrey.blake@arm.comvoid 2508512Sgeoffrey.blake@arm.comCpuLocalTimer::Timer::restartTimerCounter(uint32_t val) 2518512Sgeoffrey.blake@arm.com{ 2528512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Resetting timer counter with value %#x\n", val); 2538512Sgeoffrey.blake@arm.com if (!timerControl.enable) 2548512Sgeoffrey.blake@arm.com return; 2558512Sgeoffrey.blake@arm.com 2569545Sandreas.hansson@arm.com Tick time = parent->clockPeriod() * power(16, timerControl.prescalar); 2578512Sgeoffrey.blake@arm.com time *= val; 2588512Sgeoffrey.blake@arm.com 2598512Sgeoffrey.blake@arm.com if (timerZeroEvent.scheduled()) { 2608512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n"); 2618512Sgeoffrey.blake@arm.com parent->deschedule(timerZeroEvent); 2628512Sgeoffrey.blake@arm.com } 2638512Sgeoffrey.blake@arm.com parent->schedule(timerZeroEvent, curTick() + time); 2648512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time); 2658512Sgeoffrey.blake@arm.com} 2668512Sgeoffrey.blake@arm.com 2678512Sgeoffrey.blake@arm.comvoid 2688512Sgeoffrey.blake@arm.comCpuLocalTimer::Timer::restartWatchdogCounter(uint32_t val) 2698512Sgeoffrey.blake@arm.com{ 2708512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Resetting watchdog counter with value %#x\n", val); 2718512Sgeoffrey.blake@arm.com if (!watchdogControl.enable) 2728512Sgeoffrey.blake@arm.com return; 2738512Sgeoffrey.blake@arm.com 2749545Sandreas.hansson@arm.com Tick time = parent->clockPeriod() * power(16, watchdogControl.prescalar); 2758512Sgeoffrey.blake@arm.com time *= val; 2768512Sgeoffrey.blake@arm.com 2778512Sgeoffrey.blake@arm.com if (watchdogZeroEvent.scheduled()) { 2788512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n"); 2798512Sgeoffrey.blake@arm.com parent->deschedule(watchdogZeroEvent); 2808512Sgeoffrey.blake@arm.com } 2818512Sgeoffrey.blake@arm.com parent->schedule(watchdogZeroEvent, curTick() + time); 2828512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time); 2838512Sgeoffrey.blake@arm.com} 2848512Sgeoffrey.blake@arm.com////// 2858512Sgeoffrey.blake@arm.com 2868512Sgeoffrey.blake@arm.comvoid 2878512Sgeoffrey.blake@arm.comCpuLocalTimer::Timer::timerAtZero() 2888512Sgeoffrey.blake@arm.com{ 2898512Sgeoffrey.blake@arm.com if (!timerControl.enable) 2908512Sgeoffrey.blake@arm.com return; 2918512Sgeoffrey.blake@arm.com 2928512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Timer Counter reached zero\n"); 2938512Sgeoffrey.blake@arm.com 2948512Sgeoffrey.blake@arm.com rawIntTimer = true; 2958512Sgeoffrey.blake@arm.com bool old_pending = pendingIntTimer; 2968512Sgeoffrey.blake@arm.com if (timerControl.intEnable) 2978512Sgeoffrey.blake@arm.com pendingIntTimer = true; 2988993SAli.Saidi@ARM.com if (pendingIntTimer && !old_pending) { 2998512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- Causing interrupt\n"); 3008512Sgeoffrey.blake@arm.com parent->gic->sendPPInt(intNumTimer, cpuNum); 3018512Sgeoffrey.blake@arm.com } 3028512Sgeoffrey.blake@arm.com 3038512Sgeoffrey.blake@arm.com if (!timerControl.autoReload) 3048512Sgeoffrey.blake@arm.com return; 3058512Sgeoffrey.blake@arm.com else 3068512Sgeoffrey.blake@arm.com restartTimerCounter(timerLoadValue); 3078512Sgeoffrey.blake@arm.com} 3088512Sgeoffrey.blake@arm.com 3098512Sgeoffrey.blake@arm.comvoid 3108512Sgeoffrey.blake@arm.comCpuLocalTimer::Timer::watchdogAtZero() 3118512Sgeoffrey.blake@arm.com{ 3128512Sgeoffrey.blake@arm.com if (!watchdogControl.enable) 3138512Sgeoffrey.blake@arm.com return; 3148512Sgeoffrey.blake@arm.com 3158512Sgeoffrey.blake@arm.com DPRINTF(Timer, "Watchdog Counter reached zero\n"); 3168512Sgeoffrey.blake@arm.com 3178512Sgeoffrey.blake@arm.com rawIntWatchdog = true; 3188512Sgeoffrey.blake@arm.com bool old_pending = pendingIntWatchdog; 3198512Sgeoffrey.blake@arm.com // generates an interrupt only if the watchdog is in timer 3208512Sgeoffrey.blake@arm.com // mode. 3218512Sgeoffrey.blake@arm.com if (watchdogControl.intEnable && !watchdogControl.watchdogMode) 3228512Sgeoffrey.blake@arm.com pendingIntWatchdog = true; 3238512Sgeoffrey.blake@arm.com else if (watchdogControl.watchdogMode) { 3248512Sgeoffrey.blake@arm.com rawResetWatchdog = true; 3258512Sgeoffrey.blake@arm.com fatal("gem5 ARM Model does not support true watchdog operation!\n"); 3268512Sgeoffrey.blake@arm.com //XXX: Should we ever support a true watchdog reset? 3278512Sgeoffrey.blake@arm.com } 3288512Sgeoffrey.blake@arm.com 3298993SAli.Saidi@ARM.com if (pendingIntWatchdog && !old_pending) { 3308512Sgeoffrey.blake@arm.com DPRINTF(Timer, "-- Causing interrupt\n"); 3318512Sgeoffrey.blake@arm.com parent->gic->sendPPInt(intNumWatchdog, cpuNum); 3328512Sgeoffrey.blake@arm.com } 3338512Sgeoffrey.blake@arm.com 3348512Sgeoffrey.blake@arm.com if (watchdogControl.watchdogMode) 3358512Sgeoffrey.blake@arm.com return; 3368512Sgeoffrey.blake@arm.com else if (watchdogControl.autoReload) 3378512Sgeoffrey.blake@arm.com restartWatchdogCounter(watchdogLoadValue); 3388512Sgeoffrey.blake@arm.com} 3398512Sgeoffrey.blake@arm.com 3408512Sgeoffrey.blake@arm.comvoid 34110905Sandreas.sandberg@arm.comCpuLocalTimer::Timer::serialize(CheckpointOut &cp) const 3428512Sgeoffrey.blake@arm.com{ 3438512Sgeoffrey.blake@arm.com DPRINTF(Checkpoint, "Serializing Arm CpuLocalTimer\n"); 3448512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(intNumTimer); 3458512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(intNumWatchdog); 3468512Sgeoffrey.blake@arm.com 3478512Sgeoffrey.blake@arm.com uint32_t timer_control_serial = timerControl; 3488512Sgeoffrey.blake@arm.com uint32_t watchdog_control_serial = watchdogControl; 3498512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(timer_control_serial); 3508512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(watchdog_control_serial); 3518512Sgeoffrey.blake@arm.com 3528512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(rawIntTimer); 3538512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(rawIntWatchdog); 3548512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(rawResetWatchdog); 3558512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(watchdogDisableReg); 3568512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(pendingIntTimer); 3578512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(pendingIntWatchdog); 3588512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(timerLoadValue); 3598512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(watchdogLoadValue); 3608512Sgeoffrey.blake@arm.com 3618512Sgeoffrey.blake@arm.com bool timer_is_in_event = timerZeroEvent.scheduled(); 3628512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(timer_is_in_event); 3638512Sgeoffrey.blake@arm.com bool watchdog_is_in_event = watchdogZeroEvent.scheduled(); 3648512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(watchdog_is_in_event); 3658512Sgeoffrey.blake@arm.com 3668512Sgeoffrey.blake@arm.com Tick timer_event_time; 3678512Sgeoffrey.blake@arm.com if (timer_is_in_event){ 3688512Sgeoffrey.blake@arm.com timer_event_time = timerZeroEvent.when(); 3698512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(timer_event_time); 3708512Sgeoffrey.blake@arm.com } 3718512Sgeoffrey.blake@arm.com Tick watchdog_event_time; 3728512Sgeoffrey.blake@arm.com if (watchdog_is_in_event){ 3738512Sgeoffrey.blake@arm.com watchdog_event_time = watchdogZeroEvent.when(); 3748512Sgeoffrey.blake@arm.com SERIALIZE_SCALAR(watchdog_event_time); 3758512Sgeoffrey.blake@arm.com } 3768512Sgeoffrey.blake@arm.com} 3778512Sgeoffrey.blake@arm.com 3788512Sgeoffrey.blake@arm.comvoid 37910905Sandreas.sandberg@arm.comCpuLocalTimer::Timer::unserialize(CheckpointIn &cp) 3808512Sgeoffrey.blake@arm.com{ 3818512Sgeoffrey.blake@arm.com DPRINTF(Checkpoint, "Unserializing Arm CpuLocalTimer\n"); 3828512Sgeoffrey.blake@arm.com 3838512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(intNumTimer); 3848512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(intNumWatchdog); 3858512Sgeoffrey.blake@arm.com 3868512Sgeoffrey.blake@arm.com uint32_t timer_control_serial; 3878512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(timer_control_serial); 3888512Sgeoffrey.blake@arm.com timerControl = timer_control_serial; 3898512Sgeoffrey.blake@arm.com uint32_t watchdog_control_serial; 3908512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(watchdog_control_serial); 3918512Sgeoffrey.blake@arm.com watchdogControl = watchdog_control_serial; 3928512Sgeoffrey.blake@arm.com 3938512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(rawIntTimer); 3948512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(rawIntWatchdog); 3958512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(rawResetWatchdog); 3968512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(watchdogDisableReg); 3978512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(pendingIntTimer); 3988512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(pendingIntWatchdog); 3998512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(timerLoadValue); 4008512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(watchdogLoadValue); 4018512Sgeoffrey.blake@arm.com 4028512Sgeoffrey.blake@arm.com bool timer_is_in_event; 4038512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(timer_is_in_event); 4048512Sgeoffrey.blake@arm.com bool watchdog_is_in_event; 4058512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(watchdog_is_in_event); 4068512Sgeoffrey.blake@arm.com 4078512Sgeoffrey.blake@arm.com Tick timer_event_time; 4088512Sgeoffrey.blake@arm.com if (timer_is_in_event){ 4098512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(timer_event_time); 4108512Sgeoffrey.blake@arm.com parent->schedule(timerZeroEvent, timer_event_time); 4118512Sgeoffrey.blake@arm.com } 4128512Sgeoffrey.blake@arm.com Tick watchdog_event_time; 4138512Sgeoffrey.blake@arm.com if (watchdog_is_in_event) { 4148512Sgeoffrey.blake@arm.com UNSERIALIZE_SCALAR(watchdog_event_time); 4158512Sgeoffrey.blake@arm.com parent->schedule(watchdogZeroEvent, watchdog_event_time); 4168512Sgeoffrey.blake@arm.com } 4178512Sgeoffrey.blake@arm.com} 4188512Sgeoffrey.blake@arm.com 4198512Sgeoffrey.blake@arm.com 4208512Sgeoffrey.blake@arm.com 4218512Sgeoffrey.blake@arm.comvoid 42210905Sandreas.sandberg@arm.comCpuLocalTimer::serialize(CheckpointOut &cp) const 4238512Sgeoffrey.blake@arm.com{ 42410905Sandreas.sandberg@arm.com for (int i = 0; i < CPU_MAX; i++) 42510905Sandreas.sandberg@arm.com localTimer[i].serializeSection(cp, csprintf("timer%d", i)); 4268512Sgeoffrey.blake@arm.com} 4278512Sgeoffrey.blake@arm.com 4288512Sgeoffrey.blake@arm.comvoid 42910905Sandreas.sandberg@arm.comCpuLocalTimer::unserialize(CheckpointIn &cp) 4308512Sgeoffrey.blake@arm.com{ 43110905Sandreas.sandberg@arm.com for (int i = 0; i < CPU_MAX; i++) 43210905Sandreas.sandberg@arm.com localTimer[i].unserializeSection(cp, csprintf("timer%d", i)); 4338512Sgeoffrey.blake@arm.com} 4348512Sgeoffrey.blake@arm.com 4358512Sgeoffrey.blake@arm.comCpuLocalTimer * 4368512Sgeoffrey.blake@arm.comCpuLocalTimerParams::create() 4378512Sgeoffrey.blake@arm.com{ 4388512Sgeoffrey.blake@arm.com return new CpuLocalTimer(this); 4398512Sgeoffrey.blake@arm.com} 440