smmu_v3_slaveifc.hh revision 14252
1892SN/A/* 21762SN/A * Copyright (c) 2013, 2018-2019 ARM Limited 3892SN/A * All rights reserved 4892SN/A * 5892SN/A * The license below extends only to copyright in the software and shall 6892SN/A * not be construed as granting a license to any other intellectual 7892SN/A * property including but not limited to intellectual property relating 8892SN/A * to a hardware implementation of the functionality of the software 9892SN/A * licensed hereunder. You may use the software subject to the license 10892SN/A * terms below provided that you ensure that this notice is replicated 11892SN/A * unmodified and in its entirety in all distributions of the software, 12892SN/A * modified or unmodified, in source code or in binary form. 13892SN/A * 14892SN/A * Redistribution and use in source and binary forms, with or without 15892SN/A * modification, are permitted provided that the following conditions are 16892SN/A * met: redistributions of source code must retain the above copyright 17892SN/A * notice, this list of conditions and the following disclaimer; 18892SN/A * redistributions in binary form must reproduce the above copyright 19892SN/A * notice, this list of conditions and the following disclaimer in the 20892SN/A * documentation and/or other materials provided with the distribution; 21892SN/A * neither the name of the copyright holders nor the names of its 22892SN/A * contributors may be used to endorse or promote products derived from 23892SN/A * this software without specific prior written permission. 24892SN/A * 25892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31768SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 321730SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33768SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34768SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35768SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36768SN/A * 37768SN/A * Authors: Stan Czerniawski 38768SN/A */ 39768SN/A 40768SN/A#ifndef __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ 413540Sgblack@eecs.umich.edu#define __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ 423540Sgblack@eecs.umich.edu 433540Sgblack@eecs.umich.edu#include <list> 442542SN/A 453348SN/A#include "dev/arm/smmu_v3_caches.hh" 46768SN/A#include "dev/arm/smmu_v3_defs.hh" 47768SN/A#include "dev/arm/smmu_v3_events.hh" 48768SN/A#include "dev/arm/smmu_v3_ports.hh" 492107SN/A#include "dev/arm/smmu_v3_proc.hh" 502107SN/A#include "params/SMMUv3SlaveInterface.hh" 51768SN/A#include "sim/clocked_object.hh" 524762Snate@binkert.org 532542SN/Aclass SMMUTranslationProcess; 54768SN/Aclass SMMUv3; 553846Shsul@eecs.umich.educlass SMMUSlavePort; 56809SN/A 57835SN/Aclass SMMUv3SlaveInterface : public ClockedObject 58835SN/A{ 59835SN/A protected: 60835SN/A friend class SMMUTranslationProcess; 61835SN/A 62768SN/A public: 63896SN/A SMMUv3 *smmu; 64896SN/A SMMUTLB* microTLB; 65896SN/A SMMUTLB* mainTLB; 66775SN/A 672539SN/A const bool microTLBEnable; 682539SN/A const bool mainTLBEnable; 692539SN/A 702539SN/A SMMUSemaphore slavePortSem; 713349SN/A SMMUSemaphore microTLBSem; 722539SN/A SMMUSemaphore mainTLBSem; 732641SN/A 742641SN/A const Cycles microTLBLat; 752539SN/A const Cycles mainTLBLat; 762630SN/A 772641SN/A SMMUSlavePort *slavePort; 782641SN/A SMMUATSSlavePort atsSlavePort; 792539SN/A SMMUATSMasterPort atsMasterPort; 802539SN/A 812641SN/A // in bytes 822539SN/A const unsigned portWidth; 832539SN/A 842539SN/A unsigned wrBufSlotsRemaining; 852630SN/A unsigned xlateSlotsRemaining; 862539SN/A unsigned pendingMemAccesses; 872539SN/A 882630SN/A const bool prefetchEnable; 892539SN/A const bool prefetchReserveLastWay; 902539SN/A 912630SN/A std::list<SMMUTranslationProcess *> duplicateReqs; 922539SN/A SMMUSignal duplicateReqRemoved; 932539SN/A 942630SN/A std::list<SMMUTranslationProcess *> dependentReads[SMMU_MAX_TRANS_ID]; 952539SN/A std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID]; 962539SN/A SMMUSignal dependentReqRemoved; 972630SN/A 982539SN/A // Receiving translation requests from the master device 992539SN/A Tick recvAtomic(PacketPtr pkt); 1002630SN/A bool recvTimingReq(PacketPtr pkt); 1012539SN/A void schedTimingResp(PacketPtr pkt); 1022539SN/A 1032630SN/A Tick atsSlaveRecvAtomic(PacketPtr pkt); 1042539SN/A bool atsSlaveRecvTimingReq(PacketPtr pkt); 1052539SN/A bool atsMasterRecvTimingResp(PacketPtr pkt); 1062630SN/A void schedAtsTimingResp(PacketPtr pkt); 1072539SN/A 1082539SN/A void scheduleDeviceRetry(); 1092630SN/A void sendDeviceRetry(); 1102539SN/A void atsSendDeviceRetry(); 1112539SN/A 1122630SN/A bool deviceNeedsRetry; 1132539SN/A bool atsDeviceNeedsRetry; 1142539SN/A 1152630SN/A SMMUDeviceRetryEvent sendDeviceRetryEvent; 1162539SN/A EventWrapper< 1172542SN/A SMMUv3SlaveInterface, 1182630SN/A &SMMUv3SlaveInterface::atsSendDeviceRetry> atsSendDeviceRetryEvent; 1192539SN/A 1202539SN/A Port& getPort(const std::string &name, PortID id) override; 1212630SN/A 1222539SN/A public: 1232539SN/A SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p); 1242539SN/A 1252539SN/A ~SMMUv3SlaveInterface() 1262539SN/A { 1272539SN/A delete microTLB; 1282630SN/A delete mainTLB; 1292539SN/A } 1302539SN/A 1312630SN/A const SMMUv3SlaveInterfaceParams * 1322539SN/A params() const 1332539SN/A { 1342539SN/A return static_cast<const SMMUv3SlaveInterfaceParams *>(_params); 1352539SN/A } 1362539SN/A 1372539SN/A DrainState drain() override; 1382630SN/A 1392539SN/A void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; } 1402539SN/A void sendRange(); 1412539SN/A}; 1422539SN/A 1432539SN/A#endif /* __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ */ 1442539SN/A