smmu_v3_slaveifc.cc revision 14039:4991b2a345a1
1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Stan Czerniawski 38 * Giacomo Travaglini 39 */ 40 41#include "dev/arm/smmu_v3_slaveifc.hh" 42 43#include "debug/SMMUv3.hh" 44#include "dev/arm/smmu_v3.hh" 45#include "dev/arm/smmu_v3_transl.hh" 46 47SMMUv3SlaveInterface::SMMUv3SlaveInterface( 48 const SMMUv3SlaveInterfaceParams *p) : 49 MemObject(p), 50 smmu(nullptr), 51 microTLB(new SMMUTLB(p->utlb_entries, 52 p->utlb_assoc, 53 p->utlb_policy)), 54 mainTLB(new SMMUTLB(p->tlb_entries, 55 p->tlb_assoc, 56 p->tlb_policy)), 57 microTLBEnable(p->utlb_enable), 58 mainTLBEnable(p->tlb_enable), 59 slavePortSem(1), 60 microTLBSem(p->utlb_slots), 61 mainTLBSem(p->tlb_slots), 62 microTLBLat(p->utlb_lat), 63 mainTLBLat(p->tlb_lat), 64 slavePort(new SMMUSlavePort(csprintf("%s.slave", name()), *this)), 65 atsSlavePort(name() + ".atsSlave", *this), 66 atsMasterPort(name() + ".atsMaster", *this), 67 portWidth(p->port_width), 68 wrBufSlotsRemaining(p->wrbuf_slots), 69 xlateSlotsRemaining(p->xlate_slots), 70 prefetchEnable(p->prefetch_enable), 71 prefetchReserveLastWay( 72 p->prefetch_reserve_last_way), 73 deviceNeedsRetry(false), 74 atsDeviceNeedsRetry(false), 75 sendDeviceRetryEvent(*this), 76 atsSendDeviceRetryEvent(this) 77{} 78 79void 80SMMUv3SlaveInterface::sendRange() 81{ 82 if (slavePort->isConnected()) { 83 inform("Slave port is connected to %d\n", 84 slavePort->getMasterPort().name()); 85 86 slavePort->sendRangeChange(); 87 } else { 88 fatal("Slave port is not connected.\n"); 89 } 90} 91 92Port& 93SMMUv3SlaveInterface::getPort(const std::string &name, PortID id) 94{ 95 if (name == "ats_master") { 96 return atsMasterPort; 97 } else if (name == "slave") { 98 return *slavePort; 99 } else if (name == "ats_slave") { 100 return atsSlavePort; 101 } else { 102 return MemObject::getPort(name, id); 103 } 104} 105 106void 107SMMUv3SlaveInterface::schedTimingResp(PacketPtr pkt) 108{ 109 slavePort->schedTimingResp(pkt, nextCycle()); 110} 111 112void 113SMMUv3SlaveInterface::schedAtsTimingResp(PacketPtr pkt) 114{ 115 atsSlavePort.schedTimingResp(pkt, nextCycle()); 116 117 if (atsDeviceNeedsRetry) { 118 atsDeviceNeedsRetry = false; 119 schedule(atsSendDeviceRetryEvent, nextCycle()); 120 } 121} 122 123Tick 124SMMUv3SlaveInterface::recvAtomic(PacketPtr pkt) 125{ 126 DPRINTF(SMMUv3, "[a] req from %s addr=%#x size=%#x\n", 127 slavePort->getMasterPort().name(), 128 pkt->getAddr(), pkt->getSize()); 129 130 std::string proc_name = csprintf("%s.port", name()); 131 SMMUTranslationProcess proc(proc_name, *smmu, *this); 132 proc.beginTransaction(SMMUTranslRequest::fromPacket(pkt)); 133 134 SMMUAction a = smmu->runProcessAtomic(&proc, pkt); 135 assert(a.type == ACTION_SEND_RESP); 136 137 return a.delay; 138} 139 140bool 141SMMUv3SlaveInterface::recvTimingReq(PacketPtr pkt) 142{ 143 DPRINTF(SMMUv3, "[t] req from %s addr=%#x size=%#x\n", 144 slavePort->getMasterPort().name(), 145 pkt->getAddr(), pkt->getSize()); 146 147 // @todo: We need to pay for this and not just zero it out 148 pkt->headerDelay = pkt->payloadDelay = 0; 149 150 unsigned nbeats = 151 (pkt->getSize() + (portWidth-1)) / portWidth; 152 153 if (xlateSlotsRemaining==0 || 154 (pkt->isWrite() && wrBufSlotsRemaining < nbeats)) 155 { 156 deviceNeedsRetry = true; 157 return false; 158 } 159 160 xlateSlotsRemaining--; 161 if (pkt->isWrite()) 162 wrBufSlotsRemaining -= nbeats; 163 164 std::string proc_name = csprintf("%s.port", name()); 165 SMMUTranslationProcess *proc = 166 new SMMUTranslationProcess(proc_name, *smmu, *this); 167 proc->beginTransaction(SMMUTranslRequest::fromPacket(pkt)); 168 169 smmu->runProcessTiming(proc, pkt); 170 171 return true; 172} 173 174Tick 175SMMUv3SlaveInterface::atsSlaveRecvAtomic(PacketPtr pkt) 176{ 177 DPRINTF(SMMUv3, "[a] ATS slave req addr=%#x size=%#x\n", 178 pkt->getAddr(), pkt->getSize()); 179 180 std::string proc_name = csprintf("%s.atsport", name()); 181 const bool ats_request = true; 182 SMMUTranslationProcess proc( 183 proc_name, *smmu, *this); 184 proc.beginTransaction(SMMUTranslRequest::fromPacket(pkt, ats_request)); 185 186 SMMUAction a = smmu->runProcessAtomic(&proc, pkt); 187 assert(a.type == ACTION_SEND_RESP_ATS); 188 189 return a.delay; 190} 191 192bool 193SMMUv3SlaveInterface::atsSlaveRecvTimingReq(PacketPtr pkt) 194{ 195 DPRINTF(SMMUv3, "[t] ATS slave req addr=%#x size=%#x\n", 196 pkt->getAddr(), pkt->getSize()); 197 198 // @todo: We need to pay for this and not just zero it out 199 pkt->headerDelay = pkt->payloadDelay = 0; 200 201 if (xlateSlotsRemaining == 0) { 202 deviceNeedsRetry = true; 203 return false; 204 } 205 206 xlateSlotsRemaining--; 207 208 std::string proc_name = csprintf("%s.atsport", name()); 209 const bool ats_request = true; 210 SMMUTranslationProcess *proc = 211 new SMMUTranslationProcess(proc_name, *smmu, *this); 212 proc->beginTransaction(SMMUTranslRequest::fromPacket(pkt, ats_request)); 213 214 smmu->runProcessTiming(proc, pkt); 215 216 return true; 217} 218 219bool 220SMMUv3SlaveInterface::atsMasterRecvTimingResp(PacketPtr pkt) 221{ 222 DPRINTF(SMMUv3, "[t] ATS master resp addr=%#x size=%#x\n", 223 pkt->getAddr(), pkt->getSize()); 224 225 // @todo: We need to pay for this and not just zero it out 226 pkt->headerDelay = pkt->payloadDelay = 0; 227 228 SMMUProcess *proc = 229 safe_cast<SMMUProcess *>(pkt->popSenderState()); 230 231 smmu->runProcessTiming(proc, pkt); 232 233 return true; 234} 235 236void 237SMMUv3SlaveInterface::sendDeviceRetry() 238{ 239 slavePort->sendRetryReq(); 240} 241 242void 243SMMUv3SlaveInterface::atsSendDeviceRetry() 244{ 245 DPRINTF(SMMUv3, "ATS retry\n"); 246 atsSlavePort.sendRetryReq(); 247} 248 249void 250SMMUv3SlaveInterface::scheduleDeviceRetry() 251{ 252 if (deviceNeedsRetry && !sendDeviceRetryEvent.scheduled()) { 253 DPRINTF(SMMUv3, "sched slave retry\n"); 254 deviceNeedsRetry = false; 255 schedule(sendDeviceRetryEvent, nextCycle()); 256 } 257} 258 259SMMUv3SlaveInterface* 260SMMUv3SlaveInterfaceParams::create() 261{ 262 return new SMMUv3SlaveInterface(this); 263} 264