smmu_v3_defs.hh revision 14086:4209778f4b3e
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2013, 2018-2019 ARM Limited 39913Ssteve.reinhardt@amd.com * All rights reserved 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 147854SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 152329SN/A * modification, are permitted provided that the following conditions are 161689SN/A * met: redistributions of source code must retain the above copyright 171689SN/A * notice, this list of conditions and the following disclaimer; 181689SN/A * redistributions in binary form must reproduce the above copyright 191689SN/A * notice, this list of conditions and the following disclaimer in the 201689SN/A * documentation and/or other materials provided with the distribution; 211689SN/A * neither the name of the copyright holders nor the names of its 221689SN/A * contributors may be used to endorse or promote products derived from 231689SN/A * this software without specific prior written permission. 241689SN/A * 251689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 261689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 271689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 281689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 291689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 301689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 311689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 321689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 331689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 341689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 351689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 361689SN/A * 371689SN/A * Authors: Stan Czerniawski 381689SN/A */ 391689SN/A 402665Ssaidi@eecs.umich.edu#ifndef __DEV_ARM_SMMU_V3_DEFS_HH__ 412665Ssaidi@eecs.umich.edu#define __DEV_ARM_SMMU_V3_DEFS_HH__ 422935Sksewell@umich.edu 431689SN/A#include <stdint.h> 441689SN/A 451060SN/A#include "base/bitunion.hh" 461060SN/A 473773Sgblack@eecs.umich.eduenum { 486329Sgblack@eecs.umich.edu SMMU_SECURE_SZ = 0x184, // Secure regs are within page0 496658Snate@binkert.org SMMU_PAGE_ZERO_SZ = 0x10000, 501717SN/A SMMU_PAGE_ONE_SZ = 0x10000, 519913Ssteve.reinhardt@amd.com SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ 528232Snate@binkert.org}; 538232Snate@binkert.org 549527SMatt.Horsnell@arm.comenum { 555529Snate@binkert.org STE_CONFIG_ABORT = 0x0, 561060SN/A STE_CONFIG_BYPASS = 0x4, 576221Snate@binkert.org STE_CONFIG_STAGE1_ONLY = 0x5, 586221Snate@binkert.org STE_CONFIG_STAGE2_ONLY = 0x6, 591061SN/A STE_CONFIG_STAGE1_AND_2 = 0x7, 605529Snate@binkert.org}; 614329Sktlim@umich.edu 624329Sktlim@umich.eduenum { 632292SN/A STAGE1_CFG_1L = 0x0, 642292SN/A STAGE1_CFG_2L_4K = 0x1, 652292SN/A STAGE1_CFG_2L_64K = 0x2, 662292SN/A}; 675529Snate@binkert.org 682361SN/Aenum { 691060SN/A ST_CFG_SPLIT_SHIFT = 6, 702292SN/A ST_CD_ADDR_SHIFT = 6, 718907Slukefahr@umich.edu CD_TTB_SHIFT = 4, 722292SN/A STE_S2TTB_SHIFT = 4, 732292SN/A}; 742292SN/A 752292SN/Aenum { 762292SN/A TRANS_GRANULE_4K = 0x0, 772292SN/A TRANS_GRANULE_64K = 0x1, 782292SN/A TRANS_GRANULE_16K = 0x2, 791060SN/A TRANS_GRANULE_INVALID = 0x3, 801060SN/A}; 811061SN/A 821060SN/Aenum { 832292SN/A ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, 841062SN/A ST_CFG_SIZE_MASK = 0x000000000000003fULL, 851062SN/A ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL, 868240Snate@binkert.org ST_CFG_FMT_MASK = 0x0000000000030000ULL, 871062SN/A ST_CFG_FMT_LINEAR = 0x0000000000000000ULL, 881062SN/A ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL, 891062SN/A ST_L2_SPAN_MASK = 0x000000000000001fULL, 908240Snate@binkert.org ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL, 911062SN/A 921062SN/A VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, 931062SN/A VMT_BASE_SIZE_MASK = 0x000000000000001fULL, 948240Snate@binkert.org 951062SN/A Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, 961062SN/A Q_BASE_SIZE_MASK = 0x000000000000001fULL, 972301SN/A 988240Snate@binkert.org E_BASE_ENABLE_MASK = 0x8000000000000000ULL, 992301SN/A E_BASE_ADDR_MASK = 0x0000fffffffffffcULL, 1002301SN/A}; 1012292SN/A 1028240Snate@binkert.orgunion SMMURegs 1032292SN/A{ 1042292SN/A uint8_t data[SMMU_REG_SIZE]; 1051062SN/A 1068240Snate@binkert.org struct 1071062SN/A { 1081062SN/A uint32_t idr0; // 0x0000 1091062SN/A uint32_t idr1; // 0x0004 1108240Snate@binkert.org uint32_t idr2; // 0x0008 1111062SN/A uint32_t idr3; // 0x000c 1121062SN/A uint32_t idr4; // 0x0010 1131062SN/A uint32_t idr5; // 0x0014 1148240Snate@binkert.org uint32_t iidr; // 0x0018 1151062SN/A uint32_t aidr; // 0x001c 1161062SN/A uint32_t cr0; // 0x0020 1171062SN/A uint32_t cr0ack; // 0x0024 1188240Snate@binkert.org uint32_t cr1; // 0x0028 1192292SN/A uint32_t cr2; // 0x002c 1201062SN/A uint32_t _pad1; // 0x0030 1211062SN/A uint32_t _pad2; // 0x0034 1228240Snate@binkert.org uint32_t _pad3; // 0x0038 1232292SN/A uint32_t _pad4; // 0x003c 1241062SN/A uint32_t statusr; // 0x0040 1252292SN/A uint32_t gbpa; // 0x0044 1268240Snate@binkert.org uint32_t agbpa; // 0x0048 1272292SN/A uint32_t _pad5; // 0x004c 1282292SN/A uint32_t irq_ctrl; // 0x0050 1291062SN/A uint32_t irq_ctrlack; // 0x0054 1308240Snate@binkert.org uint32_t _pad6; // 0x0058 1311062SN/A uint32_t _pad7; // 0x005c 1321062SN/A 1331062SN/A uint32_t gerror; // 0x0060 1348240Snate@binkert.org uint32_t gerrorn; // 0x0064 1351062SN/A uint64_t gerror_irq_cfg0; // 0x0068, 64 bit 1361062SN/A uint32_t gerror_irq_cfg1; // 0x0070 1371062SN/A uint32_t gerror_irq_cfg2; // 0x0074 1388240Snate@binkert.org uint32_t _pad_1; // 0x0078 1391062SN/A uint32_t _pad_2; // 0x007c 1401062SN/A 1411062SN/A uint64_t strtab_base; // 0x0080, 64 bit 1428240Snate@binkert.org uint32_t strtab_base_cfg; // 0x0088 1431062SN/A 1441062SN/A uint64_t cmdq_base; // 0x0090, 64 bit 1451062SN/A uint32_t cmdq_prod; // 0x0098 1468240Snate@binkert.org uint32_t cmdq_cons; // 0x009c 1471062SN/A uint64_t eventq_base; // 0x00a0, 64 bit 1481062SN/A uint32_t _pad8; // 0x00a8 1492301SN/A uint32_t _pad9; // 0x00ac 1508240Snate@binkert.org uint64_t eventq_irq_cfg0; // 0x00b0, 64 bit 1512301SN/A uint32_t eventq_irq_cfg1; // 0x00b8 1522301SN/A uint32_t eventq_irq_cfg2; // 0x00bc 1532301SN/A uint64_t priq_base; // 0x00c0, 64 bit 1542301SN/A uint32_t _pad10; // 0x00c8 1558240Snate@binkert.org uint32_t _pad11; // 0x00cc 1562301SN/A 1572301SN/A uint64_t priq_irq_cfg0; // 0x00d0 1582301SN/A uint32_t priq_irq_cfg1; // 0x00d8 1592307SN/A uint32_t priq_irq_cfg2; // 0x00dc 1608240Snate@binkert.org 1612307SN/A uint32_t _pad12[8]; // 0x00e0 - 0x0100 1622307SN/A uint32_t gatos_ctrl; // 0x0100 1632307SN/A uint32_t _pad13; // 0x0104 1647897Shestness@cs.utexas.edu uint64_t gatos_sid; // 0x0108 1658240Snate@binkert.org uint64_t gatos_addr; // 0x0110 1667897Shestness@cs.utexas.edu uint64_t gatos_par; // 0x0118 1677897Shestness@cs.utexas.edu uint32_t _pad14[24]; // 0x0120 1687897Shestness@cs.utexas.edu uint32_t vatos_sel; // 0x0180 1698240Snate@binkert.org 1707897Shestness@cs.utexas.edu uint32_t _pad15[8095]; // 0x184 - 0x7ffc 1717897Shestness@cs.utexas.edu 1721062SN/A uint8_t _secure_regs[SMMU_SECURE_SZ]; // 0x8000 - 0x8180 1731062SN/A 1741062SN/A uint32_t _pad16[8095]; // 0x8184 - 0x10000 1751062SN/A 1762292SN/A // Page 1 1771060SN/A uint32_t _pad17[42]; // 0x10000 1781060SN/A uint32_t eventq_prod; // 0x100A8 1791060SN/A uint32_t eventq_cons; // 0x100AC 1801060SN/A 1811060SN/A uint32_t _pad18[6]; // 0x100B0 1821060SN/A uint32_t priq_prod; // 0x100C8 1831060SN/A uint32_t priq_cons; // 0x100CC 1841060SN/A }; 1851060SN/A}; 1861060SN/A 1871060SN/Astruct StreamTableEntry 1881060SN/A{ 1891060SN/A BitUnion64(DWORD0) 1901061SN/A Bitfield<0> valid; 1911060SN/A Bitfield<3, 1> config; 1922292SN/A Bitfield<5, 4> s1fmt; 1931060SN/A Bitfield<51, 6> s1ctxptr; 1941060SN/A Bitfield<63, 59> s1cdmax; 1951060SN/A EndBitUnion(DWORD0) 1961060SN/A DWORD0 dw0; 1971060SN/A 1981060SN/A BitUnion64(DWORD1) 1991060SN/A Bitfield<1, 0> s1dss; 2001061SN/A Bitfield<3, 2> s1cir; 2011060SN/A Bitfield<5, 4> s1cor; 2022292SN/A Bitfield<7, 6> s1csh; 2031060SN/A Bitfield<8> s2hwu59; 2041060SN/A Bitfield<9> s2hwu60; 2051060SN/A Bitfield<10> s2hwu61; 2061060SN/A Bitfield<11> s2hwu62; 2071060SN/A Bitfield<12> dre; 2081060SN/A Bitfield<16, 13> cont; 2091060SN/A Bitfield<17> dcp; 2101061SN/A Bitfield<18> ppar; 2111060SN/A Bitfield<19> mev; 2129427SAndreas.Sandberg@ARM.com Bitfield<27> s1stalld; 2131060SN/A Bitfield<29, 28> eats; 2149444SAndreas.Sandberg@ARM.com Bitfield<31, 30> strw; 2159444SAndreas.Sandberg@ARM.com Bitfield<35, 32> memattr; 2169444SAndreas.Sandberg@ARM.com Bitfield<36> mtcfg; 2179444SAndreas.Sandberg@ARM.com Bitfield<40, 37> alloccfg; 2189444SAndreas.Sandberg@ARM.com Bitfield<45, 44> shcfg; 2199444SAndreas.Sandberg@ARM.com Bitfield<47, 46> nscfg; 2209444SAndreas.Sandberg@ARM.com Bitfield<49, 48> privcfg; 2219444SAndreas.Sandberg@ARM.com Bitfield<51, 50> instcfg; 2229444SAndreas.Sandberg@ARM.com EndBitUnion(DWORD1) 2239444SAndreas.Sandberg@ARM.com DWORD1 dw1; 2249444SAndreas.Sandberg@ARM.com 2259444SAndreas.Sandberg@ARM.com BitUnion64(DWORD2) 2262329SN/A Bitfield<15, 0> s2vmid; 2276221Snate@binkert.org Bitfield<37, 32> s2t0sz; 2289444SAndreas.Sandberg@ARM.com Bitfield<39, 38> s2sl0; 2299444SAndreas.Sandberg@ARM.com Bitfield<41, 40> s2ir0; 2302292SN/A Bitfield<43, 42> s2or0; 2312292SN/A Bitfield<45, 44> s2sh0; 2322292SN/A Bitfield<47, 46> s2tg; 2332292SN/A Bitfield<50, 48> s2ps; 2349444SAndreas.Sandberg@ARM.com Bitfield<51> s2aa64; 2359444SAndreas.Sandberg@ARM.com Bitfield<52> s2endi; 2369444SAndreas.Sandberg@ARM.com Bitfield<53> s2affd; 2379444SAndreas.Sandberg@ARM.com Bitfield<54> s2ptw; 2389444SAndreas.Sandberg@ARM.com Bitfield<55> s2hd; 2399444SAndreas.Sandberg@ARM.com Bitfield<56> s2ha; 2409444SAndreas.Sandberg@ARM.com Bitfield<57> s2s; 2419444SAndreas.Sandberg@ARM.com Bitfield<58> s2r; 2422292SN/A EndBitUnion(DWORD2) 2431060SN/A DWORD2 dw2; 2441060SN/A 2452292SN/A BitUnion64(DWORD3) 2462292SN/A Bitfield<51, 4> s2ttb; 2476221Snate@binkert.org EndBitUnion(DWORD3) 2482292SN/A DWORD3 dw3; 2492292SN/A 2502292SN/A uint64_t _pad[4]; 2512292SN/A}; 2522292SN/A 2531061SN/Astruct ContextDescriptor 2541060SN/A{ 2552292SN/A BitUnion64(DWORD0) 2561060SN/A Bitfield<5, 0> t0sz; 2576221Snate@binkert.org Bitfield<7, 6> tg0; 2586221Snate@binkert.org Bitfield<9, 8> ir0; 2591060SN/A Bitfield<11, 10> or0; 2601060SN/A Bitfield<13, 12> sh0; 2611061SN/A Bitfield<14> epd0; 2621060SN/A Bitfield<15> endi; 2632292SN/A Bitfield<21, 16> t1sz; 2641060SN/A Bitfield<23, 22> tg1; 2652292SN/A Bitfield<25, 24> ir1; 2662292SN/A Bitfield<27, 26> or1; 2671060SN/A Bitfield<29, 28> sh1; 2682292SN/A Bitfield<30> epd1; 2692292SN/A Bitfield<31> valid; 2702292SN/A Bitfield<34, 32> ips; 2712292SN/A Bitfield<35> affd; 2722292SN/A Bitfield<36> wxn; 2731060SN/A Bitfield<37> uwxn; 2741060SN/A Bitfield<39, 38> tbi; 2751061SN/A Bitfield<40> pan; 2762863Sktlim@umich.edu Bitfield<41> aa64; 2779444SAndreas.Sandberg@ARM.com Bitfield<42> hd; 2781060SN/A Bitfield<43> ha; 2799444SAndreas.Sandberg@ARM.com Bitfield<44> s; 2809444SAndreas.Sandberg@ARM.com Bitfield<45> r; 2819444SAndreas.Sandberg@ARM.com Bitfield<46> a; 2829444SAndreas.Sandberg@ARM.com Bitfield<47> aset; 2839444SAndreas.Sandberg@ARM.com Bitfield<63, 48> asid; 2849444SAndreas.Sandberg@ARM.com EndBitUnion(DWORD0) 2859444SAndreas.Sandberg@ARM.com DWORD0 dw0; 2862863Sktlim@umich.edu 2872316SN/A BitUnion64(DWORD1) 2881060SN/A Bitfield<0> nscfg0; 2892316SN/A Bitfield<1> had0; 2902316SN/A Bitfield<51, 4> ttb0; 2912307SN/A Bitfield<60> hwu0g59; 2921060SN/A Bitfield<61> hwu0g60; 2939444SAndreas.Sandberg@ARM.com Bitfield<62> hwu0g61; 2949444SAndreas.Sandberg@ARM.com Bitfield<63> hwu0g62; 2951060SN/A EndBitUnion(DWORD1) 2969444SAndreas.Sandberg@ARM.com DWORD1 dw1; 2979444SAndreas.Sandberg@ARM.com 2989444SAndreas.Sandberg@ARM.com BitUnion64(DWORD2) 2999444SAndreas.Sandberg@ARM.com Bitfield<0> nscfg1; 3006221Snate@binkert.org Bitfield<1> had1; 3019444SAndreas.Sandberg@ARM.com Bitfield<51, 4> ttb1; 3029444SAndreas.Sandberg@ARM.com Bitfield<60> hwu1g59; 3039444SAndreas.Sandberg@ARM.com Bitfield<61> hwu1g60; 3049444SAndreas.Sandberg@ARM.com Bitfield<62> hwu1g61; 3052307SN/A Bitfield<63> hwu1g62; 3062307SN/A EndBitUnion(DWORD2) 3072307SN/A DWORD2 dw2; 3082307SN/A 3092307SN/A uint64_t mair; 3106221Snate@binkert.org uint64_t amair; 3111858SN/A uint64_t _pad[3]; 3122292SN/A}; 3131858SN/A 3142292SN/Aenum SMMUCommandType { 3152292SN/A CMD_PRF_CONFIG = 0x1000, 3162292SN/A CMD_PRF_ADDR = 0x1001, 3172292SN/A CMD_INV_STE = 0x1100, 3183788Sgblack@eecs.umich.edu CMD_INV_CD = 0x1101, 3192292SN/A CMD_INV_CD_ALL = 0x1102, 3202698Sktlim@umich.edu CMD_INV_ALL = 0x1104, 3213788Sgblack@eecs.umich.edu CMD_TLBI_ALL = 0x1110, 3222301SN/A CMD_TLBI_ASID = 0x1111, 3233788Sgblack@eecs.umich.edu CMD_TLBI_VAAL = 0x1112, 3243788Sgblack@eecs.umich.edu CMD_TLBI_VAA = 0x1113, 3253788Sgblack@eecs.umich.edu CMD_TLBI_VAL = 0x1114, 3263788Sgblack@eecs.umich.edu CMD_TLBI_VA = 0x1115, 3273788Sgblack@eecs.umich.edu CMD_TLBI_VM_IPAL = 0x1120, 3283788Sgblack@eecs.umich.edu CMD_TLBI_VM_IPA = 0x1121, 3293788Sgblack@eecs.umich.edu CMD_TLBI_VM_S12 = 0x1122, 3303788Sgblack@eecs.umich.edu CMD_RESUME_S = 0x1200, 3313788Sgblack@eecs.umich.edu}; 3323788Sgblack@eecs.umich.edu 3333788Sgblack@eecs.umich.edustruct SMMUCommand 3342292SN/A{ 3352292SN/A uint32_t type; 3362292SN/A uint32_t data[3]; 3372292SN/A}; 3382292SN/A 3392329SN/Aenum SMMUEventTypes { 3402292SN/A EVT_FAULT = 0x0001, 3412292SN/A}; 3422292SN/A 3432935Sksewell@umich.eduenum SMMUEventFlags { 3442935Sksewell@umich.edu EVF_WRITE = 0x0001, 3452731Sktlim@umich.edu}; 3462292SN/A 3472292SN/Astruct SMMUEvent 3482292SN/A{ 3492935Sksewell@umich.edu uint16_t type; 3502292SN/A uint16_t stag; 3512292SN/A uint32_t flags; 3522935Sksewell@umich.edu uint32_t streamId; 3534632Sgblack@eecs.umich.edu uint32_t substreamId; 3543093Sksewell@umich.edu uint64_t va; 3552292SN/A uint64_t ipa; 3562292SN/A}; 3573093Sksewell@umich.edu 3584632Sgblack@eecs.umich.eduenum { 3592935Sksewell@umich.edu SMMU_MAX_TRANS_ID = 64 3602292SN/A}; 3612292SN/A 3622292SN/A#endif /* __DEV_ARM_SMMU_V3_DEFS_HH__ */ 3632292SN/A