smmu_v3_defs.hh revision 14039
1/* 2 * Copyright (c) 2013, 2018-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Stan Czerniawski 38 */ 39 40#ifndef __DEV_ARM_SMMU_V3_DEFS_HH__ 41#define __DEV_ARM_SMMU_V3_DEFS_HH__ 42 43#include <stdint.h> 44 45#include "base/bitunion.hh" 46 47enum { 48 SMMU_SECURE_SZ = 0x184, // Secure regs are within page0 49 SMMU_PAGE_ZERO_SZ = 0x10000, 50 SMMU_PAGE_ONE_SZ = 0x10000, 51 SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ 52}; 53 54enum { 55 STE_CONFIG_ABORT = 0x0, 56 STE_CONFIG_BYPASS = 0x4, 57 STE_CONFIG_STAGE1_ONLY = 0x5, 58 STE_CONFIG_STAGE2_ONLY = 0x6, 59 STE_CONFIG_STAGE1_AND_2 = 0x7, 60}; 61 62enum { 63 STAGE1_CFG_1L = 0x0, 64 STAGE1_CFG_2L_4K = 0x1, 65 STAGE1_CFG_2L_64K = 0x2, 66}; 67 68enum { 69 ST_CFG_SPLIT_SHIFT = 6, 70 ST_CD_ADDR_SHIFT = 5, 71 CD_TTB_SHIFT = 4, 72 STE_S2TTB_SHIFT = 4, 73}; 74 75enum { 76 TRANS_GRANULE_4K = 0x0, 77 TRANS_GRANULE_64K = 0x1, 78 TRANS_GRANULE_16K = 0x2, 79 TRANS_GRANULE_INVALID = 0x3, 80}; 81 82enum { 83 ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, 84 ST_CFG_SIZE_MASK = 0x000000000000003fULL, 85 ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL, 86 ST_CFG_FMT_MASK = 0x0000000000030000ULL, 87 ST_CFG_FMT_LINEAR = 0x0000000000000000ULL, 88 ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL, 89 ST_L2_SPAN_MASK = 0x000000000000001fULL, 90 ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL, 91 92 VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, 93 VMT_BASE_SIZE_MASK = 0x000000000000001fULL, 94 95 Q_CONS_PROD_MASK = 0x00000000000fffffULL, 96 Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, 97 Q_BASE_SIZE_MASK = 0x000000000000001fULL, 98 99 E_BASE_ENABLE_MASK = 0x8000000000000000ULL, 100 E_BASE_ADDR_MASK = 0x0000fffffffffffcULL, 101}; 102 103union SMMURegs 104{ 105 uint8_t data[SMMU_REG_SIZE]; 106 107 struct 108 { 109 uint32_t idr0; // 0x0000 110 uint32_t idr1; // 0x0004 111 uint32_t idr2; // 0x0008 112 uint32_t idr3; // 0x000c 113 uint32_t idr4; // 0x0010 114 uint32_t idr5; // 0x0014 115 uint32_t iidr; // 0x0018 116 uint32_t aidr; // 0x001c 117 uint32_t cr0; // 0x0020 118 uint32_t cr0ack; // 0x0024 119 uint32_t cr1; // 0x0028 120 uint32_t cr2; // 0x002c 121 uint32_t _pad1; // 0x0030 122 uint32_t _pad2; // 0x0034 123 uint32_t _pad3; // 0x0038 124 uint32_t _pad4; // 0x003c 125 uint32_t statusr; // 0x0040 126 uint32_t gbpa; // 0x0044 127 uint32_t agbpa; // 0x0048 128 uint32_t _pad5; // 0x004c 129 uint32_t irq_ctrl; // 0x0050 130 uint32_t irq_ctrlack; // 0x0054 131 uint32_t _pad6; // 0x0058 132 uint32_t _pad7; // 0x005c 133 134 uint32_t gerror; // 0x0060 135 uint32_t gerrorn; // 0x0064 136 uint64_t gerror_irq_cfg0; // 0x0068, 64 bit 137 uint32_t gerror_irq_cfg1; // 0x0070 138 uint32_t gerror_irq_cfg2; // 0x0074 139 uint32_t _pad_1; // 0x0078 140 uint32_t _pad_2; // 0x007c 141 142 uint64_t strtab_base; // 0x0080, 64 bit 143 uint32_t strtab_base_cfg; // 0x0088 144 145 uint64_t cmdq_base; // 0x0090, 64 bit 146 uint32_t cmdq_prod; // 0x0098 147 uint32_t cmdq_cons; // 0x009c 148 uint64_t eventq_base; // 0x00a0, 64 bit 149 uint32_t _pad8; // 0x00a8 150 uint32_t _pad9; // 0x00ac 151 uint64_t eventq_irq_cfg0; // 0x00b0, 64 bit 152 uint32_t eventq_irq_cfg1; // 0x00b8 153 uint32_t eventq_irq_cfg2; // 0x00bc 154 uint64_t priq_base; // 0x00c0, 64 bit 155 uint32_t _pad10; // 0x00c8 156 uint32_t _pad11; // 0x00cc 157 158 uint64_t priq_irq_cfg0; // 0x00d0 159 uint32_t priq_irq_cfg1; // 0x00d8 160 uint32_t priq_irq_cfg2; // 0x00dc 161 162 uint32_t _pad12[8]; // 0x00e0 - 0x0100 163 uint32_t gatos_ctrl; // 0x0100 164 uint32_t _pad13; // 0x0104 165 uint64_t gatos_sid; // 0x0108 166 uint64_t gatos_addr; // 0x0110 167 uint64_t gatos_par; // 0x0118 168 uint32_t _pad14[24]; // 0x0120 169 uint32_t vatos_sel; // 0x0180 170 171 uint32_t _pad15[8095]; // 0x184 - 0x7ffc 172 173 uint8_t _secure_regs[SMMU_SECURE_SZ]; // 0x8000 - 0x8180 174 175 uint32_t _pad16[8095]; // 0x8184 - 0x10000 176 177 // Page 1 178 uint32_t _pad17[42]; // 0x10000 179 uint32_t eventq_prod; // 0x100A8 180 uint32_t eventq_cons; // 0x100AC 181 182 uint32_t _pad18[6]; // 0x100B0 183 uint32_t priq_prod; // 0x100C8 184 uint32_t priq_cons; // 0x100CC 185 }; 186}; 187 188struct StreamTableEntry 189{ 190 BitUnion64(DWORD0) 191 Bitfield<0> valid; 192 Bitfield<3, 1> config; 193 Bitfield<5, 4> s1fmt; 194 Bitfield<51, 6> s1ctxptr; 195 Bitfield<63, 59> s1cdmax; 196 EndBitUnion(DWORD0) 197 DWORD0 dw0; 198 199 BitUnion64(DWORD1) 200 Bitfield<1, 0> s1dss; 201 Bitfield<3, 2> s1cir; 202 Bitfield<5, 4> s1cor; 203 Bitfield<7, 6> s1csh; 204 Bitfield<8> s2hwu59; 205 Bitfield<9> s2hwu60; 206 Bitfield<10> s2hwu61; 207 Bitfield<11> s2hwu62; 208 Bitfield<12> dre; 209 Bitfield<16, 13> cont; 210 Bitfield<17> dcp; 211 Bitfield<18> ppar; 212 Bitfield<19> mev; 213 Bitfield<27> s1stalld; 214 Bitfield<29, 28> eats; 215 Bitfield<31, 30> strw; 216 Bitfield<35, 32> memattr; 217 Bitfield<36> mtcfg; 218 Bitfield<40, 37> alloccfg; 219 Bitfield<45, 44> shcfg; 220 Bitfield<47, 46> nscfg; 221 Bitfield<49, 48> privcfg; 222 Bitfield<51, 50> instcfg; 223 EndBitUnion(DWORD1) 224 DWORD1 dw1; 225 226 BitUnion64(DWORD2) 227 Bitfield<15, 0> s2vmid; 228 Bitfield<37, 32> s2t0sz; 229 Bitfield<39, 38> s2sl0; 230 Bitfield<41, 40> s2ir0; 231 Bitfield<43, 42> s2or0; 232 Bitfield<45, 44> s2sh0; 233 Bitfield<47, 46> s2tg; 234 Bitfield<50, 48> s2ps; 235 Bitfield<51> s2aa64; 236 Bitfield<52> s2endi; 237 Bitfield<53> s2affd; 238 Bitfield<54> s2ptw; 239 Bitfield<55> s2hd; 240 Bitfield<56> s2ha; 241 Bitfield<57> s2s; 242 Bitfield<58> s2r; 243 EndBitUnion(DWORD2) 244 DWORD2 dw2; 245 246 BitUnion64(DWORD3) 247 Bitfield<51, 4> s2ttb; 248 EndBitUnion(DWORD3) 249 DWORD3 dw3; 250 251 uint64_t _pad[4]; 252}; 253 254struct ContextDescriptor 255{ 256 BitUnion64(DWORD0) 257 Bitfield<5, 0> t0sz; 258 Bitfield<7, 6> tg0; 259 Bitfield<9, 8> ir0; 260 Bitfield<11, 10> or0; 261 Bitfield<13, 12> sh0; 262 Bitfield<14> epd0; 263 Bitfield<15> endi; 264 Bitfield<21, 16> t1sz; 265 Bitfield<23, 22> tg1; 266 Bitfield<25, 24> ir1; 267 Bitfield<27, 26> or1; 268 Bitfield<29, 28> sh1; 269 Bitfield<30> epd1; 270 Bitfield<31> valid; 271 Bitfield<34, 32> ips; 272 Bitfield<35> affd; 273 Bitfield<36> wxn; 274 Bitfield<37> uwxn; 275 Bitfield<39, 38> tbi; 276 Bitfield<40> pan; 277 Bitfield<41> aa64; 278 Bitfield<42> hd; 279 Bitfield<43> ha; 280 Bitfield<44> s; 281 Bitfield<45> r; 282 Bitfield<46> a; 283 Bitfield<47> aset; 284 Bitfield<63, 48> asid; 285 EndBitUnion(DWORD0) 286 DWORD0 dw0; 287 288 BitUnion64(DWORD1) 289 Bitfield<0> nscfg0; 290 Bitfield<1> had0; 291 Bitfield<51, 4> ttb0; 292 Bitfield<60> hwu0g59; 293 Bitfield<61> hwu0g60; 294 Bitfield<62> hwu0g61; 295 Bitfield<63> hwu0g62; 296 EndBitUnion(DWORD1) 297 DWORD1 dw1; 298 299 BitUnion64(DWORD2) 300 Bitfield<0> nscfg1; 301 Bitfield<1> had1; 302 Bitfield<51, 4> ttb1; 303 Bitfield<60> hwu1g59; 304 Bitfield<61> hwu1g60; 305 Bitfield<62> hwu1g61; 306 Bitfield<63> hwu1g62; 307 EndBitUnion(DWORD2) 308 DWORD2 dw2; 309 310 uint64_t mair; 311 uint64_t amair; 312 uint64_t _pad[3]; 313}; 314 315enum SMMUCommandType { 316 CMD_PRF_CONFIG = 0x1000, 317 CMD_PRF_ADDR = 0x1001, 318 CMD_INV_STE = 0x1100, 319 CMD_INV_CD = 0x1101, 320 CMD_INV_CD_ALL = 0x1102, 321 CMD_INV_ALL = 0x1104, 322 CMD_TLBI_ALL = 0x1110, 323 CMD_TLBI_ASID = 0x1111, 324 CMD_TLBI_VAAL = 0x1112, 325 CMD_TLBI_VAA = 0x1113, 326 CMD_TLBI_VAL = 0x1114, 327 CMD_TLBI_VA = 0x1115, 328 CMD_TLBI_VM_IPAL = 0x1120, 329 CMD_TLBI_VM_IPA = 0x1121, 330 CMD_TLBI_VM_S12 = 0x1122, 331 CMD_RESUME_S = 0x1200, 332}; 333 334struct SMMUCommand 335{ 336 uint32_t type; 337 uint32_t data[3]; 338}; 339 340enum SMMUEventTypes { 341 EVT_FAULT = 0x0001, 342}; 343 344enum SMMUEventFlags { 345 EVF_WRITE = 0x0001, 346}; 347 348struct SMMUEvent 349{ 350 uint16_t type; 351 uint16_t stag; 352 uint32_t flags; 353 uint32_t streamId; 354 uint32_t substreamId; 355 uint64_t va; 356 uint64_t ipa; 357}; 358 359enum { 360 SMMU_MAX_TRANS_ID = 64 361}; 362 363#endif /* __DEV_ARM_SMMU_V3_DEFS_HH__ */ 364