rv_ctrl.hh revision 9958
17584SAli.Saidi@arm.com/* 29958Smatt.evans@arm.com * Copyright (c) 2010,2013 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 157584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 167584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 177584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 187584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 197584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 207584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 217584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 227584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 237584SAli.Saidi@arm.com * this software without specific prior written permission. 247584SAli.Saidi@arm.com * 257584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367584SAli.Saidi@arm.com * 377584SAli.Saidi@arm.com * Authors: Ali Saidi 387584SAli.Saidi@arm.com */ 397584SAli.Saidi@arm.com 407584SAli.Saidi@arm.com#ifndef __DEV_ARM_RV_HH__ 417584SAli.Saidi@arm.com#define __DEV_ARM_RV_HH__ 427584SAli.Saidi@arm.com 437950SAli.Saidi@ARM.com#include "base/bitunion.hh" 447584SAli.Saidi@arm.com#include "dev/io_device.hh" 457584SAli.Saidi@arm.com#include "params/RealViewCtrl.hh" 467584SAli.Saidi@arm.com 477584SAli.Saidi@arm.com/** @file 487584SAli.Saidi@arm.com * This implements the simple real view registers on a PBXA9 497584SAli.Saidi@arm.com */ 507584SAli.Saidi@arm.com 517584SAli.Saidi@arm.comclass RealViewCtrl : public BasicPioDevice 527584SAli.Saidi@arm.com{ 537584SAli.Saidi@arm.com protected: 547584SAli.Saidi@arm.com enum { 557584SAli.Saidi@arm.com IdReg = 0x00, 567584SAli.Saidi@arm.com SwReg = 0x04, 577584SAli.Saidi@arm.com Led = 0x08, 587584SAli.Saidi@arm.com Osc0 = 0x0C, 597584SAli.Saidi@arm.com Osc1 = 0x10, 607584SAli.Saidi@arm.com Osc2 = 0x14, 617584SAli.Saidi@arm.com Osc3 = 0x18, 627584SAli.Saidi@arm.com Osc4 = 0x1C, 637584SAli.Saidi@arm.com Lock = 0x20, 647584SAli.Saidi@arm.com Clock100 = 0x24, 657584SAli.Saidi@arm.com CfgData1 = 0x28, 667584SAli.Saidi@arm.com CfgData2 = 0x2C, 677584SAli.Saidi@arm.com Flags = 0x30, 687584SAli.Saidi@arm.com FlagsClr = 0x34, 697584SAli.Saidi@arm.com NvFlags = 0x38, 707584SAli.Saidi@arm.com NvFlagsClr = 0x3C, 717584SAli.Saidi@arm.com ResetCtl = 0x40, 727584SAli.Saidi@arm.com PciCtl = 0x44, 737584SAli.Saidi@arm.com MciCtl = 0x48, 747584SAli.Saidi@arm.com Flash = 0x4C, 757584SAli.Saidi@arm.com Clcd = 0x50, 767584SAli.Saidi@arm.com ClcdSer = 0x54, 777584SAli.Saidi@arm.com Bootcs = 0x58, 787584SAli.Saidi@arm.com Clock24 = 0x5C, 797584SAli.Saidi@arm.com Misc = 0x60, 807584SAli.Saidi@arm.com IoSel = 0x70, 818524SAli.Saidi@ARM.com ProcId0 = 0x84, 828524SAli.Saidi@ARM.com ProcId1 = 0x88, 839958Smatt.evans@arm.com CfgData = 0xA0, 849958Smatt.evans@arm.com CfgCtrl = 0xA4, 858524SAli.Saidi@ARM.com CfgStat = 0xA8, 867584SAli.Saidi@arm.com TestOsc0 = 0xC0, 877584SAli.Saidi@arm.com TestOsc1 = 0xC4, 887584SAli.Saidi@arm.com TestOsc2 = 0xC8, 897584SAli.Saidi@arm.com TestOsc3 = 0xCC, 907584SAli.Saidi@arm.com TestOsc4 = 0xD0 917584SAli.Saidi@arm.com }; 927584SAli.Saidi@arm.com 937950SAli.Saidi@ARM.com // system lock value 947950SAli.Saidi@ARM.com BitUnion32(SysLockReg) 957950SAli.Saidi@ARM.com Bitfield<15,0> lockVal; 967950SAli.Saidi@ARM.com Bitfield<16> locked; 977950SAli.Saidi@ARM.com EndBitUnion(SysLockReg) 987950SAli.Saidi@ARM.com 997950SAli.Saidi@ARM.com SysLockReg sysLock; 1007950SAli.Saidi@ARM.com 1018281SAli.Saidi@ARM.com /** This register is used for smp booting. 1028281SAli.Saidi@ARM.com * The primary cpu writes the secondary start address here before 1038281SAli.Saidi@ARM.com * sends it a soft interrupt. The secondary cpu reads this register and if 1048281SAli.Saidi@ARM.com * it's non-zero it jumps to the address 1058281SAli.Saidi@ARM.com */ 1068281SAli.Saidi@ARM.com uint32_t flags; 1078281SAli.Saidi@ARM.com 1089958Smatt.evans@arm.com /** This register contains the result from a system control reg access 1099958Smatt.evans@arm.com */ 1109958Smatt.evans@arm.com uint32_t scData; 1119958Smatt.evans@arm.com 1127584SAli.Saidi@arm.com public: 1137584SAli.Saidi@arm.com typedef RealViewCtrlParams Params; 1147584SAli.Saidi@arm.com const Params * 1157584SAli.Saidi@arm.com params() const 1167584SAli.Saidi@arm.com { 1177584SAli.Saidi@arm.com return dynamic_cast<const Params *>(_params); 1187584SAli.Saidi@arm.com } 1197584SAli.Saidi@arm.com /** 1207584SAli.Saidi@arm.com * The constructor for RealView just registers itself with the MMU. 1217584SAli.Saidi@arm.com * @param p params structure 1227584SAli.Saidi@arm.com */ 1237584SAli.Saidi@arm.com RealViewCtrl(Params *p); 1247584SAli.Saidi@arm.com 1257584SAli.Saidi@arm.com /** 1267584SAli.Saidi@arm.com * Handle a read to the device 1277584SAli.Saidi@arm.com * @param pkt The memory request. 1287584SAli.Saidi@arm.com * @param data Where to put the data. 1297584SAli.Saidi@arm.com */ 1307584SAli.Saidi@arm.com virtual Tick read(PacketPtr pkt); 1317584SAli.Saidi@arm.com 1327584SAli.Saidi@arm.com /** 1337584SAli.Saidi@arm.com * All writes are simply ignored. 1347584SAli.Saidi@arm.com * @param pkt The memory request. 1357584SAli.Saidi@arm.com * @param data the data 1367584SAli.Saidi@arm.com */ 1377584SAli.Saidi@arm.com virtual Tick write(PacketPtr pkt); 1387584SAli.Saidi@arm.com 1397584SAli.Saidi@arm.com 1407584SAli.Saidi@arm.com virtual void serialize(std::ostream &os); 1417584SAli.Saidi@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 1427584SAli.Saidi@arm.com}; 1437584SAli.Saidi@arm.com 1447584SAli.Saidi@arm.com 1457584SAli.Saidi@arm.com#endif // __DEV_ARM_RV_HH__ 146