rv_ctrl.cc revision 8299:64a938a8b7fc 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/trace.hh"
41#include "dev/arm/rv_ctrl.hh"
42#include "mem/packet.hh"
43#include "mem/packet_access.hh"
44
45RealViewCtrl::RealViewCtrl(Params *p)
46    : BasicPioDevice(p), flags(0)
47{
48    pioSize = 0xD4;
49}
50
51Tick
52RealViewCtrl::read(PacketPtr pkt)
53{
54    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
55    assert(pkt->getSize() == 4);
56    Addr daddr = pkt->getAddr() - pioAddr;
57    pkt->allocate();
58
59    switch(daddr) {
60      case ProcId:
61        pkt->set(params()->proc_id);
62        break;
63      case Clock24:
64        Tick clk;
65        clk = (Tick)(curTick() / (24 * SimClock::Int::us));
66        pkt->set((uint32_t)(clk));
67        break;
68      case Clock100:
69        Tick clk100;
70        clk100 = (Tick)(curTick() / (100 * SimClock::Int::us));
71        pkt->set((uint32_t)(clk100));
72        break;
73      case Flash:
74        pkt->set<uint32_t>(0);
75        break;
76      case Clcd:
77        pkt->set<uint32_t>(0x00001F00);
78        break;
79      case Osc0:
80        pkt->set<uint32_t>(0x00012C5C);
81        break;
82      case Osc1:
83        pkt->set<uint32_t>(0x00002CC0);
84        break;
85      case Osc2:
86        pkt->set<uint32_t>(0x00002C75);
87        break;
88      case Osc3:
89        pkt->set<uint32_t>(0x00020211);
90        break;
91      case Osc4:
92        pkt->set<uint32_t>(0x00002C75);
93        break;
94      case Lock:
95        pkt->set<uint32_t>(sysLock);
96        break;
97      case Flags:
98        pkt->set<uint32_t>(flags);
99        break;
100      case IdReg:
101        pkt->set<uint32_t>(params()->idreg);
102        break;
103      default:
104        warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
105             daddr);
106        break;
107    }
108    pkt->makeAtomicResponse();
109    return pioDelay;
110
111}
112
113Tick
114RealViewCtrl::write(PacketPtr pkt)
115{
116    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
117
118    Addr daddr = pkt->getAddr() - pioAddr;
119    switch (daddr) {
120      case Flash:
121      case Clcd:
122      case Osc0:
123      case Osc1:
124      case Osc2:
125      case Osc3:
126      case Osc4:
127        break;
128      case Lock:
129        sysLock.lockVal = pkt->get<uint16_t>();
130        break;
131      case Flags:
132        flags = pkt->get<uint32_t>();
133        break;
134      default:
135        warn("Tried to write RVIO at offset %#x that doesn't exist\n",
136             daddr);
137        break;
138    }
139    pkt->makeAtomicResponse();
140    return pioDelay;
141}
142
143void
144RealViewCtrl::serialize(std::ostream &os)
145{
146    SERIALIZE_SCALAR(flags);
147}
148
149void
150RealViewCtrl::unserialize(Checkpoint *cp, const std::string &section)
151{
152    UNSERIALIZE_SCALAR(flags);
153}
154
155RealViewCtrl *
156RealViewCtrlParams::create()
157{
158    return new RealViewCtrl(this);
159}
160