rv_ctrl.cc revision 11011:2ca6c68fdd6c 
1/*
2 * Copyright (c) 2010,2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/trace.hh"
41#include "debug/RVCTRL.hh"
42#include "dev/arm/rv_ctrl.hh"
43#include "mem/packet.hh"
44#include "mem/packet_access.hh"
45#include "sim/voltage_domain.hh"
46
47RealViewCtrl::RealViewCtrl(Params *p)
48    : BasicPioDevice(p, 0xD4), flags(0), scData(0)
49{
50}
51
52Tick
53RealViewCtrl::read(PacketPtr pkt)
54{
55    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
56    assert(pkt->getSize() == 4);
57    Addr daddr = pkt->getAddr() - pioAddr;
58
59    switch(daddr) {
60      case ProcId0:
61        pkt->set(params()->proc_id0);
62        break;
63      case ProcId1:
64        pkt->set(params()->proc_id1);
65        break;
66      case Clock24:
67        Tick clk;
68        clk = SimClock::Float::MHz * curTick() * 24;
69        pkt->set((uint32_t)(clk));
70        break;
71      case Clock100:
72        Tick clk100;
73        clk100 = SimClock::Float::MHz * curTick() * 100;
74        pkt->set((uint32_t)(clk100));
75        break;
76      case Flash:
77        pkt->set<uint32_t>(0);
78        break;
79      case Clcd:
80        pkt->set<uint32_t>(0x00001F00);
81        break;
82      case Osc0:
83        pkt->set<uint32_t>(0x00012C5C);
84        break;
85      case Osc1:
86        pkt->set<uint32_t>(0x00002CC0);
87        break;
88      case Osc2:
89        pkt->set<uint32_t>(0x00002C75);
90        break;
91      case Osc3:
92        pkt->set<uint32_t>(0x00020211);
93        break;
94      case Osc4:
95        pkt->set<uint32_t>(0x00002C75);
96        break;
97      case Lock:
98        pkt->set<uint32_t>(sysLock);
99        break;
100      case Flags:
101        pkt->set<uint32_t>(flags);
102        break;
103      case IdReg:
104        pkt->set<uint32_t>(params()->idreg);
105        break;
106      case CfgStat:
107        pkt->set<uint32_t>(1);
108        break;
109      case CfgData:
110        pkt->set<uint32_t>(scData);
111        DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
112        break;
113      case CfgCtrl:
114        pkt->set<uint32_t>(0); // not busy
115        DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
116        break;
117      default:
118        warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
119             daddr);
120        pkt->set<uint32_t>(0);
121        break;
122    }
123    pkt->makeAtomicResponse();
124    return pioDelay;
125
126}
127
128Tick
129RealViewCtrl::write(PacketPtr pkt)
130{
131    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
132
133    Addr daddr = pkt->getAddr() - pioAddr;
134    switch (daddr) {
135      case Flash:
136      case Clcd:
137      case Osc0:
138      case Osc1:
139      case Osc2:
140      case Osc3:
141      case Osc4:
142        break;
143      case Lock:
144        sysLock.lockVal = pkt->get<uint16_t>();
145        break;
146      case Flags:
147        flags = pkt->get<uint32_t>();
148        break;
149      case FlagsClr:
150        flags = 0;
151        break;
152      case CfgData:
153        scData = pkt->get<uint32_t>();
154        break;
155      case CfgCtrl: {
156          // A request is being submitted to read/write the system control
157          // registers.  See
158          // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
159          CfgCtrlReg req = pkt->get<uint32_t>();
160          if (!req.start) {
161              DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n",
162                      req);
163              break;
164          }
165
166          auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK));
167          if (it_dev == devices.end()) {
168              warn_once("SCReg: Access to unknown device "
169                        "dcc%d:site%d:pos%d:fn%d:dev%d\n",
170                        req.dcc, req.site, req.pos, req.func, req.dev);
171              break;
172          }
173
174          // Service the request as a read or write depending on the
175          // wr bit in the control register.
176          Device &dev(*it_dev->second);
177          if (req.wr) {
178              DPRINTF(RVCTRL, "SCReg: Writing %#x (ctrlWr %#x)\n",
179                      scData, req);
180              dev.write(scData);
181
182          } else {
183              scData = dev.read();
184              DPRINTF(RVCTRL, "SCReg: Reading %#x (ctrlRd %#x)\n",
185                      scData, req);
186          }
187      } break;
188      case CfgStat:     // Weird to write this
189      default:
190        warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
191             daddr, pkt->get<uint32_t>());
192        break;
193    }
194    pkt->makeAtomicResponse();
195    return pioDelay;
196}
197
198void
199RealViewCtrl::serialize(CheckpointOut &cp) const
200{
201    SERIALIZE_SCALAR(flags);
202}
203
204void
205RealViewCtrl::unserialize(CheckpointIn &cp)
206{
207    UNSERIALIZE_SCALAR(flags);
208}
209
210void
211RealViewCtrl::registerDevice(DeviceFunc func, uint8_t site, uint8_t pos,
212                             uint8_t dcc, uint16_t dev,
213                             Device *handler)
214{
215    CfgCtrlReg addr = 0;
216    addr.func = func;
217    addr.site = site;
218    addr.pos = pos;
219    addr.dcc = dcc;
220    addr.dev = dev;
221
222    if (devices.find(addr) != devices.end()) {
223        fatal("Platform device dcc%d:site%d:pos%d:fn%d:dev%d "
224              "already registered.",
225              addr.dcc, addr.site, addr.pos, addr.func, addr.dev);
226    }
227
228    devices[addr] = handler;
229}
230
231
232RealViewOsc::RealViewOsc(RealViewOscParams *p)
233    : ClockDomain(p, p->voltage_domain),
234      RealViewCtrl::Device(*p->parent, RealViewCtrl::FUNC_OSC,
235                           p->site, p->position, p->dcc, p->device)
236{
237    if (SimClock::Float::s  / p->freq > UINT32_MAX) {
238        fatal("Oscillator frequency out of range: %f\n",
239            SimClock::Float::s  / p->freq / 1E6);
240    }
241
242    _clockPeriod = p->freq;
243}
244
245void
246RealViewOsc::startup()
247{
248    // Tell dependent object to set their clock frequency
249    for (auto m : members)
250        m->updateClockPeriod();
251}
252
253void
254RealViewOsc::serialize(CheckpointOut &cp) const
255{
256    SERIALIZE_SCALAR(_clockPeriod);
257}
258
259void
260RealViewOsc::unserialize(CheckpointIn &cp)
261{
262    UNSERIALIZE_SCALAR(_clockPeriod);
263}
264
265void
266RealViewOsc::clockPeriod(Tick clock_period)
267{
268    panic_if(clock_period == 0, "%s has a clock period of zero\n", name());
269
270    // Align all members to the current tick
271    for (auto m : members)
272        m->updateClockPeriod();
273
274    _clockPeriod = clock_period;
275
276    // inform any derived clocks they need to updated their period
277    for (auto m : children)
278        m->updateClockPeriod();
279}
280
281uint32_t
282RealViewOsc::read() const
283{
284    const uint32_t freq(SimClock::Float::s / _clockPeriod);
285    DPRINTF(RVCTRL, "Reading OSC frequency: %f MHz\n", freq / 1E6);
286    return freq;
287}
288
289void
290RealViewOsc::write(uint32_t freq)
291{
292    DPRINTF(RVCTRL, "Setting new OSC frequency: %f MHz\n", freq / 1E6);
293    clockPeriod(SimClock::Float::s / freq);
294}
295
296
297
298RealViewCtrl *
299RealViewCtrlParams::create()
300{
301    return new RealViewCtrl(this);
302}
303
304RealViewOsc *
305RealViewOscParams::create()
306{
307    return new RealViewOsc(this);
308}
309