rv_ctrl.cc revision 10905 
1/*
2 * Copyright (c) 2010,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/trace.hh"
41#include "debug/RVCTRL.hh"
42#include "dev/arm/rv_ctrl.hh"
43#include "mem/packet.hh"
44#include "mem/packet_access.hh"
45
46RealViewCtrl::RealViewCtrl(Params *p)
47    : BasicPioDevice(p, 0xD4), flags(0), scData(0)
48{
49}
50
51Tick
52RealViewCtrl::read(PacketPtr pkt)
53{
54    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
55    assert(pkt->getSize() == 4);
56    Addr daddr = pkt->getAddr() - pioAddr;
57
58    switch(daddr) {
59      case ProcId0:
60        pkt->set(params()->proc_id0);
61        break;
62      case ProcId1:
63        pkt->set(params()->proc_id1);
64        break;
65      case Clock24:
66        Tick clk;
67        clk = SimClock::Float::MHz * curTick() * 24;
68        pkt->set((uint32_t)(clk));
69        break;
70      case Clock100:
71        Tick clk100;
72        clk100 = SimClock::Float::MHz * curTick() * 100;
73        pkt->set((uint32_t)(clk100));
74        break;
75      case Flash:
76        pkt->set<uint32_t>(0);
77        break;
78      case Clcd:
79        pkt->set<uint32_t>(0x00001F00);
80        break;
81      case Osc0:
82        pkt->set<uint32_t>(0x00012C5C);
83        break;
84      case Osc1:
85        pkt->set<uint32_t>(0x00002CC0);
86        break;
87      case Osc2:
88        pkt->set<uint32_t>(0x00002C75);
89        break;
90      case Osc3:
91        pkt->set<uint32_t>(0x00020211);
92        break;
93      case Osc4:
94        pkt->set<uint32_t>(0x00002C75);
95        break;
96      case Lock:
97        pkt->set<uint32_t>(sysLock);
98        break;
99      case Flags:
100        pkt->set<uint32_t>(flags);
101        break;
102      case IdReg:
103        pkt->set<uint32_t>(params()->idreg);
104        break;
105      case CfgStat:
106        pkt->set<uint32_t>(1);
107        break;
108      case CfgData:
109        pkt->set<uint32_t>(scData);
110        DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
111        break;
112      case CfgCtrl:
113        pkt->set<uint32_t>(0); // not busy
114        DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
115        break;
116      default:
117        warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
118             daddr);
119        pkt->set<uint32_t>(0);
120        break;
121    }
122    pkt->makeAtomicResponse();
123    return pioDelay;
124
125}
126
127Tick
128RealViewCtrl::write(PacketPtr pkt)
129{
130    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
131
132    Addr daddr = pkt->getAddr() - pioAddr;
133    switch (daddr) {
134      case Flash:
135      case Clcd:
136      case Osc0:
137      case Osc1:
138      case Osc2:
139      case Osc3:
140      case Osc4:
141        break;
142      case Lock:
143        sysLock.lockVal = pkt->get<uint16_t>();
144        break;
145      case Flags:
146        flags = pkt->get<uint32_t>();
147        break;
148      case FlagsClr:
149        flags = 0;
150        break;
151      case CfgData:
152        scData = pkt->get<uint32_t>();
153        break;
154      case CfgCtrl: {
155          // A request is being submitted to read/write the system control
156          // registers.  See
157          // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
158          // For now, model as much of the OSC regs (can't find docs) as Linux
159          // seems to require (can't find docs); some clocks are deemed to be 0,
160          // giving all kinds of /0 problems booting Linux 3.9.  Return a
161          // vaguely plausible number within the range the device trees state:
162          uint32_t data = pkt->get<uint32_t>();
163          uint16_t dev = bits(data, 11, 0);
164          uint8_t pos = bits(data, 15, 12);
165          uint8_t site = bits(data, 17, 16);
166          uint8_t func = bits(data, 25, 20);
167          uint8_t dcc = bits(data, 29, 26);
168          bool wr = bits(data, 30);
169          bool start = bits(data, 31);
170
171          if (start) {
172              if (wr) {
173                  warn_once("SCReg: Writing %#x to dcc%d:site%d:pos%d:fn%d:dev%d\n",
174                          scData, dcc, site, pos, func, dev);
175                  // Only really support reading, for now!
176              } else {
177                  // Only deal with function 1 (oscillators) so far!
178                  if (dcc != 0 || pos != 0 || func != 1) {
179                      warn("SCReg: read from unknown area "
180                           "(dcc %d:site%d:pos%d:fn%d:dev%d)\n",
181                           dcc, site, pos, func, dev);
182                  } else {
183                      switch (site) {
184                        case 0: { // Motherboard regs
185                            switch(dev) {
186                              case 0: // MCC clk
187                                scData = 25000000;
188                                break;
189                              case 1: // CLCD clk
190                                scData = 25000000;
191                                break;
192                              case 2: // PeriphClk 24MHz
193                                scData = 24000000;
194                                break;
195                              default:
196                                scData = 0;
197                                warn("SCReg: read from unknown dev %d "
198                                     "(site%d:pos%d:fn%d)\n",
199                                     dev, site, pos, func);
200                            }
201                        } break;
202                        case 1: { // Coretile 1 regs
203                            switch(dev) {
204                              case 0: // CPU PLL ref
205                                scData = 50000000;
206                                break;
207                              case 4: // Muxed AXI master clock
208                                scData = 40000000;
209                                break;
210                              case 5: // HDLCD clk
211                                scData = 50000000;
212                                break;
213                              case 6: // SMB clock
214                                scData = 35000000;
215                                break;
216                              case 7: // SYS PLL (also used for pl011 UART!)
217                                scData = 40000000;
218                                break;
219                              case 8: // DDR PLL 40MHz fixed
220                                scData = 40000000;
221                                break;
222                              default:
223                                scData = 0;
224                                warn("SCReg: read from unknown dev %d "
225                                     "(site%d:pos%d:fn%d)\n",
226                                     dev, site, pos, func);
227                            }
228                        } break;
229                        default:
230                          warn("SCReg: Read from unknown site %d (pos%d:fn%d:dev%d)\n",
231                               site, pos, func, dev);
232                      }
233                      DPRINTF(RVCTRL, "SCReg: Will read %#x (ctrlWr %#x)\n", scData, data);
234                  }
235              }
236          } else {
237              DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", data);
238          }
239      } break;
240      case CfgStat:     // Weird to write this
241      default:
242        warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
243             daddr, pkt->get<uint32_t>());
244        break;
245    }
246    pkt->makeAtomicResponse();
247    return pioDelay;
248}
249
250void
251RealViewCtrl::serialize(CheckpointOut &cp) const
252{
253    SERIALIZE_SCALAR(flags);
254}
255
256void
257RealViewCtrl::unserialize(CheckpointIn &cp)
258{
259    UNSERIALIZE_SCALAR(flags);
260}
261
262RealViewCtrl *
263RealViewCtrlParams::create()
264{
265    return new RealViewCtrl(this);
266}
267