rtc_pl031.cc revision 8993 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/intmath.hh"
41#include "base/time.hh"
42#include "base/trace.hh"
43#include "debug/Checkpoint.hh"
44#include "debug/Timer.hh"
45#include "dev/arm/amba_device.hh"
46#include "dev/arm/rtc_pl031.hh"
47#include "dev/mc146818.hh"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50
51using namespace AmbaDev;
52
53PL031::PL031(Params *p)
54    : AmbaIntDevice(p), timeVal(mkutctime(&p->time)), lastWrittenTick(0),
55            loadVal(0), matchVal(0), rawInt(false), maskInt(false),
56            pendingInt(false), matchEvent(this)
57{
58    pioSize = 0xfff;
59}
60
61
62Tick
63PL031::read(PacketPtr pkt)
64{
65    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
66    assert(pkt->getSize() == 4);
67    Addr daddr = pkt->getAddr() - pioAddr;
68    pkt->allocate();
69    uint32_t data;
70
71    DPRINTF(Timer, "Reading from RTC at offset: %#x\n", daddr);
72
73    switch (daddr) {
74      case DataReg:
75        data = timeVal + ((curTick() - lastWrittenTick) / SimClock::Int::s);
76        break;
77      case MatchReg:
78        data = matchVal;
79        break;
80      case LoadReg:
81        data = loadVal;
82        break;
83      case ControlReg:
84        data = 1; // Always enabled otherwise there is no point
85        break;
86      case IntMask:
87        data = maskInt;
88        break;
89      case RawISR:
90        data = rawInt;
91        break;
92      case MaskedISR:
93        data = pendingInt;
94        break;
95      default:
96        if (AmbaDev::readId(pkt, ambaId, pioAddr)) {
97            // Hack for variable sized access
98            data = pkt->get<uint32_t>();
99            break;
100        }
101        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
102        break;
103    }
104
105    switch(pkt->getSize()) {
106      case 1:
107        pkt->set<uint8_t>(data);
108        break;
109      case 2:
110        pkt->set<uint16_t>(data);
111        break;
112      case 4:
113        pkt->set<uint32_t>(data);
114        break;
115      default:
116        panic("Uart read size too big?\n");
117        break;
118    }
119
120
121    pkt->makeAtomicResponse();
122    return pioDelay;
123}
124
125Tick
126PL031::write(PacketPtr pkt)
127{
128    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
129    assert(pkt->getSize() == 4);
130    Addr daddr = pkt->getAddr() - pioAddr;
131    pkt->allocate();
132    DPRINTF(Timer, "Writing to RTC at offset: %#x\n", daddr);
133
134    switch (daddr) {
135      case DataReg:
136        break;
137      case MatchReg:
138        matchVal = pkt->get<uint32_t>();
139        resyncMatch();
140        break;
141      case LoadReg:
142        lastWrittenTick = curTick();
143        timeVal = pkt->get<uint32_t>();
144        loadVal = timeVal;
145        resyncMatch();
146        break;
147      case ControlReg:
148        break; // Can't stop when started
149      case IntMask:
150        maskInt = pkt->get<uint32_t>();
151        break;
152      case IntClear:
153        if (pkt->get<uint32_t>()) {
154            rawInt = false;
155            pendingInt = false;
156        }
157        break;
158      default:
159        if (AmbaDev::readId(pkt, ambaId, pioAddr))
160            break;
161        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
162        break;
163    }
164
165    pkt->makeAtomicResponse();
166    return pioDelay;
167}
168
169void
170PL031::resyncMatch()
171{
172    DPRINTF(Timer, "Setting up new match event match=%d time=%d\n", matchVal,
173            timeVal);
174
175    uint32_t seconds_until = matchVal - timeVal;
176    Tick ticks_until = SimClock::Int::s * seconds_until;
177
178    if (matchEvent.scheduled()) {
179        DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
180        deschedule(matchEvent);
181    }
182    schedule(matchEvent, curTick() + ticks_until);
183    DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + ticks_until);
184}
185
186void
187PL031::counterMatch()
188{
189    DPRINTF(Timer, "Counter reached zero\n");
190
191    rawInt = true;
192    bool old_pending = pendingInt;
193    pendingInt = maskInt & rawInt;
194    if (pendingInt && !old_pending) {
195        DPRINTF(Timer, "-- Causing interrupt\n");
196        gic->sendInt(intNum);
197    }
198}
199
200void
201PL031::serialize(std::ostream &os)
202{
203    DPRINTF(Checkpoint, "Serializing Arm PL031\n");
204    SERIALIZE_SCALAR(timeVal);
205    SERIALIZE_SCALAR(lastWrittenTick);
206    SERIALIZE_SCALAR(loadVal);
207    SERIALIZE_SCALAR(matchVal);
208    SERIALIZE_SCALAR(rawInt);
209    SERIALIZE_SCALAR(maskInt);
210    SERIALIZE_SCALAR(pendingInt);
211
212    bool is_in_event = matchEvent.scheduled();
213    SERIALIZE_SCALAR(is_in_event);
214
215    Tick event_time;
216    if (is_in_event){
217        event_time = matchEvent.when();
218        SERIALIZE_SCALAR(event_time);
219    }
220}
221
222void
223PL031::unserialize(Checkpoint *cp, const std::string &section)
224{
225    DPRINTF(Checkpoint, "Unserializing Arm PL031\n");
226
227    UNSERIALIZE_SCALAR(timeVal);
228    UNSERIALIZE_SCALAR(lastWrittenTick);
229    UNSERIALIZE_SCALAR(loadVal);
230    UNSERIALIZE_SCALAR(matchVal);
231    UNSERIALIZE_SCALAR(rawInt);
232    UNSERIALIZE_SCALAR(maskInt);
233    UNSERIALIZE_SCALAR(pendingInt);
234
235    bool is_in_event;
236    UNSERIALIZE_SCALAR(is_in_event);
237
238    Tick event_time;
239    if (is_in_event){
240        UNSERIALIZE_SCALAR(event_time);
241        schedule(matchEvent, event_time);
242    }
243}
244
245
246
247PL031 *
248PL031Params::create()
249{
250    return new PL031(this);
251}
252