realview.hh revision 5834
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292665Ssaidi@eecs.umich.edu */ 302665Ssaidi@eecs.umich.edu 312SN/A/** 322SN/A * @file 332SN/A * Declaration of top level class for the T1000 platform chips. This class just 342SN/A * retains pointers to all its children so the children can communicate. 352SN/A */ 362SN/A 3775SN/A#ifndef __DEV_T1000_HH__ 382SN/A#define __DEV_T1000_HH__ 392439SN/A 402439SN/A#include "dev/platform.hh" 41603SN/A#include "params/T1000.hh" 422986Sgblack@eecs.umich.edu 43603SN/Aclass IdeController; 444762Snate@binkert.orgclass System; 452520SN/A 464762Snate@binkert.orgclass T1000 : public Platform 472378SN/A{ 482378SN/A public: 49722SN/A /** Pointer to the system */ 502521SN/A System *system; 512378SN/A 52312SN/A public: 531634SN/A typedef T1000Params Params; 542680Sktlim@umich.edu /** 551634SN/A * Constructor for the Tsunami Class. 562521SN/A * @param name name of the object 572378SN/A * @param s system the object belongs to 582378SN/A * @param intctrl pointer to the interrupt controller 59803SN/A */ 603960Sgblack@eecs.umich.edu T1000(const Params *p); 612378SN/A 623536Sgblack@eecs.umich.edu /** 633536Sgblack@eecs.umich.edu * Return the interrupting frequency to AlphaAccess 643536Sgblack@eecs.umich.edu * @return frequency of RTC interrupts 653536Sgblack@eecs.umich.edu */ 662SN/A virtual Tick intrFrequency(); 672SN/A 682SN/A /** 69603SN/A * Cause the cpu to post a serial interrupt to the CPU. 702901Ssaidi@eecs.umich.edu */ 712902Ssaidi@eecs.umich.edu virtual void postConsoleInt(); 722902Ssaidi@eecs.umich.edu 734762Snate@binkert.org /** 744762Snate@binkert.org * Clear a posted CPU interrupt 754762Snate@binkert.org */ 764762Snate@binkert.org virtual void clearConsoleInt(); 774762Snate@binkert.org 784762Snate@binkert.org /** 792901Ssaidi@eecs.umich.edu * Cause the chipset to post a cpi interrupt to the CPU. 802901Ssaidi@eecs.umich.edu */ 812901Ssaidi@eecs.umich.edu virtual void postPciInt(int line); 822901Ssaidi@eecs.umich.edu 832901Ssaidi@eecs.umich.edu /** 844762Snate@binkert.org * Clear a posted PCI->CPU interrupt 852901Ssaidi@eecs.umich.edu */ 862521SN/A virtual void clearPciInt(int line); 872SN/A 882SN/A 892680Sktlim@umich.edu virtual Addr pciToDma(Addr pciAddr) const; 905714Shsul@eecs.umich.edu 911806SN/A /** 925713Shsul@eecs.umich.edu * Calculate the configuration address given a bus/dev/func. 935713Shsul@eecs.umich.edu */ 945713Shsul@eecs.umich.edu virtual Addr calcPciConfigAddr(int bus, int dev, int func); 955713Shsul@eecs.umich.edu 965713Shsul@eecs.umich.edu /** 975714Shsul@eecs.umich.edu * Calculate the address for an IO location on the PCI bus. 981806SN/A */ 995714Shsul@eecs.umich.edu virtual Addr calcPciIOAddr(Addr addr); 1001806SN/A 1011806SN/A /** 1025714Shsul@eecs.umich.edu * Calculate the address for a memory location on the PCI bus. 1031806SN/A */ 104180SN/A virtual Addr calcPciMemAddr(Addr addr); 1052378SN/A}; 1062378SN/A 1072378SN/A#endif // __DEV_T1000_HH__ 1082378SN/A