realview.hh revision 3812
15390SN/A/* 25445SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Ali Saidi 295390SN/A */ 305390SN/A 315390SN/A/** 325445SN/A * @file 338232Snate@binkert.org * Declaration of top level class for the T1000 platform chips. This class just 345636Sgblack@eecs.umich.edu * retains pointers to all its children so the children can communicate. 355636Sgblack@eecs.umich.edu */ 365636Sgblack@eecs.umich.edu 375390SN/A#ifndef __DEV_T1000_HH__ 385390SN/A#define __DEV_T1000_HH__ 395390SN/A 405390SN/A#include "dev/platform.hh" 415390SN/A 425636Sgblack@eecs.umich.educlass IdeController; 435390SN/Aclass System; 445636Sgblack@eecs.umich.edu 455636Sgblack@eecs.umich.educlass T1000 : public Platform 465445SN/A{ 475445SN/A public: 485445SN/A /** Pointer to the system */ 495445SN/A System *system; 505445SN/A 515898Sgblack@eecs.umich.edu public: 525390SN/A /** 535390SN/A * Constructor for the Tsunami Class. 545390SN/A * @param name name of the object 555390SN/A * @param s system the object belongs to 565390SN/A * @param intctrl pointer to the interrupt controller 575390SN/A */ 585636Sgblack@eecs.umich.edu T1000(const std::string &name, System *s, IntrControl *intctrl); 595390SN/A 605390SN/A /** 615445SN/A * Return the interrupting frequency to AlphaAccess 625445SN/A * @return frequency of RTC interrupts 635445SN/A */ 645445SN/A virtual Tick intrFrequency(); 655445SN/A 665445SN/A /** 675445SN/A * Cause the cpu to post a serial interrupt to the CPU. 685445SN/A */ 695445SN/A virtual void postConsoleInt(); 705636Sgblack@eecs.umich.edu 715445SN/A /** 725898Sgblack@eecs.umich.edu * Clear a posted CPU interrupt 735390SN/A */ 745390SN/A virtual void clearConsoleInt(); 755636Sgblack@eecs.umich.edu 767903Shestness@cs.utexas.edu /** 7710905Sandreas.sandberg@arm.com * Cause the chipset to post a cpi interrupt to the CPU. 787903Shestness@cs.utexas.edu */ 797903Shestness@cs.utexas.edu virtual void postPciInt(int line); 807903Shestness@cs.utexas.edu 817903Shestness@cs.utexas.edu /** 827903Shestness@cs.utexas.edu * Clear a posted PCI->CPU interrupt 837903Shestness@cs.utexas.edu */ 8410905Sandreas.sandberg@arm.com virtual void clearPciInt(int line); 857903Shestness@cs.utexas.edu 867903Shestness@cs.utexas.edu 877903Shestness@cs.utexas.edu virtual Addr pciToDma(Addr pciAddr) const; 887903Shestness@cs.utexas.edu 897903Shestness@cs.utexas.edu /** 907903Shestness@cs.utexas.edu * Calculate the configuration address given a bus/dev/func. 915636Sgblack@eecs.umich.edu */ 925636Sgblack@eecs.umich.edu virtual Addr calcConfigAddr(int bus, int dev, int func); 935636Sgblack@eecs.umich.edu 945636Sgblack@eecs.umich.edu /** 955636Sgblack@eecs.umich.edu * Serialize this object to the given output stream. 96 * @param os The stream to serialize to. 97 */ 98 virtual void serialize(std::ostream &os); 99 100 /** 101 * Reconstruct the state of this object from a checkpoint. 102 * @param cp The checkpoint use. 103 * @param section The section name of this object 104 */ 105 virtual void unserialize(Checkpoint *cp, const std::string §ion); 106}; 107 108#endif // __DEV_T1000_HH__ 109