realview.hh revision 7090
15217Ssaidi@eecs.umich.edu/*
213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2009 ARM Limited
39920Syasuko.eckert@amd.com * All rights reserved
49428SAndreas.Sandberg@ARM.com *
59428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall
69428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual
79428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating
89428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software
99428SAndreas.Sandberg@ARM.com * licensed hereunder.  You may use the software subject to the license
109428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated
119428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software,
129428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form.
139428SAndreas.Sandberg@ARM.com *
149428SAndreas.Sandberg@ARM.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
155217Ssaidi@eecs.umich.edu * All rights reserved.
165217Ssaidi@eecs.umich.edu *
175217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
185217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are
195217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright
205217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
215217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
225217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
235217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution;
245217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its
255217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from
265217Ssaidi@eecs.umich.edu * this software without specific prior written permission.
275217Ssaidi@eecs.umich.edu *
285217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
295217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
305217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
315217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
325217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
335217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
345217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
355217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
365217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
375217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
385217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
395217Ssaidi@eecs.umich.edu *
405217Ssaidi@eecs.umich.edu * Authors: Ali Saidi
415217Ssaidi@eecs.umich.edu */
425217Ssaidi@eecs.umich.edu
435217Ssaidi@eecs.umich.edu/**
4411793Sbrandon.potter@amd.com * @file
4511793Sbrandon.potter@amd.com * Declaration of top level class for the Versatile platform chips. This class just
4613610Sgiacomo.gabrielli@arm.com * retains pointers to all its children so the children can communicate.
4711627Smichael.lebeane@amd.com */
4812334Sgabeblack@google.com
495217Ssaidi@eecs.umich.edu#ifndef __DEV_ARM_VERSATILE_HH__
506658Snate@binkert.org#define __DEV_ARM_VERSATILE_HH__
519441SAndreas.Sandberg@ARM.com
529441SAndreas.Sandberg@ARM.com#include "dev/platform.hh"
538232Snate@binkert.org#include "params/Versatile.hh"
5411627Smichael.lebeane@amd.com
5511627Smichael.lebeane@amd.comclass IdeController;
569441SAndreas.Sandberg@ARM.comclass System;
575217Ssaidi@eecs.umich.edu
585217Ssaidi@eecs.umich.educlass Versatile : public Platform
595217Ssaidi@eecs.umich.edu{
605217Ssaidi@eecs.umich.edu  public:
615217Ssaidi@eecs.umich.edu    /** Pointer to the system */
625217Ssaidi@eecs.umich.edu    System *system;
635217Ssaidi@eecs.umich.edu
645217Ssaidi@eecs.umich.edu  public:
6513557Sgabeblack@google.com    typedef VersatileParams Params;
6613557Sgabeblack@google.com    /**
675217Ssaidi@eecs.umich.edu     * Constructor for the Tsunami Class.
685217Ssaidi@eecs.umich.edu     * @param name name of the object
695217Ssaidi@eecs.umich.edu     * @param s system the object belongs to
705217Ssaidi@eecs.umich.edu     * @param intctrl pointer to the interrupt controller
715217Ssaidi@eecs.umich.edu     */
725217Ssaidi@eecs.umich.edu    Versatile(const Params *p);
735217Ssaidi@eecs.umich.edu
7413611Sgabeblack@google.com    /**
7513611Sgabeblack@google.com     * Return the interrupting frequency to AlphaAccess
765217Ssaidi@eecs.umich.edu     * @return frequency of RTC interrupts
775217Ssaidi@eecs.umich.edu     */
785217Ssaidi@eecs.umich.edu    virtual Tick intrFrequency();
795217Ssaidi@eecs.umich.edu
8012109SRekai.GonzalezAlberquilla@arm.com    /**
8112109SRekai.GonzalezAlberquilla@arm.com     * Cause the cpu to post a serial interrupt to the CPU.
8212109SRekai.GonzalezAlberquilla@arm.com     */
8312109SRekai.GonzalezAlberquilla@arm.com    virtual void postConsoleInt();
8412109SRekai.GonzalezAlberquilla@arm.com
8512109SRekai.GonzalezAlberquilla@arm.com    /**
8612109SRekai.GonzalezAlberquilla@arm.com     * Clear a posted CPU interrupt
8712109SRekai.GonzalezAlberquilla@arm.com     */
8812109SRekai.GonzalezAlberquilla@arm.com    virtual void clearConsoleInt();
8912109SRekai.GonzalezAlberquilla@arm.com
9013610Sgiacomo.gabrielli@arm.com    /**
9113610Sgiacomo.gabrielli@arm.com     * Cause the chipset to post a cpi interrupt to the CPU.
9213610Sgiacomo.gabrielli@arm.com     */
9313610Sgiacomo.gabrielli@arm.com    virtual void postPciInt(int line);
9413610Sgiacomo.gabrielli@arm.com
9513610Sgiacomo.gabrielli@arm.com    /**
9613610Sgiacomo.gabrielli@arm.com     * Clear a posted PCI->CPU interrupt
9713610Sgiacomo.gabrielli@arm.com     */
9813610Sgiacomo.gabrielli@arm.com    virtual void clearPciInt(int line);
9913610Sgiacomo.gabrielli@arm.com
10013610Sgiacomo.gabrielli@arm.com
1015217Ssaidi@eecs.umich.edu    virtual Addr pciToDma(Addr pciAddr) const;
10213557Sgabeblack@google.com
10313557Sgabeblack@google.com    /**
1045217Ssaidi@eecs.umich.edu     * Calculate the configuration address given a bus/dev/func.
1055217Ssaidi@eecs.umich.edu     */
1065217Ssaidi@eecs.umich.edu    virtual Addr calcPciConfigAddr(int bus, int dev, int func);
1075217Ssaidi@eecs.umich.edu
1085217Ssaidi@eecs.umich.edu    /**
1099920Syasuko.eckert@amd.com     * Calculate the address for an IO location on the PCI bus.
1109920Syasuko.eckert@amd.com     */
11113622Sgabeblack@google.com    virtual Addr calcPciIOAddr(Addr addr);
11213622Sgabeblack@google.com
1139920Syasuko.eckert@amd.com    /**
1149920Syasuko.eckert@amd.com     * Calculate the address for a memory location on the PCI bus.
1159920Syasuko.eckert@amd.com     */
1169920Syasuko.eckert@amd.com    virtual Addr calcPciMemAddr(Addr addr);
1177720Sgblack@eecs.umich.edu};
1187720Sgblack@eecs.umich.edu
1195712Shsul@eecs.umich.edu#endif // __DEV_ARM_VERSATILE_HH__
1205712Shsul@eecs.umich.edu