pl111.hh revision 9415:f5d159450dfb 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: William Wang
38 *          Ali Saidi
39 */
40
41
42/** @file
43 * Implementiation of a PL111 CLCD controller
44 */
45
46#ifndef __DEV_ARM_PL111_HH__
47#define __DEV_ARM_PL111_HH__
48
49#include <fstream>
50
51#include "dev/arm/amba_device.hh"
52#include "params/Pl111.hh"
53#include "sim/serialize.hh"
54
55class Gic;
56class VncInput;
57class Bitmap;
58
59class Pl111: public AmbaDmaDevice
60{
61  protected:
62    static const uint64_t AMBA_ID       = ULL(0xb105f00d00141111);
63    /** ARM PL111 register map*/
64    static const int LcdTiming0       = 0x000;
65    static const int LcdTiming1       = 0x004;
66    static const int LcdTiming2       = 0x008;
67    static const int LcdTiming3       = 0x00C;
68    static const int LcdUpBase        = 0x010;
69    static const int LcdLpBase        = 0x014;
70    static const int LcdControl       = 0x018;
71    static const int LcdImsc          = 0x01C;
72    static const int LcdRis           = 0x020;
73    static const int LcdMis           = 0x024;
74    static const int LcdIcr           = 0x028;
75    static const int LcdUpCurr        = 0x02C;
76    static const int LcdLpCurr        = 0x030;
77    static const int LcdPalette       = 0x200;
78    static const int CrsrImage        = 0x800;
79    static const int ClcdCrsrCtrl     = 0xC00;
80    static const int ClcdCrsrConfig   = 0xC04;
81    static const int ClcdCrsrPalette0 = 0xC08;
82    static const int ClcdCrsrPalette1 = 0xC0C;
83    static const int ClcdCrsrXY       = 0xC10;
84    static const int ClcdCrsrClip     = 0xC14;
85    static const int ClcdCrsrImsc     = 0xC20;
86    static const int ClcdCrsrIcr      = 0xC24;
87    static const int ClcdCrsrRis      = 0xC28;
88    static const int ClcdCrsrMis      = 0xC2C;
89
90    static const int LcdPaletteSize   = 128;
91    static const int CrsrImageSize    = 256;
92
93    static const int LcdMaxWidth      = 1024; // pixels per line
94    static const int LcdMaxHeight     = 768;  // lines per panel
95
96    static const int dmaSize            = 8;    // 64 bits
97    static const int maxOutstandingDma  = 16;   // 16 deep FIFO of 64 bits
98
99    static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
100
101    enum LcdMode {
102        bpp1 = 0,
103        bpp2,
104        bpp4,
105        bpp8,
106        bpp16,
107        bpp24,
108        bpp16m565,
109        bpp12
110    };
111
112    BitUnion8(InterruptReg)
113        Bitfield<1> underflow;
114        Bitfield<2> baseaddr;
115        Bitfield<3> vcomp;
116        Bitfield<4> ahbmaster;
117    EndBitUnion(InterruptReg)
118
119    BitUnion32(TimingReg0)
120        Bitfield<7,2> ppl;
121        Bitfield<15,8> hsw;
122        Bitfield<23,16> hfp;
123        Bitfield<31,24> hbp;
124    EndBitUnion(TimingReg0)
125
126    BitUnion32(TimingReg1)
127        Bitfield<9,0> lpp;
128        Bitfield<15,10> vsw;
129        Bitfield<23,16> vfp;
130        Bitfield<31,24> vbp;
131    EndBitUnion(TimingReg1)
132
133    BitUnion32(TimingReg2)
134        Bitfield<4,0> pcdlo;
135        Bitfield<5> clksel;
136        Bitfield<10,6> acb;
137        Bitfield<11> avs;
138        Bitfield<12> ihs;
139        Bitfield<13> ipc;
140        Bitfield<14> ioe;
141        Bitfield<25,16> cpl;
142        Bitfield<26> bcd;
143        Bitfield<31,27> pcdhi;
144    EndBitUnion(TimingReg2)
145
146    BitUnion32(TimingReg3)
147        Bitfield<6,0> led;
148        Bitfield<16> lee;
149    EndBitUnion(TimingReg3)
150
151    BitUnion32(ControlReg)
152        Bitfield<0> lcden;
153        Bitfield<3,1> lcdbpp;
154        Bitfield<4> lcdbw;
155        Bitfield<5> lcdtft;
156        Bitfield<6> lcdmono8;
157        Bitfield<7> lcddual;
158        Bitfield<8> bgr;
159        Bitfield<9> bebo;
160        Bitfield<10> bepo;
161        Bitfield<11> lcdpwr;
162        Bitfield<13,12> lcdvcomp;
163        Bitfield<16> watermark;
164    EndBitUnion(ControlReg)
165
166    /**
167     * Event wrapper for dmaDone()
168     *
169     * This event calls pushes its this pointer onto the freeDoneEvent
170     * vector and calls dmaDone() when triggered.
171     */
172    class DmaDoneEvent : public Event
173    {
174      private:
175        Pl111 &obj;
176
177      public:
178        DmaDoneEvent(Pl111 *_obj)
179            : Event(), obj(*_obj) {}
180
181        void process() {
182            obj.dmaDoneEventFree.push_back(this);
183            obj.dmaDone();
184        }
185
186        const std::string name() const {
187            return obj.name() + ".DmaDoneEvent";
188        }
189    };
190
191    /** Horizontal axis panel control register */
192    TimingReg0 lcdTiming0;
193
194    /** Vertical axis panel control register */
195    TimingReg1 lcdTiming1;
196
197    /** Clock and signal polarity control register */
198    TimingReg2 lcdTiming2;
199
200    /** Line end control register */
201    TimingReg3 lcdTiming3;
202
203    /** Upper panel frame base address register */
204    int lcdUpbase;
205
206    /** Lower panel frame base address register */
207    int lcdLpbase;
208
209    /** Control register */
210    ControlReg lcdControl;
211
212    /** Interrupt mask set/clear register */
213    InterruptReg lcdImsc;
214
215    /** Raw interrupt status register - const */
216    InterruptReg lcdRis;
217
218    /** Masked interrupt status register */
219    InterruptReg lcdMis;
220
221    /** 256x16-bit color palette registers
222     * 256 palette entries organized as 128 locations of two entries per word */
223    int lcdPalette[LcdPaletteSize];
224
225    /** Cursor image RAM register
226     * 256-word wide values defining images overlaid by the hw cursor mechanism */
227    int cursorImage[CrsrImageSize];
228
229    /** Cursor control register */
230    int clcdCrsrCtrl;
231
232    /** Cursor configuration register */
233    int clcdCrsrConfig;
234
235    /** Cursor palette registers */
236    int clcdCrsrPalette0;
237    int clcdCrsrPalette1;
238
239    /** Cursor XY position register */
240    int clcdCrsrXY;
241
242    /** Cursor clip position register */
243    int clcdCrsrClip;
244
245    /** Cursor interrupt mask set/clear register */
246    InterruptReg clcdCrsrImsc;
247
248    /** Cursor interrupt clear register */
249    InterruptReg clcdCrsrIcr;
250
251    /** Cursor raw interrupt status register - const */
252    InterruptReg clcdCrsrRis;
253
254    /** Cursor masked interrupt status register - const */
255    InterruptReg clcdCrsrMis;
256
257    /** Pixel clock */
258    Tick pixelClock;
259
260    /** VNC server */
261    VncInput *vnc;
262
263    /** Helper to write out bitmaps */
264    Bitmap *bmp;
265
266    /** Picture of what the current frame buffer looks like */
267    std::ostream *pic;
268
269    /** Frame buffer width - pixels per line */
270    uint16_t width;
271
272    /** Frame buffer height - lines per panel */
273    uint16_t height;
274
275    /** Bytes per pixel */
276    uint8_t bytesPerPixel;
277
278    /** CLCDC supports up to 1024x768 */
279    uint8_t *dmaBuffer;
280
281    /** Start time for frame buffer dma read */
282    Tick startTime;
283
284    /** Frame buffer base address */
285    Addr startAddr;
286
287    /** Frame buffer max address */
288    Addr maxAddr;
289
290    /** Frame buffer current address */
291    Addr curAddr;
292
293    /** DMA FIFO watermark */
294    int waterMark;
295
296    /** Number of pending dma reads */
297    int dmaPendingNum;
298
299    /** Send updated parameters to the vnc server */
300    void updateVideoParams();
301
302    /** DMA framebuffer read */
303    void readFramebuffer();
304
305    /** Generate dma framebuffer read event */
306    void generateReadEvent();
307
308    /** Function to generate interrupt */
309    void generateInterrupt();
310
311    /** fillFIFO event */
312    void fillFifo();
313
314    /** start the dmas off after power is enabled */
315    void startDma();
316
317    /** DMA done event */
318    void dmaDone();
319
320    /** DMA framebuffer read event */
321    EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent;
322
323    /** Fill fifo */
324    EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
325
326    /**@{*/
327    /**
328     * All pre-allocated DMA done events
329     *
330     * The PL111 model preallocates maxOutstandingDma number of
331     * DmaDoneEvents to avoid having to heap allocate every single
332     * event when it is needed. In order to keep track of which events
333     * are in flight and which are ready to be used, we use two
334     * different vectors. dmaDoneEventAll contains <i>all</i>
335     * DmaDoneEvents that the object may use, while dmaDoneEventFree
336     * contains a list of currently <i>unused</i> events. When an
337     * event needs to be scheduled, the last element of the
338     * dmaDoneEventFree is used and removed from the list. When an
339     * event fires, it is added to the end of the
340     * dmaEventFreeList. dmaDoneEventAll is never used except for in
341     * initialization and serialization.
342     */
343    std::vector<DmaDoneEvent> dmaDoneEventAll;
344
345    /** Unused DMA done events that are ready to be scheduled */
346    std::vector<DmaDoneEvent *> dmaDoneEventFree;
347    /**@}*/
348
349    /** Wrapper to create an event out of the interrupt */
350    EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
351
352  public:
353    typedef Pl111Params Params;
354
355    const Params *
356    params() const
357    {
358        return dynamic_cast<const Params *>(_params);
359    }
360    Pl111(const Params *p);
361    ~Pl111();
362
363    virtual Tick read(PacketPtr pkt);
364    virtual Tick write(PacketPtr pkt);
365
366    virtual void serialize(std::ostream &os);
367    virtual void unserialize(Checkpoint *cp, const std::string &section);
368
369    /**
370     * Determine the address ranges that this device responds to.
371     *
372     * @return a list of non-overlapping address ranges
373     */
374    AddrRangeList getAddrRanges() const;
375};
376
377#endif
378