pl111.hh revision 9395:bf428987f54e 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: William Wang
38 *          Ali Saidi
39 */
40
41
42/** @file
43 * Implementiation of a PL111 CLCD controller
44 */
45
46#ifndef __DEV_ARM_PL111_HH__
47#define __DEV_ARM_PL111_HH__
48
49#include <fstream>
50
51#include "dev/arm/amba_device.hh"
52#include "params/Pl111.hh"
53#include "sim/serialize.hh"
54
55class Gic;
56class VncInput;
57class Bitmap;
58
59class Pl111: public AmbaDmaDevice
60{
61  protected:
62    static const uint64_t AMBA_ID       = ULL(0xb105f00d00141111);
63    /** ARM PL111 register map*/
64    static const int LcdTiming0       = 0x000;
65    static const int LcdTiming1       = 0x004;
66    static const int LcdTiming2       = 0x008;
67    static const int LcdTiming3       = 0x00C;
68    static const int LcdUpBase        = 0x010;
69    static const int LcdLpBase        = 0x014;
70    static const int LcdControl       = 0x018;
71    static const int LcdImsc          = 0x01C;
72    static const int LcdRis           = 0x020;
73    static const int LcdMis           = 0x024;
74    static const int LcdIcr           = 0x028;
75    static const int LcdUpCurr        = 0x02C;
76    static const int LcdLpCurr        = 0x030;
77    static const int LcdPalette       = 0x200;
78    static const int CrsrImage        = 0x800;
79    static const int ClcdCrsrCtrl     = 0xC00;
80    static const int ClcdCrsrConfig   = 0xC04;
81    static const int ClcdCrsrPalette0 = 0xC08;
82    static const int ClcdCrsrPalette1 = 0xC0C;
83    static const int ClcdCrsrXY       = 0xC10;
84    static const int ClcdCrsrClip     = 0xC14;
85    static const int ClcdCrsrImsc     = 0xC20;
86    static const int ClcdCrsrIcr      = 0xC24;
87    static const int ClcdCrsrRis      = 0xC28;
88    static const int ClcdCrsrMis      = 0xC2C;
89
90    static const int LcdPaletteSize   = 128;
91    static const int CrsrImageSize    = 256;
92
93    static const int LcdMaxWidth      = 1024; // pixels per line
94    static const int LcdMaxHeight     = 768;  // lines per panel
95
96    static const int dmaSize            = 8;    // 64 bits
97    static const int maxOutstandingDma  = 16;   // 16 deep FIFO of 64 bits
98
99    enum LcdMode {
100        bpp1 = 0,
101        bpp2,
102        bpp4,
103        bpp8,
104        bpp16,
105        bpp24,
106        bpp16m565,
107        bpp12
108    };
109
110    BitUnion8(InterruptReg)
111        Bitfield<1> underflow;
112        Bitfield<2> baseaddr;
113        Bitfield<3> vcomp;
114        Bitfield<4> ahbmaster;
115    EndBitUnion(InterruptReg)
116
117    BitUnion32(TimingReg0)
118        Bitfield<7,2> ppl;
119        Bitfield<15,8> hsw;
120        Bitfield<23,16> hfp;
121        Bitfield<31,24> hbp;
122    EndBitUnion(TimingReg0)
123
124    BitUnion32(TimingReg1)
125        Bitfield<9,0> lpp;
126        Bitfield<15,10> vsw;
127        Bitfield<23,16> vfp;
128        Bitfield<31,24> vbp;
129    EndBitUnion(TimingReg1)
130
131    BitUnion32(TimingReg2)
132        Bitfield<4,0> pcdlo;
133        Bitfield<5> clksel;
134        Bitfield<10,6> acb;
135        Bitfield<11> avs;
136        Bitfield<12> ihs;
137        Bitfield<13> ipc;
138        Bitfield<14> ioe;
139        Bitfield<25,16> cpl;
140        Bitfield<26> bcd;
141        Bitfield<31,27> pcdhi;
142    EndBitUnion(TimingReg2)
143
144    BitUnion32(TimingReg3)
145        Bitfield<6,0> led;
146        Bitfield<16> lee;
147    EndBitUnion(TimingReg3)
148
149    BitUnion32(ControlReg)
150        Bitfield<0> lcden;
151        Bitfield<3,1> lcdbpp;
152        Bitfield<4> lcdbw;
153        Bitfield<5> lcdtft;
154        Bitfield<6> lcdmono8;
155        Bitfield<7> lcddual;
156        Bitfield<8> bgr;
157        Bitfield<9> bebo;
158        Bitfield<10> bepo;
159        Bitfield<11> lcdpwr;
160        Bitfield<13,12> lcdvcomp;
161        Bitfield<16> watermark;
162    EndBitUnion(ControlReg)
163
164    /**
165     * Event wrapper for dmaDone()
166     *
167     * This event calls pushes its this pointer onto the freeDoneEvent
168     * vector and calls dmaDone() when triggered.
169     */
170    class DmaDoneEvent : public Event
171    {
172      private:
173        Pl111 &obj;
174
175      public:
176        DmaDoneEvent(Pl111 *_obj)
177            : Event(), obj(*_obj) {}
178
179        void process() {
180            obj.dmaDoneEventFree.push_back(this);
181            obj.dmaDone();
182        }
183
184        const std::string name() const {
185            return obj.name() + ".DmaDoneEvent";
186        }
187    };
188
189    /** Horizontal axis panel control register */
190    TimingReg0 lcdTiming0;
191
192    /** Vertical axis panel control register */
193    TimingReg1 lcdTiming1;
194
195    /** Clock and signal polarity control register */
196    TimingReg2 lcdTiming2;
197
198    /** Line end control register */
199    TimingReg3 lcdTiming3;
200
201    /** Upper panel frame base address register */
202    int lcdUpbase;
203
204    /** Lower panel frame base address register */
205    int lcdLpbase;
206
207    /** Control register */
208    ControlReg lcdControl;
209
210    /** Interrupt mask set/clear register */
211    InterruptReg lcdImsc;
212
213    /** Raw interrupt status register - const */
214    InterruptReg lcdRis;
215
216    /** Masked interrupt status register */
217    InterruptReg lcdMis;
218
219    /** 256x16-bit color palette registers
220     * 256 palette entries organized as 128 locations of two entries per word */
221    int lcdPalette[LcdPaletteSize];
222
223    /** Cursor image RAM register
224     * 256-word wide values defining images overlaid by the hw cursor mechanism */
225    int cursorImage[CrsrImageSize];
226
227    /** Cursor control register */
228    int clcdCrsrCtrl;
229
230    /** Cursor configuration register */
231    int clcdCrsrConfig;
232
233    /** Cursor palette registers */
234    int clcdCrsrPalette0;
235    int clcdCrsrPalette1;
236
237    /** Cursor XY position register */
238    int clcdCrsrXY;
239
240    /** Cursor clip position register */
241    int clcdCrsrClip;
242
243    /** Cursor interrupt mask set/clear register */
244    InterruptReg clcdCrsrImsc;
245
246    /** Cursor interrupt clear register */
247    InterruptReg clcdCrsrIcr;
248
249    /** Cursor raw interrupt status register - const */
250    InterruptReg clcdCrsrRis;
251
252    /** Cursor masked interrupt status register - const */
253    InterruptReg clcdCrsrMis;
254
255    /** Pixel clock */
256    Tick pixelClock;
257
258    /** VNC server */
259    VncInput *vnc;
260
261    /** Helper to write out bitmaps */
262    Bitmap *bmp;
263
264    /** Picture of what the current frame buffer looks like */
265    std::ostream *pic;
266
267    /** Frame buffer width - pixels per line */
268    uint16_t width;
269
270    /** Frame buffer height - lines per panel */
271    uint16_t height;
272
273    /** Bytes per pixel */
274    uint8_t bytesPerPixel;
275
276    /** CLCDC supports up to 1024x768 */
277    uint8_t *dmaBuffer;
278
279    /** Start time for frame buffer dma read */
280    Tick startTime;
281
282    /** Frame buffer base address */
283    Addr startAddr;
284
285    /** Frame buffer max address */
286    Addr maxAddr;
287
288    /** Frame buffer current address */
289    Addr curAddr;
290
291    /** DMA FIFO watermark */
292    int waterMark;
293
294    /** Number of pending dma reads */
295    int dmaPendingNum;
296
297    /** Send updated parameters to the vnc server */
298    void updateVideoParams();
299
300    /** DMA framebuffer read */
301    void readFramebuffer();
302
303    /** Generate dma framebuffer read event */
304    void generateReadEvent();
305
306    /** Function to generate interrupt */
307    void generateInterrupt();
308
309    /** fillFIFO event */
310    void fillFifo();
311
312    /** start the dmas off after power is enabled */
313    void startDma();
314
315    /** DMA done event */
316    void dmaDone();
317
318    /** DMA framebuffer read event */
319    EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent;
320
321    /** Fill fifo */
322    EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
323
324    /**@{*/
325    /**
326     * All pre-allocated DMA done events
327     *
328     * The PL111 model preallocates maxOutstandingDma number of
329     * DmaDoneEvents to avoid having to heap allocate every single
330     * event when it is needed. In order to keep track of which events
331     * are in flight and which are ready to be used, we use two
332     * different vectors. dmaDoneEventAll contains <i>all</i>
333     * DmaDoneEvents that the object may use, while dmaDoneEventFree
334     * contains a list of currently <i>unused</i> events. When an
335     * event needs to be scheduled, the last element of the
336     * dmaDoneEventFree is used and removed from the list. When an
337     * event fires, it is added to the end of the
338     * dmaEventFreeList. dmaDoneEventAll is never used except for in
339     * initialization and serialization.
340     */
341    std::vector<DmaDoneEvent> dmaDoneEventAll;
342
343    /** Unused DMA done events that are ready to be scheduled */
344    std::vector<DmaDoneEvent *> dmaDoneEventFree;
345    /**@}*/
346
347    /** Wrapper to create an event out of the interrupt */
348    EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
349
350  public:
351    typedef Pl111Params Params;
352
353    const Params *
354    params() const
355    {
356        return dynamic_cast<const Params *>(_params);
357    }
358    Pl111(const Params *p);
359    ~Pl111();
360
361    virtual Tick read(PacketPtr pkt);
362    virtual Tick write(PacketPtr pkt);
363
364    virtual void serialize(std::ostream &os);
365    virtual void unserialize(Checkpoint *cp, const std::string &section);
366
367    /**
368     * Determine the address ranges that this device responds to.
369     *
370     * @return a list of non-overlapping address ranges
371     */
372    AddrRangeList getAddrRanges() const;
373};
374
375#endif
376