pl011.hh revision 9235:5aa4896ed55a 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementiation of a PL011 UART
46 */
47
48#ifndef __DEV_ARM_PL011_H__
49#define __DEV_ARM_PL011_H__
50
51#include "dev/io_device.hh"
52#include "dev/uart.hh"
53#include "params/Pl011.hh"
54
55class Gic;
56
57class Pl011 : public Uart
58{
59  protected:
60    static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
61    static const int UART_DR = 0x000;
62    static const int UART_FR = 0x018;
63    static const int UART_FR_CTS  = 0x001;
64    static const int UART_FR_TXFE = 0x080;
65    static const int UART_FR_RXFE = 0x010;
66    static const int UART_IBRD = 0x024;
67    static const int UART_FBRD = 0x028;
68    static const int UART_LCRH = 0x02C;
69    static const int UART_CR   = 0x030;
70    static const int UART_IFLS = 0x034;
71    static const int UART_IMSC = 0x038;
72    static const int UART_RIS  = 0x03C;
73    static const int UART_MIS  = 0x040;
74    static const int UART_ICR  = 0x044;
75
76    uint16_t control;
77
78    /** fractional baud rate divisor. Not used for anything but reporting
79     * written value */
80    uint16_t fbrd;
81
82    /** integer baud rate divisor. Not used for anything but reporting
83     * written value */
84    uint16_t ibrd;
85
86    /** Line control register. Not used for anything but reporting
87     * written value */
88    uint16_t lcrh;
89
90    /** interrupt fifo level register. Not used for anything but reporting
91     * written value */
92    uint16_t ifls;
93
94    BitUnion16(INTREG)
95        Bitfield<0> rimim;
96        Bitfield<1> ctsmim;
97        Bitfield<2> dcdmim;
98        Bitfield<3> dsrmim;
99        Bitfield<4> rxim;
100        Bitfield<5> txim;
101        Bitfield<6> rtim;
102        Bitfield<7> feim;
103        Bitfield<8> peim;
104        Bitfield<9> beim;
105        Bitfield<10> oeim;
106        Bitfield<15,11> rsvd;
107    EndBitUnion(INTREG)
108
109    /** interrupt mask register. */
110    INTREG imsc;
111
112    /** raw interrupt status register */
113    INTREG rawInt;
114
115    /** Masked interrupt status register */
116    INTREG maskInt;
117
118    /** Interrupt number to generate */
119    int intNum;
120
121    /** Gic to use for interrupting */
122    Gic *gic;
123
124    /** Should the simulation end on an EOT */
125    bool endOnEOT;
126
127    /** Delay before interrupting */
128    Tick intDelay;
129
130    /** Function to generate interrupt */
131    void generateInterrupt();
132
133    /** Wrapper to create an event out of the thing */
134    EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
135
136  public:
137   typedef Pl011Params Params;
138   const Params *
139    params() const
140    {
141        return dynamic_cast<const Params *>(_params);
142    }
143    Pl011(const Params *p);
144
145    virtual Tick read(PacketPtr pkt);
146    virtual Tick write(PacketPtr pkt);
147
148    /**
149     * Inform the uart that there is data available.
150     */
151    virtual void dataAvailable();
152
153
154    /**
155     * Return if we have an interrupt pending
156     * @return interrupt status
157     * @todo fix me when implementation improves
158     */
159    virtual bool intStatus() { return false; }
160
161    virtual void serialize(std::ostream &os);
162    virtual void unserialize(Checkpoint *cp, const std::string &section);
163
164};
165
166#endif //__DEV_ARM_PL011_H__
167