pl011.hh revision 7587:177151a54462
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43 44/** @file 45 * Implementiation of a PL011 UART 46 */ 47 48#ifndef __DEV_ARM_PL011_H__ 49#define __DEV_ARM_PL011_H__ 50 51#include "base/range.hh" 52#include "dev/io_device.hh" 53#include "dev/uart.hh" 54#include "params/Pl011.hh" 55 56class Gic; 57 58class Pl011 : public Uart 59{ 60 protected: 61 static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); 62 static const int UART_DR = 0x000; 63 static const int UART_FR = 0x018; 64 static const int UART_FR_CTS = 0x001; 65 static const int UART_FR_TXFE = 0x080; 66 static const int UART_FR_RXFE = 0x010; 67 static const int UART_IBRD = 0x024; 68 static const int UART_FBRD = 0x028; 69 static const int UART_LCRH = 0x02C; 70 static const int UART_CR = 0x030; 71 static const int UART_IFLS = 0x034; 72 static const int UART_IMSC = 0x038; 73 static const int UART_RIS = 0x03C; 74 static const int UART_MIS = 0x040; 75 static const int UART_ICR = 0x044; 76 77 uint16_t control; 78 79 /** fractional baud rate divisor. Not used for anything but reporting 80 * written value */ 81 uint16_t fbrd; 82 83 /** integer baud rate divisor. Not used for anything but reporting 84 * written value */ 85 uint16_t ibrd; 86 87 /** Line control register. Not used for anything but reporting 88 * written value */ 89 uint16_t lcrh; 90 91 /** interrupt fifo level register. Not used for anything but reporting 92 * written value */ 93 uint16_t ifls; 94 95 BitUnion16(INTREG) 96 Bitfield<0> rimim; 97 Bitfield<1> ctsmim; 98 Bitfield<2> dcdmim; 99 Bitfield<3> dsrmim; 100 Bitfield<4> rxim; 101 Bitfield<5> txim; 102 Bitfield<6> rtim; 103 Bitfield<7> feim; 104 Bitfield<8> peim; 105 Bitfield<9> beim; 106 Bitfield<10> oeim; 107 Bitfield<15,11> rsvd; 108 EndBitUnion(INTREG) 109 110 /** interrupt mask register. */ 111 INTREG imsc; 112 113 /** raw interrupt status register */ 114 INTREG rawInt; 115 116 /** Masked interrupt status register */ 117 INTREG maskInt; 118 119 /** Interrupt number to generate */ 120 int intNum; 121 122 /** Gic to use for interrupting */ 123 Gic *gic; 124 125 /** Should the simulation end on an EOT */ 126 bool endOnEOT; 127 128 /** Delay before interrupting */ 129 Tick intDelay; 130 131 /** Function to generate interrupt */ 132 void generateInterrupt(); 133 134 /** Wrapper to create an event out of the thing */ 135 EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent; 136 137 public: 138 typedef Pl011Params Params; 139 const Params * 140 params() const 141 { 142 return dynamic_cast<const Params *>(_params); 143 } 144 Pl011(const Params *p); 145 146 virtual Tick read(PacketPtr pkt); 147 virtual Tick write(PacketPtr pkt); 148 149 /** 150 * Inform the uart that there is data available. 151 */ 152 virtual void dataAvailable(); 153 154 155 /** 156 * Return if we have an interrupt pending 157 * @return interrupt status 158 * @todo fix me when implementation improves 159 */ 160 virtual bool intStatus() { return false; } 161 162 virtual void serialize(std::ostream &os); 163 virtual void unserialize(Checkpoint *cp, const std::string §ion); 164 165}; 166 167#endif //__DEV_ARM_PL011_H__ 168