pl011.hh revision 11168
110515SAli.Saidi@ARM.com/* 210515SAli.Saidi@ARM.com * Copyright (c) 2010-2015 ARM Limited 311860Sandreas.hansson@arm.com * All rights reserved 411860Sandreas.hansson@arm.com * 511860Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 610515SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 711860Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811860Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911860Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011860Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111860Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211860Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311860Sandreas.hansson@arm.com * 1410515SAli.Saidi@ARM.com * Copyright (c) 2005 The Regents of The University of Michigan 1510515SAli.Saidi@ARM.com * All rights reserved. 1611860Sandreas.hansson@arm.com * 1711860Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 1811860Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 1911860Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 2011860Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 2111860Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 2211860Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 2311860Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 2411860Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 2511860Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 2610636Snilay@cs.wisc.edu * this software without specific prior written permission. 2711860Sandreas.hansson@arm.com * 2811860Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911860Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011860Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111860Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211860Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311860Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411860Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510636Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611860Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711860Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811860Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911860Sandreas.hansson@arm.com * 4011860Sandreas.hansson@arm.com * Authors: Ali Saidi 4111860Sandreas.hansson@arm.com * Andreas Sandberg 4211860Sandreas.hansson@arm.com */ 4311860Sandreas.hansson@arm.com 4411860Sandreas.hansson@arm.com 4511860Sandreas.hansson@arm.com/** @file 4611860Sandreas.hansson@arm.com * Implementiation of a PL011 UART 4711860Sandreas.hansson@arm.com */ 4811860Sandreas.hansson@arm.com 4911860Sandreas.hansson@arm.com#ifndef __DEV_ARM_PL011_H__ 5011860Sandreas.hansson@arm.com#define __DEV_ARM_PL011_H__ 5111860Sandreas.hansson@arm.com 5211860Sandreas.hansson@arm.com#include "dev/arm/amba_device.hh" 5311860Sandreas.hansson@arm.com#include "dev/uart.hh" 5411860Sandreas.hansson@arm.com 5511860Sandreas.hansson@arm.comclass BaseGic; 5611860Sandreas.hansson@arm.comstruct Pl011Params; 5711860Sandreas.hansson@arm.com 5811860Sandreas.hansson@arm.comclass Pl011 : public Uart, public AmbaDevice 5911860Sandreas.hansson@arm.com{ 6011860Sandreas.hansson@arm.com public: 6111860Sandreas.hansson@arm.com Pl011(const Pl011Params *p); 6211860Sandreas.hansson@arm.com 6311860Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 6411860Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 6511860Sandreas.hansson@arm.com 6611336Sandreas.hansson@arm.com public: // PioDevice 6711860Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 6811860Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 6911860Sandreas.hansson@arm.com 7011860Sandreas.hansson@arm.com public: // Uart 7111860Sandreas.hansson@arm.com void dataAvailable() override; 7211860Sandreas.hansson@arm.com 7311860Sandreas.hansson@arm.com 7411860Sandreas.hansson@arm.com protected: // Interrupt handling 7511860Sandreas.hansson@arm.com /** Function to generate interrupt */ 7611860Sandreas.hansson@arm.com void generateInterrupt(); 7711860Sandreas.hansson@arm.com 7811860Sandreas.hansson@arm.com /** 7911860Sandreas.hansson@arm.com * Assign new interrupt values and update interrupt signals 8011860Sandreas.hansson@arm.com * 8111860Sandreas.hansson@arm.com * A new interrupt is scheduled signalled if the set of unmasked 8211860Sandreas.hansson@arm.com * interrupts goes empty to non-empty. Conversely, if the set of 8311860Sandreas.hansson@arm.com * unmasked interrupts goes from non-empty to empty, the interrupt 8411860Sandreas.hansson@arm.com * signal is cleared. 8511860Sandreas.hansson@arm.com * 8611860Sandreas.hansson@arm.com * @param ints New <i>raw</i> interrupt status 8711860Sandreas.hansson@arm.com * @param mask New interrupt mask 8811860Sandreas.hansson@arm.com */ 8911860Sandreas.hansson@arm.com void setInterrupts(uint16_t ints, uint16_t mask); 9011860Sandreas.hansson@arm.com /** 9111860Sandreas.hansson@arm.com * Convenience function to update the interrupt mask 9211860Sandreas.hansson@arm.com * 9311860Sandreas.hansson@arm.com * @see setInterrupts 9411860Sandreas.hansson@arm.com * @param mask New interrupt mask 9511860Sandreas.hansson@arm.com */ 9611860Sandreas.hansson@arm.com void setInterruptMask(uint16_t mask) { setInterrupts(rawInt, mask); } 9711860Sandreas.hansson@arm.com /** 9811860Sandreas.hansson@arm.com * Convenience function to raise a new interrupt 9910515SAli.Saidi@ARM.com * 10011860Sandreas.hansson@arm.com * @see setInterrupts 10111860Sandreas.hansson@arm.com * @param ints Set of interrupts to raise 10210515SAli.Saidi@ARM.com */ 10310515SAli.Saidi@ARM.com void raiseInterrupts(uint16_t ints) { setInterrupts(rawInt | ints, imsc); } 10410515SAli.Saidi@ARM.com /** 10510515SAli.Saidi@ARM.com * Convenience function to clear interrupts 10610515SAli.Saidi@ARM.com * 10710515SAli.Saidi@ARM.com * @see setInterrupts 10811860Sandreas.hansson@arm.com * @param ints Set of interrupts to clear 10910515SAli.Saidi@ARM.com */ 11010515SAli.Saidi@ARM.com void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); } 11110515SAli.Saidi@ARM.com 11210515SAli.Saidi@ARM.com /** Masked interrupt status register */ 11310515SAli.Saidi@ARM.com const inline uint16_t maskInt() const { return rawInt & imsc; } 11410515SAli.Saidi@ARM.com 11511860Sandreas.hansson@arm.com /** Wrapper to create an event out of the thing */ 11611860Sandreas.hansson@arm.com EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent; 11711860Sandreas.hansson@arm.com 11811860Sandreas.hansson@arm.com protected: // Registers 11911860Sandreas.hansson@arm.com static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); 12011860Sandreas.hansson@arm.com static const int UART_DR = 0x000; 12111860Sandreas.hansson@arm.com static const int UART_FR = 0x018; 12211754Sandreas.hansson@arm.com static const int UART_FR_CTS = 0x001; 12311860Sandreas.hansson@arm.com static const int UART_FR_TXFE = 0x080; 12411860Sandreas.hansson@arm.com static const int UART_FR_RXFE = 0x010; 12511860Sandreas.hansson@arm.com static const int UART_IBRD = 0x024; 12611860Sandreas.hansson@arm.com static const int UART_FBRD = 0x028; 12711860Sandreas.hansson@arm.com static const int UART_LCRH = 0x02C; 12811860Sandreas.hansson@arm.com static const int UART_CR = 0x030; 12911860Sandreas.hansson@arm.com static const int UART_IFLS = 0x034; 13011860Sandreas.hansson@arm.com static const int UART_IMSC = 0x038; 13111860Sandreas.hansson@arm.com static const int UART_RIS = 0x03C; 13211860Sandreas.hansson@arm.com static const int UART_MIS = 0x040; 13311860Sandreas.hansson@arm.com static const int UART_ICR = 0x044; 13411860Sandreas.hansson@arm.com 13511860Sandreas.hansson@arm.com static const uint16_t UART_RIINTR = 1 << 0; 13611860Sandreas.hansson@arm.com static const uint16_t UART_CTSINTR = 1 << 1; 13711606Sandreas.sandberg@arm.com static const uint16_t UART_CDCINTR = 1 << 2; 13810515SAli.Saidi@ARM.com static const uint16_t UART_DSRINTR = 1 << 3; 13910515SAli.Saidi@ARM.com static const uint16_t UART_RXINTR = 1 << 4; 14010515SAli.Saidi@ARM.com static const uint16_t UART_TXINTR = 1 << 5; 14110515SAli.Saidi@ARM.com static const uint16_t UART_RTINTR = 1 << 6; 14210515SAli.Saidi@ARM.com static const uint16_t UART_FEINTR = 1 << 7; 14310515SAli.Saidi@ARM.com static const uint16_t UART_PEINTR = 1 << 8; 14410515SAli.Saidi@ARM.com static const uint16_t UART_BEINTR = 1 << 9; 14510515SAli.Saidi@ARM.com static const uint16_t UART_OEINTR = 1 << 10; 14610515SAli.Saidi@ARM.com 14710515SAli.Saidi@ARM.com uint16_t control; 14810515SAli.Saidi@ARM.com 14910515SAli.Saidi@ARM.com /** fractional baud rate divisor. Not used for anything but reporting 15010515SAli.Saidi@ARM.com * written value */ 15110515SAli.Saidi@ARM.com uint16_t fbrd; 15210515SAli.Saidi@ARM.com 15310515SAli.Saidi@ARM.com /** integer baud rate divisor. Not used for anything but reporting 15410515SAli.Saidi@ARM.com * written value */ 15510515SAli.Saidi@ARM.com uint16_t ibrd; 15610515SAli.Saidi@ARM.com 15710515SAli.Saidi@ARM.com /** Line control register. Not used for anything but reporting 15810515SAli.Saidi@ARM.com * written value */ 15910515SAli.Saidi@ARM.com uint16_t lcrh; 16010515SAli.Saidi@ARM.com 16110515SAli.Saidi@ARM.com /** interrupt fifo level register. Not used for anything but reporting 16210515SAli.Saidi@ARM.com * written value */ 16311860Sandreas.hansson@arm.com uint16_t ifls; 16411860Sandreas.hansson@arm.com 16511860Sandreas.hansson@arm.com /** interrupt mask register. */ 16611860Sandreas.hansson@arm.com uint16_t imsc; 16711860Sandreas.hansson@arm.com 16811860Sandreas.hansson@arm.com /** raw interrupt status register */ 16911860Sandreas.hansson@arm.com uint16_t rawInt; 17011860Sandreas.hansson@arm.com 17111860Sandreas.hansson@arm.com protected: // Configuration 17211860Sandreas.hansson@arm.com /** Gic to use for interrupting */ 17311860Sandreas.hansson@arm.com BaseGic * const gic; 17411860Sandreas.hansson@arm.com 17511860Sandreas.hansson@arm.com /** Should the simulation end on an EOT */ 17611860Sandreas.hansson@arm.com const bool endOnEOT; 17711860Sandreas.hansson@arm.com 17811860Sandreas.hansson@arm.com /** Interrupt number to generate */ 17911860Sandreas.hansson@arm.com const int intNum; 18011860Sandreas.hansson@arm.com 18111860Sandreas.hansson@arm.com /** Delay before interrupting */ 18211860Sandreas.hansson@arm.com const Tick intDelay; 18311860Sandreas.hansson@arm.com}; 18411860Sandreas.hansson@arm.com 18511860Sandreas.hansson@arm.com#endif //__DEV_ARM_PL011_H__ 18611860Sandreas.hansson@arm.com