pl011.hh revision 10718:4ed87af2930f
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2010-2015 ARM Limited 38466Snilay@cs.wisc.edu * All rights reserved 45086Sgblack@eecs.umich.edu * 55086Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 137087Snate@binkert.org * 145086Sgblack@eecs.umich.edu * Copyright (c) 2005 The Regents of The University of Michigan 157087Snate@binkert.org * All rights reserved. 167087Snate@binkert.org * 177087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 187087Snate@binkert.org * modification, are permitted provided that the following conditions are 197087Snate@binkert.org * met: redistributions of source code must retain the above copyright 207087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 217087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 227087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 235086Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247087Snate@binkert.org * neither the name of the copyright holders nor the names of its 255086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 265086Sgblack@eecs.umich.edu * this software without specific prior written permission. 275086Sgblack@eecs.umich.edu * 285086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395086Sgblack@eecs.umich.edu * 405086Sgblack@eecs.umich.edu * Authors: Ali Saidi 415647Sgblack@eecs.umich.edu * Andreas Sandberg 428466Snilay@cs.wisc.edu */ 438466Snilay@cs.wisc.edu 445086Sgblack@eecs.umich.edu 455135Sgblack@eecs.umich.edu/** @file 465647Sgblack@eecs.umich.edu * Implementiation of a PL011 UART 475234Sgblack@eecs.umich.edu */ 485086Sgblack@eecs.umich.edu 495086Sgblack@eecs.umich.edu#ifndef __DEV_ARM_PL011_H__ 505086Sgblack@eecs.umich.edu#define __DEV_ARM_PL011_H__ 517707Sgblack@eecs.umich.edu 527707Sgblack@eecs.umich.edu#include "dev/arm/amba_device.hh" 537707Sgblack@eecs.umich.edu#include "dev/uart.hh" 545086Sgblack@eecs.umich.edu 555086Sgblack@eecs.umich.educlass BaseGic; 565086Sgblack@eecs.umich.edustruct Pl011Params; 575135Sgblack@eecs.umich.edu 585135Sgblack@eecs.umich.educlass Pl011 : public Uart, public AmbaDevice 595135Sgblack@eecs.umich.edu{ 606048Sgblack@eecs.umich.edu public: 616048Sgblack@eecs.umich.edu Pl011(const Pl011Params *p); 626048Sgblack@eecs.umich.edu 636048Sgblack@eecs.umich.edu void serialize(std::ostream &os) M5_ATTR_OVERRIDE; 646048Sgblack@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE; 656048Sgblack@eecs.umich.edu 667720Sgblack@eecs.umich.edu public: // PioDevice 677720Sgblack@eecs.umich.edu Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; 687720Sgblack@eecs.umich.edu Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; 697720Sgblack@eecs.umich.edu 705135Sgblack@eecs.umich.edu public: // Uart 715135Sgblack@eecs.umich.edu void dataAvailable() M5_ATTR_OVERRIDE; 725135Sgblack@eecs.umich.edu 735135Sgblack@eecs.umich.edu 745135Sgblack@eecs.umich.edu protected: // Interrupt handling 755135Sgblack@eecs.umich.edu /** Function to generate interrupt */ 765135Sgblack@eecs.umich.edu void generateInterrupt(); 775135Sgblack@eecs.umich.edu 785135Sgblack@eecs.umich.edu /** 795135Sgblack@eecs.umich.edu * Assign new interrupt values and update interrupt signals 805135Sgblack@eecs.umich.edu * 815135Sgblack@eecs.umich.edu * A new interrupt is scheduled signalled if the set of unmasked 825135Sgblack@eecs.umich.edu * interrupts goes empty to non-empty. Conversely, if the set of 835135Sgblack@eecs.umich.edu * unmasked interrupts goes from non-empty to empty, the interrupt 845135Sgblack@eecs.umich.edu * signal is cleared. 855135Sgblack@eecs.umich.edu * 865135Sgblack@eecs.umich.edu * @param ints New <i>raw</i> interrupt status 875264Sgblack@eecs.umich.edu * @param mask New interrupt mask 885135Sgblack@eecs.umich.edu */ 895135Sgblack@eecs.umich.edu void setInterrupts(uint16_t ints, uint16_t mask); 905135Sgblack@eecs.umich.edu /** 915135Sgblack@eecs.umich.edu * Convenience function to update the interrupt mask 925141Sgblack@eecs.umich.edu * 935141Sgblack@eecs.umich.edu * @see setInterrupts 945141Sgblack@eecs.umich.edu * @param mask New interrupt mask 955141Sgblack@eecs.umich.edu */ 965141Sgblack@eecs.umich.edu void setInterruptMask(uint16_t mask) { setInterrupts(rawInt, mask); } 975141Sgblack@eecs.umich.edu /** 985141Sgblack@eecs.umich.edu * Convenience function to raise a new interrupt 995141Sgblack@eecs.umich.edu * 1005141Sgblack@eecs.umich.edu * @see setInterrupts 1015182Sgblack@eecs.umich.edu * @param ints Set of interrupts to raise 1025141Sgblack@eecs.umich.edu */ 1035141Sgblack@eecs.umich.edu void raiseInterrupts(uint16_t ints) { setInterrupts(rawInt | ints, imsc); } 1045141Sgblack@eecs.umich.edu /** 1055141Sgblack@eecs.umich.edu * Convenience function to clear interrupts 1065141Sgblack@eecs.umich.edu * 1075141Sgblack@eecs.umich.edu * @see setInterrupts 1085135Sgblack@eecs.umich.edu * @param ints Set of interrupts to clear 1095141Sgblack@eecs.umich.edu */ 1105141Sgblack@eecs.umich.edu void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); } 1115141Sgblack@eecs.umich.edu 1125141Sgblack@eecs.umich.edu /** Masked interrupt status register */ 1135141Sgblack@eecs.umich.edu const inline uint16_t maskInt() const { return rawInt & imsc; } 1145141Sgblack@eecs.umich.edu 1155141Sgblack@eecs.umich.edu /** Wrapper to create an event out of the thing */ 1165141Sgblack@eecs.umich.edu EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent; 1175141Sgblack@eecs.umich.edu 1185141Sgblack@eecs.umich.edu protected: // Registers 1195141Sgblack@eecs.umich.edu static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); 1205141Sgblack@eecs.umich.edu static const int UART_DR = 0x000; 1215135Sgblack@eecs.umich.edu static const int UART_FR = 0x018; 1225141Sgblack@eecs.umich.edu static const int UART_FR_CTS = 0x001; 1235141Sgblack@eecs.umich.edu static const int UART_FR_TXFE = 0x080; 1245135Sgblack@eecs.umich.edu static const int UART_FR_RXFE = 0x010; 1255141Sgblack@eecs.umich.edu static const int UART_IBRD = 0x024; 1265141Sgblack@eecs.umich.edu static const int UART_FBRD = 0x028; 1275141Sgblack@eecs.umich.edu static const int UART_LCRH = 0x02C; 1285141Sgblack@eecs.umich.edu static const int UART_CR = 0x030; 1295135Sgblack@eecs.umich.edu static const int UART_IFLS = 0x034; 1305141Sgblack@eecs.umich.edu static const int UART_IMSC = 0x038; 1315141Sgblack@eecs.umich.edu static const int UART_RIS = 0x03C; 1325141Sgblack@eecs.umich.edu static const int UART_MIS = 0x040; 1335141Sgblack@eecs.umich.edu static const int UART_ICR = 0x044; 1345141Sgblack@eecs.umich.edu 1355141Sgblack@eecs.umich.edu static const uint16_t UART_RIINTR = 1 << 0; 1365141Sgblack@eecs.umich.edu static const uint16_t UART_CTSINTR = 1 << 1; 1375141Sgblack@eecs.umich.edu static const uint16_t UART_CDCINTR = 1 << 2; 1385141Sgblack@eecs.umich.edu static const uint16_t UART_DSRINTR = 1 << 3; 1395141Sgblack@eecs.umich.edu static const uint16_t UART_RXINTR = 1 << 4; 1405141Sgblack@eecs.umich.edu static const uint16_t UART_TXINTR = 1 << 5; 1415141Sgblack@eecs.umich.edu static const uint16_t UART_RTINTR = 1 << 6; 1425264Sgblack@eecs.umich.edu static const uint16_t UART_FEINTR = 1 << 7; 1435141Sgblack@eecs.umich.edu static const uint16_t UART_PEINTR = 1 << 8; 1445141Sgblack@eecs.umich.edu static const uint16_t UART_BEINTR = 1 << 9; 1455141Sgblack@eecs.umich.edu static const uint16_t UART_OEINTR = 1 << 10; 1465141Sgblack@eecs.umich.edu 1475141Sgblack@eecs.umich.edu uint16_t control; 1485141Sgblack@eecs.umich.edu 1495141Sgblack@eecs.umich.edu /** fractional baud rate divisor. Not used for anything but reporting 1505141Sgblack@eecs.umich.edu * written value */ 1515141Sgblack@eecs.umich.edu uint16_t fbrd; 1525141Sgblack@eecs.umich.edu 1535141Sgblack@eecs.umich.edu /** integer baud rate divisor. Not used for anything but reporting 1545141Sgblack@eecs.umich.edu * written value */ 1555141Sgblack@eecs.umich.edu uint16_t ibrd; 1565141Sgblack@eecs.umich.edu 1575141Sgblack@eecs.umich.edu /** Line control register. Not used for anything but reporting 1585141Sgblack@eecs.umich.edu * written value */ 1595141Sgblack@eecs.umich.edu uint16_t lcrh; 1605135Sgblack@eecs.umich.edu 1615135Sgblack@eecs.umich.edu /** interrupt fifo level register. Not used for anything but reporting 1625135Sgblack@eecs.umich.edu * written value */ 1635360Sgblack@eecs.umich.edu uint16_t ifls; 1645360Sgblack@eecs.umich.edu 1655360Sgblack@eecs.umich.edu /** interrupt mask register. */ 1665360Sgblack@eecs.umich.edu uint16_t imsc; 1675360Sgblack@eecs.umich.edu 1685360Sgblack@eecs.umich.edu /** raw interrupt status register */ 1695647Sgblack@eecs.umich.edu uint16_t rawInt; 1705647Sgblack@eecs.umich.edu 1715647Sgblack@eecs.umich.edu protected: // Configuration 1725360Sgblack@eecs.umich.edu /** Gic to use for interrupting */ 1735647Sgblack@eecs.umich.edu BaseGic * const gic; 1745647Sgblack@eecs.umich.edu 1755647Sgblack@eecs.umich.edu /** Should the simulation end on an EOT */ 1769157Sandreas.hansson@arm.com const bool endOnEOT; 1775141Sgblack@eecs.umich.edu 1785141Sgblack@eecs.umich.edu /** Interrupt number to generate */ 1795141Sgblack@eecs.umich.edu const int intNum; 1805141Sgblack@eecs.umich.edu 1815141Sgblack@eecs.umich.edu /** Delay before interrupting */ 1825141Sgblack@eecs.umich.edu const Tick intDelay; 1835135Sgblack@eecs.umich.edu}; 1845135Sgblack@eecs.umich.edu 1855135Sgblack@eecs.umich.edu#endif //__DEV_ARM_PL011_H__ 1865135Sgblack@eecs.umich.edu