pl011.hh revision 9338
17584SAli.Saidi@arm.com/* 27584SAli.Saidi@arm.com * Copyright (c) 2010 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 157584SAli.Saidi@arm.com * All rights reserved. 167584SAli.Saidi@arm.com * 177584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 187584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 197584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 207584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 217584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 227584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 237584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 247584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 257584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 267584SAli.Saidi@arm.com * this software without specific prior written permission. 277584SAli.Saidi@arm.com * 287584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397584SAli.Saidi@arm.com * 407584SAli.Saidi@arm.com * Authors: Ali Saidi 417584SAli.Saidi@arm.com */ 427584SAli.Saidi@arm.com 437584SAli.Saidi@arm.com 447584SAli.Saidi@arm.com/** @file 457584SAli.Saidi@arm.com * Implementiation of a PL011 UART 467584SAli.Saidi@arm.com */ 477584SAli.Saidi@arm.com 487584SAli.Saidi@arm.com#ifndef __DEV_ARM_PL011_H__ 497584SAli.Saidi@arm.com#define __DEV_ARM_PL011_H__ 507584SAli.Saidi@arm.com 519338SAndreas.Sandberg@arm.com#include "base/bitfield.hh" 529338SAndreas.Sandberg@arm.com#include "base/bitunion.hh" 537584SAli.Saidi@arm.com#include "dev/io_device.hh" 547584SAli.Saidi@arm.com#include "dev/uart.hh" 557584SAli.Saidi@arm.com#include "params/Pl011.hh" 567584SAli.Saidi@arm.com 577584SAli.Saidi@arm.comclass Gic; 587584SAli.Saidi@arm.com 597584SAli.Saidi@arm.comclass Pl011 : public Uart 607584SAli.Saidi@arm.com{ 617584SAli.Saidi@arm.com protected: 627587SAli.Saidi@arm.com static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); 637584SAli.Saidi@arm.com static const int UART_DR = 0x000; 647584SAli.Saidi@arm.com static const int UART_FR = 0x018; 657584SAli.Saidi@arm.com static const int UART_FR_CTS = 0x001; 667584SAli.Saidi@arm.com static const int UART_FR_TXFE = 0x080; 677584SAli.Saidi@arm.com static const int UART_FR_RXFE = 0x010; 687584SAli.Saidi@arm.com static const int UART_IBRD = 0x024; 697584SAli.Saidi@arm.com static const int UART_FBRD = 0x028; 707584SAli.Saidi@arm.com static const int UART_LCRH = 0x02C; 717584SAli.Saidi@arm.com static const int UART_CR = 0x030; 727584SAli.Saidi@arm.com static const int UART_IFLS = 0x034; 737584SAli.Saidi@arm.com static const int UART_IMSC = 0x038; 747584SAli.Saidi@arm.com static const int UART_RIS = 0x03C; 757584SAli.Saidi@arm.com static const int UART_MIS = 0x040; 767584SAli.Saidi@arm.com static const int UART_ICR = 0x044; 777584SAli.Saidi@arm.com 787584SAli.Saidi@arm.com uint16_t control; 797584SAli.Saidi@arm.com 807584SAli.Saidi@arm.com /** fractional baud rate divisor. Not used for anything but reporting 817584SAli.Saidi@arm.com * written value */ 827584SAli.Saidi@arm.com uint16_t fbrd; 837584SAli.Saidi@arm.com 847584SAli.Saidi@arm.com /** integer baud rate divisor. Not used for anything but reporting 857584SAli.Saidi@arm.com * written value */ 867584SAli.Saidi@arm.com uint16_t ibrd; 877584SAli.Saidi@arm.com 887584SAli.Saidi@arm.com /** Line control register. Not used for anything but reporting 897584SAli.Saidi@arm.com * written value */ 907584SAli.Saidi@arm.com uint16_t lcrh; 917584SAli.Saidi@arm.com 927584SAli.Saidi@arm.com /** interrupt fifo level register. Not used for anything but reporting 937584SAli.Saidi@arm.com * written value */ 947584SAli.Saidi@arm.com uint16_t ifls; 957584SAli.Saidi@arm.com 967584SAli.Saidi@arm.com BitUnion16(INTREG) 977584SAli.Saidi@arm.com Bitfield<0> rimim; 987584SAli.Saidi@arm.com Bitfield<1> ctsmim; 997584SAli.Saidi@arm.com Bitfield<2> dcdmim; 1007584SAli.Saidi@arm.com Bitfield<3> dsrmim; 1017584SAli.Saidi@arm.com Bitfield<4> rxim; 1027584SAli.Saidi@arm.com Bitfield<5> txim; 1037584SAli.Saidi@arm.com Bitfield<6> rtim; 1047584SAli.Saidi@arm.com Bitfield<7> feim; 1057584SAli.Saidi@arm.com Bitfield<8> peim; 1067584SAli.Saidi@arm.com Bitfield<9> beim; 1077584SAli.Saidi@arm.com Bitfield<10> oeim; 1087584SAli.Saidi@arm.com Bitfield<15,11> rsvd; 1097584SAli.Saidi@arm.com EndBitUnion(INTREG) 1107584SAli.Saidi@arm.com 1117584SAli.Saidi@arm.com /** interrupt mask register. */ 1127584SAli.Saidi@arm.com INTREG imsc; 1137584SAli.Saidi@arm.com 1147584SAli.Saidi@arm.com /** raw interrupt status register */ 1157584SAli.Saidi@arm.com INTREG rawInt; 1167584SAli.Saidi@arm.com 1177584SAli.Saidi@arm.com /** Masked interrupt status register */ 1187584SAli.Saidi@arm.com INTREG maskInt; 1197584SAli.Saidi@arm.com 1207584SAli.Saidi@arm.com /** Interrupt number to generate */ 1217584SAli.Saidi@arm.com int intNum; 1227584SAli.Saidi@arm.com 1237584SAli.Saidi@arm.com /** Gic to use for interrupting */ 1247584SAli.Saidi@arm.com Gic *gic; 1257584SAli.Saidi@arm.com 1267584SAli.Saidi@arm.com /** Should the simulation end on an EOT */ 1277584SAli.Saidi@arm.com bool endOnEOT; 1287584SAli.Saidi@arm.com 1297584SAli.Saidi@arm.com /** Delay before interrupting */ 1307584SAli.Saidi@arm.com Tick intDelay; 1317584SAli.Saidi@arm.com 1327584SAli.Saidi@arm.com /** Function to generate interrupt */ 1337584SAli.Saidi@arm.com void generateInterrupt(); 1347584SAli.Saidi@arm.com 1357584SAli.Saidi@arm.com /** Wrapper to create an event out of the thing */ 1367584SAli.Saidi@arm.com EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent; 1377584SAli.Saidi@arm.com 1387584SAli.Saidi@arm.com public: 1397584SAli.Saidi@arm.com typedef Pl011Params Params; 1407584SAli.Saidi@arm.com const Params * 1417584SAli.Saidi@arm.com params() const 1427584SAli.Saidi@arm.com { 1437584SAli.Saidi@arm.com return dynamic_cast<const Params *>(_params); 1447584SAli.Saidi@arm.com } 1457584SAli.Saidi@arm.com Pl011(const Params *p); 1467584SAli.Saidi@arm.com 1477584SAli.Saidi@arm.com virtual Tick read(PacketPtr pkt); 1487584SAli.Saidi@arm.com virtual Tick write(PacketPtr pkt); 1497584SAli.Saidi@arm.com 1507584SAli.Saidi@arm.com /** 1517584SAli.Saidi@arm.com * Inform the uart that there is data available. 1527584SAli.Saidi@arm.com */ 1537584SAli.Saidi@arm.com virtual void dataAvailable(); 1547584SAli.Saidi@arm.com 1557584SAli.Saidi@arm.com 1567584SAli.Saidi@arm.com /** 1577584SAli.Saidi@arm.com * Return if we have an interrupt pending 1587584SAli.Saidi@arm.com * @return interrupt status 1597584SAli.Saidi@arm.com * @todo fix me when implementation improves 1607584SAli.Saidi@arm.com */ 1617584SAli.Saidi@arm.com virtual bool intStatus() { return false; } 1627584SAli.Saidi@arm.com 1637584SAli.Saidi@arm.com virtual void serialize(std::ostream &os); 1647584SAli.Saidi@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 1657584SAli.Saidi@arm.com 1667584SAli.Saidi@arm.com}; 1677584SAli.Saidi@arm.com 1687584SAli.Saidi@arm.com#endif //__DEV_ARM_PL011_H__ 169