pl011.cc revision 13230:2988dc5d1d6f
1/* 2 * Copyright (c) 2010, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Andreas Sandberg 42 */ 43 44#include "dev/arm/pl011.hh" 45 46#include "base/trace.hh" 47#include "debug/Checkpoint.hh" 48#include "debug/Uart.hh" 49#include "dev/arm/amba_device.hh" 50#include "dev/arm/base_gic.hh" 51#include "mem/packet.hh" 52#include "mem/packet_access.hh" 53#include "params/Pl011.hh" 54#include "sim/sim_exit.hh" 55 56Pl011::Pl011(const Pl011Params *p) 57 : Uart(p, 0x1000), 58 intEvent([this]{ generateInterrupt(); }, name()), 59 control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), 60 imsc(0), rawInt(0), 61 gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num), 62 intDelay(p->int_delay) 63{ 64} 65 66Tick 67Pl011::read(PacketPtr pkt) 68{ 69 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 70 71 Addr daddr = pkt->getAddr() - pioAddr; 72 73 DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize()); 74 75 // use a temporary data since the uart registers are read/written with 76 // different size operations 77 // 78 uint32_t data = 0; 79 80 switch(daddr) { 81 case UART_DR: 82 data = 0; 83 if (device->dataAvailable()) { 84 data = device->readData(); 85 // Since we don't simulate a FIFO for incoming data, we 86 // assume it's empty and clear RXINTR and RTINTR. 87 clearInterrupts(UART_RXINTR | UART_RTINTR); 88 if (device->dataAvailable()) { 89 DPRINTF(Uart, "Re-raising interrupt due to more data " 90 "after UART_DR read\n"); 91 dataAvailable(); 92 } 93 } 94 break; 95 case UART_RSR: 96 data = 0x0; // We never have errors 97 break; 98 case UART_FR: 99 data = 100 UART_FR_CTS | // Clear To Send 101 // Given we do not simulate a FIFO we are either empty or full. 102 (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) | 103 UART_FR_TXFE; // TX FIFO empty 104 105 DPRINTF(Uart, 106 "Reading FR register as %#x rawInt=0x%x " 107 "imsc=0x%x maskInt=0x%x\n", 108 data, rawInt, imsc, maskInt()); 109 break; 110 case UART_CR: 111 data = control; 112 break; 113 case UART_IBRD: 114 data = ibrd; 115 break; 116 case UART_FBRD: 117 data = fbrd; 118 break; 119 case UART_LCRH: 120 data = lcrh; 121 break; 122 case UART_IFLS: 123 data = ifls; 124 break; 125 case UART_IMSC: 126 data = imsc; 127 break; 128 case UART_RIS: 129 data = rawInt; 130 DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt); 131 break; 132 case UART_MIS: 133 DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt()); 134 data = maskInt(); 135 break; 136 default: 137 if (readId(pkt, AMBA_ID, pioAddr)) { 138 // Hack for variable size accesses 139 data = pkt->getLE<uint32_t>(); 140 break; 141 } 142 143 panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr); 144 break; 145 } 146 147 switch(pkt->getSize()) { 148 case 1: 149 pkt->setLE<uint8_t>(data); 150 break; 151 case 2: 152 pkt->setLE<uint16_t>(data); 153 break; 154 case 4: 155 pkt->setLE<uint32_t>(data); 156 break; 157 default: 158 panic("Uart read size too big?\n"); 159 break; 160 } 161 162 163 pkt->makeAtomicResponse(); 164 return pioDelay; 165} 166 167Tick 168Pl011::write(PacketPtr pkt) 169{ 170 171 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 172 173 Addr daddr = pkt->getAddr() - pioAddr; 174 175 DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr, 176 pkt->getLE<uint8_t>(), pkt->getSize()); 177 178 // use a temporary data since the uart registers are read/written with 179 // different size operations 180 // 181 uint32_t data = 0; 182 183 switch(pkt->getSize()) { 184 case 1: 185 data = pkt->getLE<uint8_t>(); 186 break; 187 case 2: 188 data = pkt->getLE<uint16_t>(); 189 break; 190 case 4: 191 data = pkt->getLE<uint32_t>(); 192 break; 193 default: 194 panic("Uart write size too big?\n"); 195 break; 196 } 197 198 199 switch (daddr) { 200 case UART_DR: 201 if ((data & 0xFF) == 0x04 && endOnEOT) 202 exitSimLoop("UART received EOT", 0); 203 204 device->writeData(data & 0xFF); 205 // We're supposed to clear TXINTR when this register is 206 // written to, however. since we're also infinitely fast, we 207 // need to immediately raise it again. 208 clearInterrupts(UART_TXINTR); 209 raiseInterrupts(UART_TXINTR); 210 break; 211 case UART_ECR: // clears errors, ignore 212 break; 213 case UART_CR: 214 control = data; 215 break; 216 case UART_IBRD: 217 ibrd = data; 218 break; 219 case UART_FBRD: 220 fbrd = data; 221 break; 222 case UART_LCRH: 223 lcrh = data; 224 break; 225 case UART_IFLS: 226 ifls = data; 227 break; 228 case UART_IMSC: 229 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data); 230 setInterruptMask(data); 231 break; 232 233 case UART_ICR: 234 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 235 clearInterrupts(data); 236 if (device->dataAvailable()) { 237 DPRINTF(Uart, "Re-raising interrupt due to more data after " 238 "UART_ICR write\n"); 239 dataAvailable(); 240 } 241 break; 242 default: 243 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr); 244 break; 245 } 246 pkt->makeAtomicResponse(); 247 return pioDelay; 248} 249 250void 251Pl011::dataAvailable() 252{ 253 /*@todo ignore the fifo, just say we have data now 254 * We might want to fix this, or we might not care */ 255 DPRINTF(Uart, "Data available, scheduling interrupt\n"); 256 raiseInterrupts(UART_RXINTR | UART_RTINTR); 257} 258 259void 260Pl011::generateInterrupt() 261{ 262 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 263 imsc, rawInt, maskInt()); 264 265 if (maskInt()) { 266 gic->sendInt(intNum); 267 DPRINTF(Uart, " -- Generated\n"); 268 } 269} 270 271void 272Pl011::setInterrupts(uint16_t ints, uint16_t mask) 273{ 274 const bool old_ints(!!maskInt()); 275 276 imsc = mask; 277 rawInt = ints; 278 279 if (!old_ints && maskInt()) { 280 if (!intEvent.scheduled()) 281 schedule(intEvent, curTick() + intDelay); 282 } else if (old_ints && !maskInt()) { 283 gic->clearInt(intNum); 284 } 285} 286 287 288 289void 290Pl011::serialize(CheckpointOut &cp) const 291{ 292 DPRINTF(Checkpoint, "Serializing Arm PL011\n"); 293 SERIALIZE_SCALAR(control); 294 SERIALIZE_SCALAR(fbrd); 295 SERIALIZE_SCALAR(ibrd); 296 SERIALIZE_SCALAR(lcrh); 297 SERIALIZE_SCALAR(ifls); 298 299 // Preserve backwards compatibility by giving these silly names. 300 paramOut(cp, "imsc_serial", imsc); 301 paramOut(cp, "rawInt_serial", rawInt); 302} 303 304void 305Pl011::unserialize(CheckpointIn &cp) 306{ 307 DPRINTF(Checkpoint, "Unserializing Arm PL011\n"); 308 309 UNSERIALIZE_SCALAR(control); 310 UNSERIALIZE_SCALAR(fbrd); 311 UNSERIALIZE_SCALAR(ibrd); 312 UNSERIALIZE_SCALAR(lcrh); 313 UNSERIALIZE_SCALAR(ifls); 314 315 // Preserve backwards compatibility by giving these silly names. 316 paramIn(cp, "imsc_serial", imsc); 317 paramIn(cp, "rawInt_serial", rawInt); 318} 319 320Pl011 * 321Pl011Params::create() 322{ 323 return new Pl011(this); 324} 325