pl011.cc revision 11480:2af4c6a4f3f5 
1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Andreas Sandberg
42 */
43
44#include "dev/arm/pl011.hh"
45
46#include "base/trace.hh"
47#include "debug/Checkpoint.hh"
48#include "debug/Uart.hh"
49#include "dev/arm/amba_device.hh"
50#include "dev/arm/base_gic.hh"
51#include "dev/terminal.hh"
52#include "mem/packet.hh"
53#include "mem/packet_access.hh"
54#include "sim/sim_exit.hh"
55#include "params/Pl011.hh"
56
57Pl011::Pl011(const Pl011Params *p)
58    : Uart(p, 0xfff),
59      intEvent(this),
60      control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
61      imsc(0), rawInt(0),
62      gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num),
63      intDelay(p->int_delay)
64{
65}
66
67Tick
68Pl011::read(PacketPtr pkt)
69{
70    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
71
72    Addr daddr = pkt->getAddr() - pioAddr;
73
74    DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
75
76    // use a temporary data since the uart registers are read/written with
77    // different size operations
78    //
79    uint32_t data = 0;
80
81    switch(daddr) {
82      case UART_DR:
83        data = 0;
84        if (term->dataAvailable()) {
85            data = term->in();
86            // Since we don't simulate a FIFO for incoming data, we
87            // assume it's empty and clear RXINTR and RTINTR.
88            clearInterrupts(UART_RXINTR | UART_RTINTR);
89        }
90        break;
91      case UART_FR:
92        data =
93            UART_FR_CTS | // Clear To Send
94            // Given we do not simulate a FIFO we are either empty or full.
95            (!term->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
96            UART_FR_TXFE; // TX FIFO empty
97
98        DPRINTF(Uart,
99                "Reading FR register as %#x rawInt=0x%x "
100                "imsc=0x%x maskInt=0x%x\n",
101                data, rawInt, imsc, maskInt());
102        break;
103      case UART_CR:
104        data = control;
105        break;
106      case UART_IBRD:
107        data = ibrd;
108        break;
109      case UART_FBRD:
110        data = fbrd;
111        break;
112      case UART_LCRH:
113        data = lcrh;
114        break;
115      case UART_IFLS:
116        data = ifls;
117        break;
118      case UART_IMSC:
119        data = imsc;
120        break;
121      case UART_RIS:
122        data = rawInt;
123        DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
124        break;
125      case UART_MIS:
126        DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
127        data = maskInt();
128        break;
129      default:
130        if (readId(pkt, AMBA_ID, pioAddr)) {
131            // Hack for variable size accesses
132            data = pkt->get<uint32_t>();
133            break;
134        }
135
136        panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
137        break;
138    }
139
140    switch(pkt->getSize()) {
141      case 1:
142        pkt->set<uint8_t>(data);
143        break;
144      case 2:
145        pkt->set<uint16_t>(data);
146        break;
147      case 4:
148        pkt->set<uint32_t>(data);
149        break;
150      default:
151        panic("Uart read size too big?\n");
152        break;
153    }
154
155
156    pkt->makeAtomicResponse();
157    return pioDelay;
158}
159
160Tick
161Pl011::write(PacketPtr pkt)
162{
163
164    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
165
166    Addr daddr = pkt->getAddr() - pioAddr;
167
168    DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
169            pkt->get<uint8_t>(), pkt->getSize());
170
171    // use a temporary data since the uart registers are read/written with
172    // different size operations
173    //
174    uint32_t data = 0;
175
176    switch(pkt->getSize()) {
177      case 1:
178        data = pkt->get<uint8_t>();
179        break;
180      case 2:
181        data = pkt->get<uint16_t>();
182        break;
183      case 4:
184        data = pkt->get<uint32_t>();
185        break;
186      default:
187        panic("Uart write size too big?\n");
188        break;
189    }
190
191
192    switch (daddr) {
193        case UART_DR:
194          if ((data & 0xFF) == 0x04 && endOnEOT)
195            exitSimLoop("UART received EOT", 0);
196
197        term->out(data & 0xFF);
198        // We're supposed to clear TXINTR when this register is
199        // written to, however. since we're also infinitely fast, we
200        // need to immediately raise it again.
201        clearInterrupts(UART_TXINTR);
202        raiseInterrupts(UART_TXINTR);
203        break;
204      case UART_CR:
205        control = data;
206        break;
207      case UART_IBRD:
208        ibrd = data;
209        break;
210      case UART_FBRD:
211        fbrd = data;
212        break;
213      case UART_LCRH:
214        lcrh = data;
215        break;
216      case UART_IFLS:
217        ifls = data;
218        break;
219      case UART_IMSC:
220        DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
221        setInterruptMask(data);
222        break;
223
224      case UART_ICR:
225        DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
226        clearInterrupts(data);
227        break;
228      default:
229        panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
230        break;
231    }
232    pkt->makeAtomicResponse();
233    return pioDelay;
234}
235
236void
237Pl011::dataAvailable()
238{
239    /*@todo ignore the fifo, just say we have data now
240     * We might want to fix this, or we might not care */
241    DPRINTF(Uart, "Data available, scheduling interrupt\n");
242    raiseInterrupts(UART_RXINTR | UART_RTINTR);
243}
244
245void
246Pl011::generateInterrupt()
247{
248    DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
249            imsc, rawInt, maskInt());
250
251    if (maskInt()) {
252        gic->sendInt(intNum);
253        DPRINTF(Uart, " -- Generated\n");
254    }
255}
256
257void
258Pl011::setInterrupts(uint16_t ints, uint16_t mask)
259{
260    const bool old_ints(!!maskInt());
261
262    imsc = mask;
263    rawInt = ints;
264
265    if (!old_ints && maskInt()) {
266        if (!intEvent.scheduled())
267            schedule(intEvent, curTick() + intDelay);
268    } else if (old_ints && !maskInt()) {
269        gic->clearInt(intNum);
270    }
271}
272
273
274
275void
276Pl011::serialize(CheckpointOut &cp) const
277{
278    DPRINTF(Checkpoint, "Serializing Arm PL011\n");
279    SERIALIZE_SCALAR(control);
280    SERIALIZE_SCALAR(fbrd);
281    SERIALIZE_SCALAR(ibrd);
282    SERIALIZE_SCALAR(lcrh);
283    SERIALIZE_SCALAR(ifls);
284
285    // Preserve backwards compatibility by giving these silly names.
286    paramOut(cp, "imsc_serial", imsc);
287    paramOut(cp, "rawInt_serial", rawInt);
288}
289
290void
291Pl011::unserialize(CheckpointIn &cp)
292{
293    DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
294
295    UNSERIALIZE_SCALAR(control);
296    UNSERIALIZE_SCALAR(fbrd);
297    UNSERIALIZE_SCALAR(ibrd);
298    UNSERIALIZE_SCALAR(lcrh);
299    UNSERIALIZE_SCALAR(ifls);
300
301    // Preserve backwards compatibility by giving these silly names.
302    paramIn(cp, "imsc_serial", imsc);
303    paramIn(cp, "rawInt_serial", rawInt);
304}
305
306Pl011 *
307Pl011Params::create()
308{
309    return new Pl011(this);
310}
311