pl011.cc revision 10718
17584SAli.Saidi@arm.com/* 210718SAndreas.Sandberg@ARM.com * Copyright (c) 2010, 2015 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 157584SAli.Saidi@arm.com * All rights reserved. 167584SAli.Saidi@arm.com * 177584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 187584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 197584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 207584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 217584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 227584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 237584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 247584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 257584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 267584SAli.Saidi@arm.com * this software without specific prior written permission. 277584SAli.Saidi@arm.com * 287584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397584SAli.Saidi@arm.com * 407584SAli.Saidi@arm.com * Authors: Ali Saidi 4110718SAndreas.Sandberg@ARM.com * Andreas Sandberg 427584SAli.Saidi@arm.com */ 437584SAli.Saidi@arm.com 4410718SAndreas.Sandberg@ARM.com#include "dev/arm/pl011.hh" 4510718SAndreas.Sandberg@ARM.com 467584SAli.Saidi@arm.com#include "base/trace.hh" 478245Snate@binkert.org#include "debug/Checkpoint.hh" 488245Snate@binkert.org#include "debug/Uart.hh" 497587SAli.Saidi@arm.com#include "dev/arm/amba_device.hh" 509525SAndreas.Sandberg@ARM.com#include "dev/arm/base_gic.hh" 517584SAli.Saidi@arm.com#include "dev/terminal.hh" 527584SAli.Saidi@arm.com#include "mem/packet.hh" 537584SAli.Saidi@arm.com#include "mem/packet_access.hh" 547584SAli.Saidi@arm.com#include "sim/sim_exit.hh" 5510718SAndreas.Sandberg@ARM.com#include "params/Pl011.hh" 567584SAli.Saidi@arm.com 5710718SAndreas.Sandberg@ARM.comPl011::Pl011(const Pl011Params *p) 5810718SAndreas.Sandberg@ARM.com : Uart(p, 0xfff), 5910718SAndreas.Sandberg@ARM.com intEvent(this), 6010718SAndreas.Sandberg@ARM.com control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), 6110718SAndreas.Sandberg@ARM.com imsc(0), rawInt(0), 6210718SAndreas.Sandberg@ARM.com gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num), 6310718SAndreas.Sandberg@ARM.com intDelay(p->int_delay) 647584SAli.Saidi@arm.com{ 657584SAli.Saidi@arm.com} 667584SAli.Saidi@arm.com 677584SAli.Saidi@arm.comTick 687584SAli.Saidi@arm.comPl011::read(PacketPtr pkt) 697584SAli.Saidi@arm.com{ 707584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 717584SAli.Saidi@arm.com 727584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 737584SAli.Saidi@arm.com 747584SAli.Saidi@arm.com DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize()); 757584SAli.Saidi@arm.com 767584SAli.Saidi@arm.com // use a temporary data since the uart registers are read/written with 777584SAli.Saidi@arm.com // different size operations 787584SAli.Saidi@arm.com // 797584SAli.Saidi@arm.com uint32_t data = 0; 807584SAli.Saidi@arm.com 817584SAli.Saidi@arm.com switch(daddr) { 827584SAli.Saidi@arm.com case UART_DR: 837584SAli.Saidi@arm.com data = 0; 8410718SAndreas.Sandberg@ARM.com if (term->dataAvailable()) { 857584SAli.Saidi@arm.com data = term->in(); 8610718SAndreas.Sandberg@ARM.com // Since we don't simulate a FIFO for incoming data, we 8710718SAndreas.Sandberg@ARM.com // assume it's empty and clear RXINTR and RTINTR. 8810718SAndreas.Sandberg@ARM.com clearInterrupts(UART_RXINTR | UART_RTINTR); 8910718SAndreas.Sandberg@ARM.com } 907584SAli.Saidi@arm.com break; 917584SAli.Saidi@arm.com case UART_FR: 9210718SAndreas.Sandberg@ARM.com data = 9310718SAndreas.Sandberg@ARM.com UART_FR_CTS | // Clear To Send 9410718SAndreas.Sandberg@ARM.com (!term->dataAvailable() ? UART_FR_RXFE : 0) | // RX FIFO Empty 9510718SAndreas.Sandberg@ARM.com UART_FR_TXFE; // TX FIFO empty 9610718SAndreas.Sandberg@ARM.com 9710718SAndreas.Sandberg@ARM.com DPRINTF(Uart, 9810718SAndreas.Sandberg@ARM.com "Reading FR register as %#x rawInt=0x%x " 9910718SAndreas.Sandberg@ARM.com "imsc=0x%x maskInt=0x%x\n", 10010718SAndreas.Sandberg@ARM.com data, rawInt, imsc, maskInt()); 1017584SAli.Saidi@arm.com break; 1027584SAli.Saidi@arm.com case UART_CR: 1037584SAli.Saidi@arm.com data = control; 1047584SAli.Saidi@arm.com break; 1057584SAli.Saidi@arm.com case UART_IBRD: 1067584SAli.Saidi@arm.com data = ibrd; 1077584SAli.Saidi@arm.com break; 1087584SAli.Saidi@arm.com case UART_FBRD: 1097584SAli.Saidi@arm.com data = fbrd; 1107584SAli.Saidi@arm.com break; 1117584SAli.Saidi@arm.com case UART_LCRH: 1127584SAli.Saidi@arm.com data = lcrh; 1137584SAli.Saidi@arm.com break; 1147584SAli.Saidi@arm.com case UART_IFLS: 1157584SAli.Saidi@arm.com data = ifls; 1167584SAli.Saidi@arm.com break; 1177584SAli.Saidi@arm.com case UART_IMSC: 1187584SAli.Saidi@arm.com data = imsc; 1197584SAli.Saidi@arm.com break; 1207584SAli.Saidi@arm.com case UART_RIS: 1217584SAli.Saidi@arm.com data = rawInt; 1227584SAli.Saidi@arm.com DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt); 1237584SAli.Saidi@arm.com break; 1247584SAli.Saidi@arm.com case UART_MIS: 12510718SAndreas.Sandberg@ARM.com DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt()); 12610718SAndreas.Sandberg@ARM.com data = maskInt(); 1277584SAli.Saidi@arm.com break; 1287584SAli.Saidi@arm.com default: 1299806Sstever@gmail.com if (readId(pkt, AMBA_ID, pioAddr)) { 1307587SAli.Saidi@arm.com // Hack for variable size accesses 1317587SAli.Saidi@arm.com data = pkt->get<uint32_t>(); 1327584SAli.Saidi@arm.com break; 1337584SAli.Saidi@arm.com } 1347587SAli.Saidi@arm.com 1357584SAli.Saidi@arm.com panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr); 1367584SAli.Saidi@arm.com break; 1377584SAli.Saidi@arm.com } 1387584SAli.Saidi@arm.com 1397584SAli.Saidi@arm.com switch(pkt->getSize()) { 1407584SAli.Saidi@arm.com case 1: 1417584SAli.Saidi@arm.com pkt->set<uint8_t>(data); 1427584SAli.Saidi@arm.com break; 1437584SAli.Saidi@arm.com case 2: 1447584SAli.Saidi@arm.com pkt->set<uint16_t>(data); 1457584SAli.Saidi@arm.com break; 1467584SAli.Saidi@arm.com case 4: 1477584SAli.Saidi@arm.com pkt->set<uint32_t>(data); 1487584SAli.Saidi@arm.com break; 1497584SAli.Saidi@arm.com default: 1507584SAli.Saidi@arm.com panic("Uart read size too big?\n"); 1517584SAli.Saidi@arm.com break; 1527584SAli.Saidi@arm.com } 1537584SAli.Saidi@arm.com 1547584SAli.Saidi@arm.com 1557584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 1567584SAli.Saidi@arm.com return pioDelay; 1577584SAli.Saidi@arm.com} 1587584SAli.Saidi@arm.com 1597584SAli.Saidi@arm.comTick 1607584SAli.Saidi@arm.comPl011::write(PacketPtr pkt) 1617584SAli.Saidi@arm.com{ 1627584SAli.Saidi@arm.com 1637584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1647584SAli.Saidi@arm.com 1657584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 1667584SAli.Saidi@arm.com 1677584SAli.Saidi@arm.com DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr, 1687584SAli.Saidi@arm.com pkt->get<uint8_t>(), pkt->getSize()); 1697584SAli.Saidi@arm.com 1707584SAli.Saidi@arm.com // use a temporary data since the uart registers are read/written with 1717584SAli.Saidi@arm.com // different size operations 1727584SAli.Saidi@arm.com // 1737584SAli.Saidi@arm.com uint32_t data = 0; 1747584SAli.Saidi@arm.com 1757584SAli.Saidi@arm.com switch(pkt->getSize()) { 1767584SAli.Saidi@arm.com case 1: 1777584SAli.Saidi@arm.com data = pkt->get<uint8_t>(); 1787584SAli.Saidi@arm.com break; 1797584SAli.Saidi@arm.com case 2: 1807584SAli.Saidi@arm.com data = pkt->get<uint16_t>(); 1817584SAli.Saidi@arm.com break; 1827584SAli.Saidi@arm.com case 4: 1837584SAli.Saidi@arm.com data = pkt->get<uint32_t>(); 1847584SAli.Saidi@arm.com break; 1857584SAli.Saidi@arm.com default: 1867584SAli.Saidi@arm.com panic("Uart write size too big?\n"); 1877584SAli.Saidi@arm.com break; 1887584SAli.Saidi@arm.com } 1897584SAli.Saidi@arm.com 1907584SAli.Saidi@arm.com 1917584SAli.Saidi@arm.com switch (daddr) { 1927584SAli.Saidi@arm.com case UART_DR: 1937584SAli.Saidi@arm.com if ((data & 0xFF) == 0x04 && endOnEOT) 1947584SAli.Saidi@arm.com exitSimLoop("UART received EOT", 0); 1957584SAli.Saidi@arm.com 1967584SAli.Saidi@arm.com term->out(data & 0xFF); 19710718SAndreas.Sandberg@ARM.com // We're supposed to clear TXINTR when this register is 19810718SAndreas.Sandberg@ARM.com // written to, however. since we're also infinitely fast, we 19910718SAndreas.Sandberg@ARM.com // need to immediately raise it again. 20010718SAndreas.Sandberg@ARM.com clearInterrupts(UART_TXINTR); 20110718SAndreas.Sandberg@ARM.com raiseInterrupts(UART_TXINTR); 2027584SAli.Saidi@arm.com break; 2037584SAli.Saidi@arm.com case UART_CR: 2047584SAli.Saidi@arm.com control = data; 2057584SAli.Saidi@arm.com break; 2067584SAli.Saidi@arm.com case UART_IBRD: 2077584SAli.Saidi@arm.com ibrd = data; 2087584SAli.Saidi@arm.com break; 2097584SAli.Saidi@arm.com case UART_FBRD: 2107584SAli.Saidi@arm.com fbrd = data; 2117584SAli.Saidi@arm.com break; 2127584SAli.Saidi@arm.com case UART_LCRH: 2137584SAli.Saidi@arm.com lcrh = data; 2147584SAli.Saidi@arm.com break; 2157584SAli.Saidi@arm.com case UART_IFLS: 2167584SAli.Saidi@arm.com ifls = data; 2177584SAli.Saidi@arm.com break; 2187584SAli.Saidi@arm.com case UART_IMSC: 21910718SAndreas.Sandberg@ARM.com DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data); 22010718SAndreas.Sandberg@ARM.com setInterruptMask(data); 2217584SAli.Saidi@arm.com break; 2227584SAli.Saidi@arm.com 2237584SAli.Saidi@arm.com case UART_ICR: 2247584SAli.Saidi@arm.com DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 22510718SAndreas.Sandberg@ARM.com clearInterrupts(data); 2267584SAli.Saidi@arm.com break; 2277584SAli.Saidi@arm.com default: 2287584SAli.Saidi@arm.com panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr); 2297584SAli.Saidi@arm.com break; 2307584SAli.Saidi@arm.com } 2317584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 2327584SAli.Saidi@arm.com return pioDelay; 2337584SAli.Saidi@arm.com} 2347584SAli.Saidi@arm.com 2357584SAli.Saidi@arm.comvoid 2367584SAli.Saidi@arm.comPl011::dataAvailable() 2377584SAli.Saidi@arm.com{ 2387584SAli.Saidi@arm.com /*@todo ignore the fifo, just say we have data now 2397584SAli.Saidi@arm.com * We might want to fix this, or we might not care */ 2407584SAli.Saidi@arm.com DPRINTF(Uart, "Data available, scheduling interrupt\n"); 24110718SAndreas.Sandberg@ARM.com raiseInterrupts(UART_RXINTR | UART_RTINTR); 2427584SAli.Saidi@arm.com} 2437584SAli.Saidi@arm.com 2447584SAli.Saidi@arm.comvoid 2457584SAli.Saidi@arm.comPl011::generateInterrupt() 2467584SAli.Saidi@arm.com{ 2477584SAli.Saidi@arm.com DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 24810718SAndreas.Sandberg@ARM.com imsc, rawInt, maskInt()); 2497584SAli.Saidi@arm.com 25010718SAndreas.Sandberg@ARM.com if (maskInt()) { 2517584SAli.Saidi@arm.com gic->sendInt(intNum); 2527584SAli.Saidi@arm.com DPRINTF(Uart, " -- Generated\n"); 2537584SAli.Saidi@arm.com } 25410718SAndreas.Sandberg@ARM.com} 2557584SAli.Saidi@arm.com 25610718SAndreas.Sandberg@ARM.comvoid 25710718SAndreas.Sandberg@ARM.comPl011::setInterrupts(uint16_t ints, uint16_t mask) 25810718SAndreas.Sandberg@ARM.com{ 25910718SAndreas.Sandberg@ARM.com const bool old_ints(!!maskInt()); 26010718SAndreas.Sandberg@ARM.com 26110718SAndreas.Sandberg@ARM.com imsc = mask; 26210718SAndreas.Sandberg@ARM.com rawInt = ints; 26310718SAndreas.Sandberg@ARM.com 26410718SAndreas.Sandberg@ARM.com if (!old_ints && maskInt()) { 26510718SAndreas.Sandberg@ARM.com if (!intEvent.scheduled()) 26610718SAndreas.Sandberg@ARM.com schedule(intEvent, curTick() + intDelay); 26710718SAndreas.Sandberg@ARM.com } else if (old_ints && !maskInt()) { 26810718SAndreas.Sandberg@ARM.com gic->clearInt(intNum); 26910718SAndreas.Sandberg@ARM.com } 2707584SAli.Saidi@arm.com} 2717584SAli.Saidi@arm.com 2727584SAli.Saidi@arm.com 2737584SAli.Saidi@arm.com 2747584SAli.Saidi@arm.comvoid 2757584SAli.Saidi@arm.comPl011::serialize(std::ostream &os) 2767584SAli.Saidi@arm.com{ 2777733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm PL011\n"); 2787733SAli.Saidi@ARM.com SERIALIZE_SCALAR(control); 2797733SAli.Saidi@ARM.com SERIALIZE_SCALAR(fbrd); 2807733SAli.Saidi@ARM.com SERIALIZE_SCALAR(ibrd); 2817733SAli.Saidi@ARM.com SERIALIZE_SCALAR(lcrh); 2827733SAli.Saidi@ARM.com SERIALIZE_SCALAR(ifls); 2837733SAli.Saidi@ARM.com 28410718SAndreas.Sandberg@ARM.com // Preserve backwards compatibility by giving these silly names. 28510718SAndreas.Sandberg@ARM.com paramOut(os, "imsc_serial", imsc); 28610718SAndreas.Sandberg@ARM.com paramOut(os, "rawInt_serial", rawInt); 2877584SAli.Saidi@arm.com} 2887584SAli.Saidi@arm.com 2897584SAli.Saidi@arm.comvoid 2907584SAli.Saidi@arm.comPl011::unserialize(Checkpoint *cp, const std::string §ion) 2917584SAli.Saidi@arm.com{ 2927733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm PL011\n"); 2937733SAli.Saidi@ARM.com 2947733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(control); 2957733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(fbrd); 2967733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(ibrd); 2977733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(lcrh); 2987733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(ifls); 2997733SAli.Saidi@ARM.com 30010718SAndreas.Sandberg@ARM.com // Preserve backwards compatibility by giving these silly names. 30110718SAndreas.Sandberg@ARM.com paramIn(cp, section, "imsc_serial", imsc); 30210718SAndreas.Sandberg@ARM.com paramIn(cp, section, "rawInt_serial", rawInt); 3037584SAli.Saidi@arm.com} 3047584SAli.Saidi@arm.com 3057584SAli.Saidi@arm.comPl011 * 3067584SAli.Saidi@arm.comPl011Params::create() 3077584SAli.Saidi@arm.com{ 3087584SAli.Saidi@arm.com return new Pl011(this); 3097584SAli.Saidi@arm.com} 310