gic_v3_redistributor.hh revision 14258:c75d22c32dec 
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_REDISTRIBUTOR_H__
44#define __DEV_ARM_GICV3_REDISTRIBUTOR_H__
45
46#include "base/addr_range.hh"
47#include "dev/arm/gic_v3.hh"
48#include "sim/serialize.hh"
49
50class Gicv3CPUInterface;
51class Gicv3Distributor;
52class Gicv3Its;
53
54class Gicv3Redistributor : public Serializable
55{
56  private:
57
58    friend class Gicv3CPUInterface;
59    friend class Gicv3Distributor;
60    friend class Gicv3Its;
61
62  protected:
63
64    Gicv3 * gic;
65    Gicv3Distributor * distributor;
66    Gicv3CPUInterface * cpuInterface;
67    uint32_t cpuId;
68    PortProxy * memProxy;
69
70    /*
71     * GICv3 defines 2 contiguous 64KB frames for each redistributor.
72     * Order of frames must be RD_base, SGI_base.
73     */
74    static const uint32_t RD_base  = 0x0;
75    static const uint32_t SGI_base = 0x10000;
76
77    enum {
78        // Control Register
79        GICR_CTLR  = RD_base + 0x0000,
80        // Implementer Identification Register
81        GICR_IIDR  = RD_base + 0x0004,
82        // Type Register
83        GICR_TYPER = RD_base + 0x0008,
84        // Wake Register
85        GICR_WAKER = RD_base + 0x0014,
86        // Peripheral ID0 Register
87        GICR_PIDR0 = RD_base + 0xffe0,
88        // Peripheral ID1 Register
89        GICR_PIDR1 = RD_base + 0xffe4,
90        // Peripheral ID2 Register
91        GICR_PIDR2 = RD_base + 0xffe8,
92        // Peripheral ID3 Register
93        GICR_PIDR3 = RD_base + 0xffec,
94        // Peripheral ID4 Register
95        GICR_PIDR4 = RD_base + 0xffd0,
96        // Peripheral ID5 Register
97        GICR_PIDR5 = RD_base + 0xffd4,
98        // Peripheral ID6 Register
99        GICR_PIDR6 = RD_base + 0xffd8,
100        // Peripheral ID7 Register
101        GICR_PIDR7 = RD_base + 0xffdc,
102    };
103
104    static const uint32_t GICR_WAKER_ProcessorSleep = 1 << 1;
105    static const uint32_t GICR_WAKER_ChildrenAsleep = 1 << 2;
106
107    bool peInLowPowerState;
108
109    enum {
110        // Interrupt Group Register 0
111        GICR_IGROUPR0   = SGI_base + 0x0080,
112        // Interrupt Set-Enable Register 0
113        GICR_ISENABLER0 = SGI_base + 0x0100,
114        // Interrupt Clear-Enable Register 0
115        GICR_ICENABLER0 = SGI_base + 0x0180,
116        // Interrupt Set-Pending Register 0
117        GICR_ISPENDR0   = SGI_base + 0x0200,
118        // Interrupt Clear-Pending Register 0
119        GICR_ICPENDR0   = SGI_base + 0x0280,
120        // Interrupt Set-Active Register 0
121        GICR_ISACTIVER0 = SGI_base + 0x0300,
122        // Interrupt Clear-Active Register 0
123        GICR_ICACTIVER0 = SGI_base + 0x0380,
124        // SGI Configuration Register
125        GICR_ICFGR0     = SGI_base + 0x0c00,
126        // PPI Configuration Register
127        GICR_ICFGR1     = SGI_base + 0x0c04,
128        // Interrupt Group Modifier Register 0
129        GICR_IGRPMODR0  = SGI_base + 0x0d00,
130        // Non-secure Access Control Register
131        GICR_NSACR      = SGI_base + 0x0e00,
132    };
133
134    // Interrupt Priority Registers
135    static const AddrRange GICR_IPRIORITYR;
136
137    // GIC physical LPI Redistributor register
138    enum {
139        // Set LPI Pending Register
140        GICR_SETLPIR = RD_base + 0x0040,
141        // Clear LPI Pending Register
142        GICR_CLRLPIR = RD_base + 0x0048,
143        //Redistributor Properties Base Address Register
144        GICR_PROPBASER = RD_base + 0x0070,
145        // Redistributor LPI Pending Table Base Address Register
146        GICR_PENDBASER = RD_base + 0x0078,
147        // Redistributor Invalidate LPI Register
148        GICR_INVLPIR = RD_base + 0x00A0,
149        // Redistributor Invalidate All Register
150        GICR_INVALLR = RD_base + 0x00B0,
151        // Redistributor Synchronize Register
152        GICR_SYNCR = RD_base + 0x00C0,
153    };
154
155    std::vector <uint8_t> irqGroup;
156    std::vector <bool> irqEnabled;
157    std::vector <bool> irqPending;
158    std::vector <bool> irqActive;
159    std::vector <uint8_t> irqPriority;
160    std::vector <Gicv3::IntTriggerType> irqConfig;
161    std::vector <uint8_t> irqGrpmod;
162    std::vector <uint8_t> irqNsacr;
163
164    bool DPG1S;
165    bool DPG1NS;
166    bool DPG0;
167    bool EnableLPIs;
168
169    Addr lpiConfigurationTablePtr;
170    uint8_t lpiIDBits;
171    Addr lpiPendingTablePtr;
172
173    BitUnion8(LPIConfigurationTableEntry)
174        Bitfield<7, 2> priority;
175        Bitfield<1> res1;
176        Bitfield<0> enable;
177    EndBitUnion(LPIConfigurationTableEntry)
178
179    static const uint32_t GICR_CTLR_ENABLE_LPIS = 1 << 0;
180    static const uint32_t GICR_CTLR_DPG0   = 1 << 24;
181    static const uint32_t GICR_CTLR_DPG1NS = 1 << 25;
182    static const uint32_t GICR_CTLR_DPG1S  = 1 << 26;
183
184  public:
185
186    /*
187     * GICv3 defines only 2 64K consecutive frames for the redistributor
188     * (RD_base and SGI_base) but we are using 2 extra 64K stride frames
189     * to match GICv4 that defines 4 64K consecutive frames for them.
190     * Note this must match with DTB/DTS GIC node definition and boot
191     * loader code.
192     */
193    const uint32_t addrRangeSize;
194
195    static const uint32_t SMALLEST_LPI_ID = 8192;
196
197
198    void activateIRQ(uint32_t int_id);
199    bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const;
200    void deactivateIRQ(uint32_t int_id);
201
202    inline Gicv3CPUInterface *
203    getCPUInterface() const
204    {
205        return cpuInterface;
206    }
207
208    uint32_t
209    processorNumber() const
210    {
211        return cpuId;
212    }
213
214    Gicv3::GroupId getIntGroup(int int_id) const;
215    Gicv3::IntStatus intStatus(uint32_t int_id) const;
216    uint8_t readEntryLPI(uint32_t intid);
217    void writeEntryLPI(uint32_t intid, uint8_t lpi_entry);
218    bool isPendingLPI(uint32_t intid);
219    void setClrLPI(uint64_t data, bool set);
220    void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
221    void serialize(CheckpointOut & cp) const override;
222    void unserialize(CheckpointIn & cp) override;
223    void update();
224    void updateDistributor();
225
226  public:
227
228    Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
229    uint32_t getAffinity() const;
230    void init();
231    uint64_t read(Addr addr, size_t size, bool is_secure_access);
232    void sendPPInt(uint32_t int_id);
233    void write(Addr addr, uint64_t data, size_t size, bool is_secure_access);
234};
235
236#endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__
237