gic_v3_cpu_interface.cc revision 13926:d6ebddee93a7
1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Jairo Balart 29 */ 30 31#include "dev/arm/gic_v3_cpu_interface.hh" 32 33#include "arch/arm/isa.hh" 34#include "debug/GIC.hh" 35#include "dev/arm/gic_v3.hh" 36#include "dev/arm/gic_v3_distributor.hh" 37#include "dev/arm/gic_v3_redistributor.hh" 38 39const uint8_t Gicv3CPUInterface::GIC_MIN_BPR; 40const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; 41 42Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 43 : BaseISADevice(), 44 gic(gic), 45 redistributor(nullptr), 46 distributor(nullptr), 47 cpuId(cpu_id) 48{ 49} 50 51void 52Gicv3CPUInterface::init() 53{ 54 redistributor = gic->getRedistributor(cpuId); 55 distributor = gic->getDistributor(); 56} 57 58void 59Gicv3CPUInterface::initState() 60{ 61 reset(); 62} 63 64void 65Gicv3CPUInterface::reset() 66{ 67 hppi.prio = 0xff; 68} 69 70void 71Gicv3CPUInterface::setThreadContext(ThreadContext *tc) 72{ 73 maintenanceInterrupt = gic->params()->maint_int->get(tc); 74} 75 76bool 77Gicv3CPUInterface::getHCREL2FMO() const 78{ 79 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 80 81 if (hcr.tge && hcr.e2h) { 82 return false; 83 } else if (hcr.tge) { 84 return true; 85 } else { 86 return hcr.fmo; 87 } 88} 89 90bool 91Gicv3CPUInterface::getHCREL2IMO() const 92{ 93 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 94 95 if (hcr.tge && hcr.e2h) { 96 return false; 97 } else if (hcr.tge) { 98 return true; 99 } else { 100 return hcr.imo; 101 } 102} 103 104RegVal 105Gicv3CPUInterface::readMiscReg(int misc_reg) 106{ 107 RegVal value = isa->readMiscRegNoEffect(misc_reg); 108 bool hcr_fmo = getHCREL2FMO(); 109 bool hcr_imo = getHCREL2IMO(); 110 111 switch (misc_reg) { 112 // Active Priorities Group 1 Registers 113 case MISCREG_ICC_AP1R0: 114 case MISCREG_ICC_AP1R0_EL1: { 115 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 116 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 117 } 118 119 break; 120 } 121 122 case MISCREG_ICC_AP1R1: 123 case MISCREG_ICC_AP1R1_EL1: 124 125 // only implemented if supporting 6 or more bits of priority 126 case MISCREG_ICC_AP1R2: 127 case MISCREG_ICC_AP1R2_EL1: 128 129 // only implemented if supporting 7 or more bits of priority 130 case MISCREG_ICC_AP1R3: 131 case MISCREG_ICC_AP1R3_EL1: 132 // only implemented if supporting 7 or more bits of priority 133 return 0; 134 135 // Active Priorities Group 0 Registers 136 case MISCREG_ICC_AP0R0: 137 case MISCREG_ICC_AP0R0_EL1: { 138 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 139 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 140 } 141 142 break; 143 } 144 145 case MISCREG_ICC_AP0R1: 146 case MISCREG_ICC_AP0R1_EL1: 147 148 // only implemented if supporting 6 or more bits of priority 149 case MISCREG_ICC_AP0R2: 150 case MISCREG_ICC_AP0R2_EL1: 151 152 // only implemented if supporting 7 or more bits of priority 153 case MISCREG_ICC_AP0R3: 154 case MISCREG_ICC_AP0R3_EL1: 155 // only implemented if supporting 7 or more bits of priority 156 return 0; 157 158 // Interrupt Group 0 Enable register EL1 159 case MISCREG_ICC_IGRPEN0: 160 case MISCREG_ICC_IGRPEN0_EL1: { 161 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 162 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1); 163 } 164 165 break; 166 } 167 168 // Interrupt Group 1 Enable register EL1 169 case MISCREG_ICC_IGRPEN1: 170 case MISCREG_ICC_IGRPEN1_EL1: { 171 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 172 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1); 173 } 174 175 break; 176 } 177 178 // Interrupt Group 1 Enable register EL3 179 case MISCREG_ICC_MGRPEN1: 180 case MISCREG_ICC_IGRPEN1_EL3: 181 break; 182 183 // Running Priority Register 184 case MISCREG_ICC_RPR: 185 case MISCREG_ICC_RPR_EL1: { 186 if ((currEL() == EL1) && !inSecureState() && 187 (hcr_imo || hcr_fmo)) { 188 return readMiscReg(MISCREG_ICV_RPR_EL1); 189 } 190 191 uint8_t rprio = highestActivePriority(); 192 193 if (haveEL(EL3) && !inSecureState() && 194 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 195 // Spec section 4.8.1 196 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 197 if ((rprio & 0x80) == 0) { 198 // If the current priority mask value is in the range of 199 // 0x00-0x7F a read access returns the value 0x0 200 rprio = 0; 201 } else if (rprio != 0xff) { 202 // If the current priority mask value is in the range of 203 // 0x80-0xFF a read access returns the Non-secure read of 204 // the current value 205 rprio = (rprio << 1) & 0xff; 206 } 207 } 208 209 value = rprio; 210 break; 211 } 212 213 // Virtual Running Priority Register 214 case MISCREG_ICV_RPR_EL1: { 215 value = virtualHighestActivePriority(); 216 break; 217 } 218 219 // Highest Priority Pending Interrupt Register 0 220 case MISCREG_ICC_HPPIR0: 221 case MISCREG_ICC_HPPIR0_EL1: { 222 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 223 return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 224 } 225 226 value = getHPPIR0(); 227 break; 228 } 229 230 // Virtual Highest Priority Pending Interrupt Register 0 231 case MISCREG_ICV_HPPIR0_EL1: { 232 value = Gicv3::INTID_SPURIOUS; 233 int lr_idx = getHPPVILR(); 234 235 if (lr_idx >= 0) { 236 ICH_LR_EL2 ich_lr_el2 = 237 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 238 Gicv3::GroupId group = 239 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 240 241 if (group == Gicv3::G0S) { 242 value = ich_lr_el2.vINTID; 243 } 244 } 245 246 break; 247 } 248 249 // Highest Priority Pending Interrupt Register 1 250 case MISCREG_ICC_HPPIR1: 251 case MISCREG_ICC_HPPIR1_EL1: { 252 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 253 return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 254 } 255 256 value = getHPPIR1(); 257 break; 258 } 259 260 // Virtual Highest Priority Pending Interrupt Register 1 261 case MISCREG_ICV_HPPIR1_EL1: { 262 value = Gicv3::INTID_SPURIOUS; 263 int lr_idx = getHPPVILR(); 264 265 if (lr_idx >= 0) { 266 ICH_LR_EL2 ich_lr_el2 = 267 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 268 Gicv3::GroupId group = 269 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 270 271 if (group == Gicv3::G1NS) { 272 value = ich_lr_el2.vINTID; 273 } 274 } 275 276 break; 277 } 278 279 // Binary Point Register 0 280 case MISCREG_ICC_BPR0: 281 case MISCREG_ICC_BPR0_EL1: 282 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 283 return readMiscReg(MISCREG_ICV_BPR0_EL1); 284 } 285 286 M5_FALLTHROUGH; 287 288 // Binary Point Register 1 289 case MISCREG_ICC_BPR1: 290 case MISCREG_ICC_BPR1_EL1: { 291 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 292 return readMiscReg(MISCREG_ICV_BPR1_EL1); 293 } 294 295 Gicv3::GroupId group = 296 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 297 298 if (group == Gicv3::G1S && !inSecureState()) { 299 group = Gicv3::G1NS; 300 } 301 302 ICC_CTLR_EL1 icc_ctlr_el1_s = 303 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 304 305 if ((group == Gicv3::G1S) && !isEL3OrMon() && 306 icc_ctlr_el1_s.CBPR) { 307 group = Gicv3::G0S; 308 } 309 310 bool sat_inc = false; 311 312 ICC_CTLR_EL1 icc_ctlr_el1_ns = 313 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 314 315 if ((group == Gicv3::G1NS) && (currEL() < EL3) && 316 icc_ctlr_el1_ns.CBPR) { 317 // Reads return BPR0 + 1 saturated to 7, WI 318 group = Gicv3::G0S; 319 sat_inc = true; 320 } 321 322 uint8_t bpr; 323 324 if (group == Gicv3::G0S) { 325 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 326 } else { 327 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1); 328 bpr = std::max(bpr, group == Gicv3::G1S ? 329 GIC_MIN_BPR : GIC_MIN_BPR_NS); 330 } 331 332 if (sat_inc) { 333 bpr++; 334 335 if (bpr > 7) { 336 bpr = 7; 337 } 338 } 339 340 value = bpr; 341 break; 342 } 343 344 // Virtual Binary Point Register 1 345 case MISCREG_ICV_BPR0_EL1: 346 case MISCREG_ICV_BPR1_EL1: { 347 Gicv3::GroupId group = 348 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 349 ICH_VMCR_EL2 ich_vmcr_el2 = 350 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 351 bool sat_inc = false; 352 353 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 354 // bpr0 + 1 saturated to 7, WI 355 group = Gicv3::G0S; 356 sat_inc = true; 357 } 358 359 uint8_t vbpr; 360 361 if (group == Gicv3::G0S) { 362 vbpr = ich_vmcr_el2.VBPR0; 363 } else { 364 vbpr = ich_vmcr_el2.VBPR1; 365 } 366 367 if (sat_inc) { 368 vbpr++; 369 370 if (vbpr > 7) { 371 vbpr = 7; 372 } 373 } 374 375 value = vbpr; 376 break; 377 } 378 379 // Interrupt Priority Mask Register 380 case MISCREG_ICC_PMR: 381 case MISCREG_ICC_PMR_EL1: 382 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 383 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1); 384 } 385 386 if (haveEL(EL3) && !inSecureState() && 387 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 388 // Spec section 4.8.1 389 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: 390 if ((value & 0x80) == 0) { 391 // If the current priority mask value is in the range of 392 // 0x00-0x7F a read access returns the value 0x00. 393 value = 0; 394 } else if (value != 0xff) { 395 // If the current priority mask value is in the range of 396 // 0x80-0xFF a read access returns the Non-secure read of the 397 // current value. 398 value = (value << 1) & 0xff; 399 } 400 } 401 402 break; 403 404 // Interrupt Acknowledge Register 0 405 case MISCREG_ICC_IAR0: 406 case MISCREG_ICC_IAR0_EL1: { 407 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 408 return readMiscReg(MISCREG_ICV_IAR0_EL1); 409 } 410 411 uint32_t int_id; 412 413 if (hppiCanPreempt()) { 414 int_id = getHPPIR0(); 415 416 // avoid activation for special interrupts 417 if (int_id < Gicv3::INTID_SECURE || 418 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 419 activateIRQ(int_id, hppi.group); 420 } 421 } else { 422 int_id = Gicv3::INTID_SPURIOUS; 423 } 424 425 value = int_id; 426 break; 427 } 428 429 // Virtual Interrupt Acknowledge Register 0 430 case MISCREG_ICV_IAR0_EL1: { 431 int lr_idx = getHPPVILR(); 432 uint32_t int_id = Gicv3::INTID_SPURIOUS; 433 434 if (lr_idx >= 0) { 435 ICH_LR_EL2 ich_lr_el2 = 436 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 437 438 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 439 int_id = ich_lr_el2.vINTID; 440 441 if (int_id < Gicv3::INTID_SECURE || 442 int_id > Gicv3::INTID_SPURIOUS) { 443 virtualActivateIRQ(lr_idx); 444 } else { 445 // Bogus... Pseudocode says: 446 // - Move from pending to invalid... 447 // - Return de bogus id... 448 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 449 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 450 ich_lr_el2); 451 } 452 } 453 } 454 455 value = int_id; 456 virtualUpdate(); 457 break; 458 } 459 460 // Interrupt Acknowledge Register 1 461 case MISCREG_ICC_IAR1: 462 case MISCREG_ICC_IAR1_EL1: { 463 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 464 return readMiscReg(MISCREG_ICV_IAR1_EL1); 465 } 466 467 uint32_t int_id; 468 469 if (hppiCanPreempt()) { 470 int_id = getHPPIR1(); 471 472 // avoid activation for special interrupts 473 if (int_id < Gicv3::INTID_SECURE || 474 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 475 activateIRQ(int_id, hppi.group); 476 } 477 } else { 478 int_id = Gicv3::INTID_SPURIOUS; 479 } 480 481 value = int_id; 482 break; 483 } 484 485 // Virtual Interrupt Acknowledge Register 1 486 case MISCREG_ICV_IAR1_EL1: { 487 int lr_idx = getHPPVILR(); 488 uint32_t int_id = Gicv3::INTID_SPURIOUS; 489 490 if (lr_idx >= 0) { 491 ICH_LR_EL2 ich_lr_el2 = 492 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 493 494 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 495 int_id = ich_lr_el2.vINTID; 496 497 if (int_id < Gicv3::INTID_SECURE || 498 int_id > Gicv3::INTID_SPURIOUS) { 499 virtualActivateIRQ(lr_idx); 500 } else { 501 // Bogus... Pseudocode says: 502 // - Move from pending to invalid... 503 // - Return de bogus id... 504 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 505 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 506 ich_lr_el2); 507 } 508 } 509 } 510 511 value = int_id; 512 virtualUpdate(); 513 break; 514 } 515 516 // System Register Enable Register EL1 517 case MISCREG_ICC_SRE: 518 case MISCREG_ICC_SRE_EL1: { 519 /* 520 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 521 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 522 * SRE [0] == 1 (Only system register interface supported, RAO/WI) 523 */ 524 ICC_SRE_EL1 icc_sre_el1 = 0; 525 icc_sre_el1.SRE = 1; 526 icc_sre_el1.DIB = 1; 527 icc_sre_el1.DFB = 1; 528 value = icc_sre_el1; 529 break; 530 } 531 532 // System Register Enable Register EL2 533 case MISCREG_ICC_HSRE: 534 case MISCREG_ICC_SRE_EL2: { 535 /* 536 * Enable [3] == 1 537 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) 538 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 539 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 540 * SRE [0] == 1 (Only system register interface supported, RAO/WI) 541 */ 542 ICC_SRE_EL2 icc_sre_el2 = 0; 543 icc_sre_el2.SRE = 1; 544 icc_sre_el2.DIB = 1; 545 icc_sre_el2.DFB = 1; 546 icc_sre_el2.Enable = 1; 547 value = icc_sre_el2; 548 break; 549 } 550 551 // System Register Enable Register EL3 552 case MISCREG_ICC_MSRE: 553 case MISCREG_ICC_SRE_EL3: { 554 /* 555 * Enable [3] == 1 556 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 557 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 558 * RAO/WI) 559 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 560 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 561 * SRE [0] == 1 (Only system register interface supported, RAO/WI) 562 */ 563 ICC_SRE_EL3 icc_sre_el3 = 0; 564 icc_sre_el3.SRE = 1; 565 icc_sre_el3.DIB = 1; 566 icc_sre_el3.DFB = 1; 567 icc_sre_el3.Enable = 1; 568 value = icc_sre_el3; 569 break; 570 } 571 572 // Control Register 573 case MISCREG_ICC_CTLR: 574 case MISCREG_ICC_CTLR_EL1: { 575 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 576 return readMiscReg(MISCREG_ICV_CTLR_EL1); 577 } 578 579 // Enforce value for RO bits 580 // ExtRange [19], INTIDs in the range 1024..8191 not supported 581 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 582 // A3V [15], supports non-zero values of the Aff3 field in SGI 583 // generation System registers 584 // SEIS [14], does not support generation of SEIs (deprecated) 585 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 586 // PRIbits [10:8], number of priority bits implemented, minus one 587 ICC_CTLR_EL1 icc_ctlr_el1 = value; 588 icc_ctlr_el1.ExtRange = 0; 589 icc_ctlr_el1.RSS = 1; 590 icc_ctlr_el1.A3V = 1; 591 icc_ctlr_el1.SEIS = 0; 592 icc_ctlr_el1.IDbits = 1; 593 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 594 value = icc_ctlr_el1; 595 break; 596 } 597 598 // Virtual Control Register 599 case MISCREG_ICV_CTLR_EL1: { 600 ICV_CTLR_EL1 icv_ctlr_el1 = value; 601 icv_ctlr_el1.RSS = 0; 602 icv_ctlr_el1.A3V = 1; 603 icv_ctlr_el1.SEIS = 0; 604 icv_ctlr_el1.IDbits = 1; 605 icv_ctlr_el1.PRIbits = 7; 606 value = icv_ctlr_el1; 607 break; 608 } 609 610 // Control Register 611 case MISCREG_ICC_MCTLR: 612 case MISCREG_ICC_CTLR_EL3: { 613 // Enforce value for RO bits 614 // ExtRange [19], INTIDs in the range 1024..8191 not supported 615 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 616 // nDS [17], supports disabling of security 617 // A3V [15], supports non-zero values of the Aff3 field in SGI 618 // generation System registers 619 // SEIS [14], does not support generation of SEIs (deprecated) 620 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 621 // PRIbits [10:8], number of priority bits implemented, minus one 622 ICC_CTLR_EL3 icc_ctlr_el3 = value; 623 icc_ctlr_el3.ExtRange = 0; 624 icc_ctlr_el3.RSS = 1; 625 icc_ctlr_el3.nDS = 0; 626 icc_ctlr_el3.A3V = 1; 627 icc_ctlr_el3.SEIS = 0; 628 icc_ctlr_el3.IDbits = 0; 629 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 630 value = icc_ctlr_el3; 631 break; 632 } 633 634 // Hyp Control Register 635 case MISCREG_ICH_HCR: 636 case MISCREG_ICH_HCR_EL2: 637 break; 638 639 // Hyp Active Priorities Group 0 Registers 640 case MISCREG_ICH_AP0R0: 641 case MISCREG_ICH_AP0R0_EL2: 642 break; 643 644 // Hyp Active Priorities Group 1 Registers 645 case MISCREG_ICH_AP1R0: 646 case MISCREG_ICH_AP1R0_EL2: 647 break; 648 649 // Maintenance Interrupt State Register 650 case MISCREG_ICH_MISR: 651 case MISCREG_ICH_MISR_EL2: 652 value = maintenanceInterruptStatus(); 653 break; 654 655 // VGIC Type Register 656 case MISCREG_ICH_VTR: 657 case MISCREG_ICH_VTR_EL2: { 658 ICH_VTR_EL2 ich_vtr_el2 = value; 659 660 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 661 ich_vtr_el2.A3V = 1; 662 ich_vtr_el2.IDbits = 1; 663 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 664 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; 665 666 value = ich_vtr_el2; 667 break; 668 } 669 670 // End of Interrupt Status Register 671 case MISCREG_ICH_EISR: 672 case MISCREG_ICH_EISR_EL2: 673 value = eoiMaintenanceInterruptStatus(); 674 break; 675 676 // Empty List Register Status Register 677 case MISCREG_ICH_ELRSR: 678 case MISCREG_ICH_ELRSR_EL2: 679 value = 0; 680 681 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 682 ICH_LR_EL2 ich_lr_el2 = 683 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 684 685 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 686 (ich_lr_el2.HW || !ich_lr_el2.EOI)) { 687 value |= (1 << lr_idx); 688 } 689 } 690 691 break; 692 693 // List Registers 694 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 695 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 696 value = value >> 32; 697 break; 698 699 // List Registers 700 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 701 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 702 value = value & 0xffffffff; 703 break; 704 705 // List Registers 706 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 707 break; 708 709 // Virtual Machine Control Register 710 case MISCREG_ICH_VMCR: 711 case MISCREG_ICH_VMCR_EL2: 712 break; 713 714 default: 715 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 716 misc_reg, miscRegName[misc_reg]); 717 } 718 719 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 720 miscRegName[misc_reg], value); 721 return value; 722} 723 724void 725Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 726{ 727 bool do_virtual_update = false; 728 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 729 miscRegName[misc_reg], val); 730 bool hcr_fmo = getHCREL2FMO(); 731 bool hcr_imo = getHCREL2IMO(); 732 733 switch (misc_reg) { 734 // Active Priorities Group 1 Registers 735 case MISCREG_ICC_AP1R0: 736 case MISCREG_ICC_AP1R0_EL1: 737 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 738 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 739 } 740 741 break; 742 743 case MISCREG_ICC_AP1R1: 744 case MISCREG_ICC_AP1R1_EL1: 745 746 // only implemented if supporting 6 or more bits of priority 747 case MISCREG_ICC_AP1R2: 748 case MISCREG_ICC_AP1R2_EL1: 749 750 // only implemented if supporting 7 or more bits of priority 751 case MISCREG_ICC_AP1R3: 752 case MISCREG_ICC_AP1R3_EL1: 753 // only implemented if supporting 7 or more bits of priority 754 break; 755 756 // Active Priorities Group 0 Registers 757 case MISCREG_ICC_AP0R0: 758 case MISCREG_ICC_AP0R0_EL1: 759 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 760 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 761 } 762 763 break; 764 765 case MISCREG_ICC_AP0R1: 766 case MISCREG_ICC_AP0R1_EL1: 767 768 // only implemented if supporting 6 or more bits of priority 769 case MISCREG_ICC_AP0R2: 770 case MISCREG_ICC_AP0R2_EL1: 771 772 // only implemented if supporting 7 or more bits of priority 773 case MISCREG_ICC_AP0R3: 774 case MISCREG_ICC_AP0R3_EL1: 775 // only implemented if supporting 7 or more bits of priority 776 break; 777 778 // End Of Interrupt Register 0 779 case MISCREG_ICC_EOIR0: 780 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 781 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 782 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 783 } 784 785 int int_id = val & 0xffffff; 786 787 // avoid activation for special interrupts 788 if (int_id >= Gicv3::INTID_SECURE && 789 int_id <= Gicv3::INTID_SPURIOUS) { 790 return; 791 } 792 793 Gicv3::GroupId group = Gicv3::G0S; 794 795 if (highestActiveGroup() != group) { 796 return; 797 } 798 799 dropPriority(group); 800 801 if (!isEOISplitMode()) { 802 deactivateIRQ(int_id, group); 803 } 804 805 break; 806 } 807 808 // Virtual End Of Interrupt Register 0 809 case MISCREG_ICV_EOIR0_EL1: { 810 int int_id = val & 0xffffff; 811 812 // avoid deactivation for special interrupts 813 if (int_id >= Gicv3::INTID_SECURE && 814 int_id <= Gicv3::INTID_SPURIOUS) { 815 return; 816 } 817 818 uint8_t drop_prio = virtualDropPriority(); 819 820 if (drop_prio == 0xff) { 821 return; 822 } 823 824 int lr_idx = virtualFindActive(int_id); 825 826 if (lr_idx < 0) { 827 // No LR found matching 828 virtualIncrementEOICount(); 829 } else { 830 ICH_LR_EL2 ich_lr_el2 = 831 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 832 Gicv3::GroupId lr_group = 833 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 834 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 835 836 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) { 837 //if (!virtualIsEOISplitMode()) 838 { 839 virtualDeactivateIRQ(lr_idx); 840 } 841 } 842 } 843 844 virtualUpdate(); 845 break; 846 } 847 848 // End Of Interrupt Register 1 849 case MISCREG_ICC_EOIR1: 850 case MISCREG_ICC_EOIR1_EL1: { 851 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 852 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 853 } 854 855 int int_id = val & 0xffffff; 856 857 // avoid deactivation for special interrupts 858 if (int_id >= Gicv3::INTID_SECURE && 859 int_id <= Gicv3::INTID_SPURIOUS) { 860 return; 861 } 862 863 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 864 865 if (highestActiveGroup() == Gicv3::G0S) { 866 return; 867 } 868 869 if (distributor->DS == 0) { 870 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 871 return; 872 } else if (highestActiveGroup() == Gicv3::G1NS && 873 !(!inSecureState() or (currEL() == EL3))) { 874 return; 875 } 876 } 877 878 dropPriority(group); 879 880 if (!isEOISplitMode()) { 881 deactivateIRQ(int_id, group); 882 } 883 884 break; 885 } 886 887 // Virtual End Of Interrupt Register 1 888 case MISCREG_ICV_EOIR1_EL1: { 889 int int_id = val & 0xffffff; 890 891 // avoid deactivation for special interrupts 892 if (int_id >= Gicv3::INTID_SECURE && 893 int_id <= Gicv3::INTID_SPURIOUS) { 894 return; 895 } 896 897 uint8_t drop_prio = virtualDropPriority(); 898 899 if (drop_prio == 0xff) { 900 return; 901 } 902 903 int lr_idx = virtualFindActive(int_id); 904 905 if (lr_idx < 0) { 906 // No matching LR found 907 virtualIncrementEOICount(); 908 } else { 909 ICH_LR_EL2 ich_lr_el2 = 910 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 911 Gicv3::GroupId lr_group = 912 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 913 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 914 915 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 916 if (!virtualIsEOISplitMode()) { 917 virtualDeactivateIRQ(lr_idx); 918 } 919 } 920 } 921 922 virtualUpdate(); 923 break; 924 } 925 926 // Deactivate Interrupt Register 927 case MISCREG_ICC_DIR: 928 case MISCREG_ICC_DIR_EL1: { 929 if ((currEL() == EL1) && !inSecureState() && 930 (hcr_imo || hcr_fmo)) { 931 return setMiscReg(MISCREG_ICV_DIR_EL1, val); 932 } 933 934 int int_id = val & 0xffffff; 935 936 // The following checks are as per spec pseudocode 937 // aarch64/support/ICC_DIR_EL1 938 939 // Check for spurious ID 940 if (int_id >= Gicv3::INTID_SECURE) { 941 return; 942 } 943 944 // EOI mode is not set, so don't deactivate 945 if (!isEOISplitMode()) { 946 return; 947 } 948 949 Gicv3::GroupId group = 950 int_id >= 32 ? distributor->getIntGroup(int_id) : 951 redistributor->getIntGroup(int_id); 952 bool irq_is_grp0 = group == Gicv3::G0S; 953 bool single_sec_state = distributor->DS; 954 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 955 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 956 bool route_fiq_to_el3 = scr_el3.fiq; 957 bool route_irq_to_el3 = scr_el3.irq; 958 bool route_fiq_to_el2 = hcr_fmo; 959 bool route_irq_to_el2 = hcr_imo; 960 961 switch (currEL()) { 962 case EL3: 963 break; 964 965 case EL2: 966 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 967 break; 968 } 969 970 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 971 break; 972 } 973 974 return; 975 976 case EL1: 977 if (!isSecureBelowEL3()) { 978 if (single_sec_state && irq_is_grp0 && 979 !route_fiq_to_el3 && !route_fiq_to_el2) { 980 break; 981 } 982 983 if (!irq_is_secure && !irq_is_grp0 && 984 !route_irq_to_el3 && !route_irq_to_el2) { 985 break; 986 } 987 } else { 988 if (irq_is_grp0 && !route_fiq_to_el3) { 989 break; 990 } 991 992 if (!irq_is_grp0 && 993 (!irq_is_secure || !single_sec_state) && 994 !route_irq_to_el3) { 995 break; 996 } 997 } 998 999 return; 1000 1001 default: 1002 break; 1003 } 1004 1005 deactivateIRQ(int_id, group); 1006 break; 1007 } 1008 1009 // Deactivate Virtual Interrupt Register 1010 case MISCREG_ICV_DIR_EL1: { 1011 int int_id = val & 0xffffff; 1012 1013 // avoid deactivation for special interrupts 1014 if (int_id >= Gicv3::INTID_SECURE && 1015 int_id <= Gicv3::INTID_SPURIOUS) { 1016 return; 1017 } 1018 1019 if (!virtualIsEOISplitMode()) { 1020 return; 1021 } 1022 1023 int lr_idx = virtualFindActive(int_id); 1024 1025 if (lr_idx < 0) { 1026 // No matching LR found 1027 virtualIncrementEOICount(); 1028 } else { 1029 virtualDeactivateIRQ(lr_idx); 1030 } 1031 1032 virtualUpdate(); 1033 break; 1034 } 1035 1036 // Binary Point Register 0 1037 case MISCREG_ICC_BPR0: 1038 case MISCREG_ICC_BPR0_EL1: 1039 // Binary Point Register 1 1040 case MISCREG_ICC_BPR1: 1041 case MISCREG_ICC_BPR1_EL1: { 1042 if ((currEL() == EL1) && !inSecureState()) { 1043 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) { 1044 return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 1045 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) { 1046 return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 1047 } 1048 } 1049 1050 Gicv3::GroupId group = 1051 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 1052 1053 if (group == Gicv3::G1S && !inSecureState()) { 1054 group = Gicv3::G1NS; 1055 } 1056 1057 ICC_CTLR_EL1 icc_ctlr_el1_s = 1058 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 1059 1060 if ((group == Gicv3::G1S) && !isEL3OrMon() && 1061 icc_ctlr_el1_s.CBPR) { 1062 group = Gicv3::G0S; 1063 } 1064 1065 ICC_CTLR_EL1 icc_ctlr_el1_ns = 1066 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 1067 1068 if ((group == Gicv3::G1NS) && (currEL() < EL3) && 1069 icc_ctlr_el1_ns.CBPR) { 1070 // BPR0 + 1 saturated to 7, WI 1071 return; 1072 } 1073 1074 uint8_t min_val = (group == Gicv3::G1NS) ? 1075 GIC_MIN_BPR_NS : GIC_MIN_BPR; 1076 val &= 0x7; 1077 1078 if (val < min_val) { 1079 val = min_val; 1080 } 1081 1082 break; 1083 } 1084 1085 // Virtual Binary Point Register 0 1086 case MISCREG_ICV_BPR0_EL1: 1087 // Virtual Binary Point Register 1 1088 case MISCREG_ICV_BPR1_EL1: { 1089 Gicv3::GroupId group = 1090 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 1091 ICH_VMCR_EL2 ich_vmcr_el2 = 1092 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1093 1094 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 1095 // BPR0 + 1 saturated to 7, WI 1096 return; 1097 } 1098 1099 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 1100 1101 if (group != Gicv3::G0S) { 1102 min_VPBR++; 1103 } 1104 1105 if (val < min_VPBR) { 1106 val = min_VPBR; 1107 } 1108 1109 if (group == Gicv3::G0S) { 1110 ich_vmcr_el2.VBPR0 = val; 1111 } else { 1112 ich_vmcr_el2.VBPR1 = val; 1113 } 1114 1115 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1116 do_virtual_update = true; 1117 break; 1118 } 1119 1120 // Control Register EL1 1121 case MISCREG_ICC_CTLR: 1122 case MISCREG_ICC_CTLR_EL1: { 1123 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 1124 return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 1125 } 1126 1127 /* 1128 * ExtRange is RO. 1129 * RSS is RO. 1130 * A3V is RO. 1131 * SEIS is RO. 1132 * IDbits is RO. 1133 * PRIbits is RO. 1134 */ 1135 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 1136 ICC_CTLR_EL1 icc_ctlr_el1 = 1137 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 1138 1139 ICC_CTLR_EL3 icc_ctlr_el3 = 1140 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 1141 1142 // The following could be refactored but it is following 1143 // spec description section 9.2.6 point by point. 1144 1145 // PMHE 1146 if (haveEL(EL3)) { 1147 // PMHE is alias of ICC_CTLR_EL3.PMHE 1148 1149 if (distributor->DS == 0) { 1150 // PMHE is RO 1151 } else if (distributor->DS == 1) { 1152 // PMHE is RW 1153 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 1154 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 1155 } 1156 } else { 1157 // PMHE is RW (by implementation choice) 1158 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 1159 } 1160 1161 // EOImode 1162 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 1163 1164 if (inSecureState()) { 1165 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 1166 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 1167 } else { 1168 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 1169 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 1170 } 1171 1172 // CBPR 1173 if (haveEL(EL3)) { 1174 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 1175 1176 if (distributor->DS == 0) { 1177 // CBPR is RO 1178 } else { 1179 // CBPR is RW 1180 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 1181 1182 if (inSecureState()) { 1183 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 1184 } else { 1185 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 1186 } 1187 } 1188 } else { 1189 // CBPR is RW 1190 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 1191 } 1192 1193 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 1194 1195 val = icc_ctlr_el1; 1196 break; 1197 } 1198 1199 // Virtual Control Register 1200 case MISCREG_ICV_CTLR_EL1: { 1201 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 1202 ICV_CTLR_EL1 icv_ctlr_el1 = 1203 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 1204 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 1205 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 1206 val = icv_ctlr_el1; 1207 1208 // Aliases 1209 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 1210 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 1211 ICH_VMCR_EL2 ich_vmcr_el2 = 1212 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1213 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 1214 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 1215 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1216 break; 1217 } 1218 1219 // Control Register EL3 1220 case MISCREG_ICC_MCTLR: 1221 case MISCREG_ICC_CTLR_EL3: { 1222 /* 1223 * ExtRange is RO. 1224 * RSS is RO. 1225 * nDS is RO. 1226 * A3V is RO. 1227 * SEIS is RO. 1228 * IDbits is RO. 1229 * PRIbits is RO. 1230 * PMHE is RAO/WI, priority-based routing is always used. 1231 */ 1232 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; 1233 1234 // Aliases 1235 if (haveEL(EL3)) 1236 { 1237 ICC_CTLR_EL1 icc_ctlr_el1_s = 1238 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 1239 ICC_CTLR_EL1 icc_ctlr_el1_ns = 1240 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 1241 1242 // ICC_CTLR_EL1(NS).EOImode is an alias of 1243 // ICC_CTLR_EL3.EOImode_EL1NS 1244 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 1245 // ICC_CTLR_EL1(S).EOImode is an alias of 1246 // ICC_CTLR_EL3.EOImode_EL1S 1247 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 1248 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 1249 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 1250 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 1251 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; 1252 1253 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 1254 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 1255 icc_ctlr_el1_ns); 1256 } 1257 1258 ICC_CTLR_EL3 icc_ctlr_el3 = 1259 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 1260 1261 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 1262 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 1263 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 1264 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 1265 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 1266 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 1267 1268 val = icc_ctlr_el3; 1269 break; 1270 } 1271 1272 // Priority Mask Register 1273 case MISCREG_ICC_PMR: 1274 case MISCREG_ICC_PMR_EL1: { 1275 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 1276 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val); 1277 } 1278 1279 val &= 0xff; 1280 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 1281 1282 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) { 1283 // Spec section 4.8.1 1284 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: 1285 RegVal old_icc_pmr_el1 = 1286 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 1287 1288 if (!(old_icc_pmr_el1 & 0x80)) { 1289 // If the current priority mask value is in the range of 1290 // 0x00-0x7F then WI 1291 return; 1292 } 1293 1294 // If the current priority mask value is in the range of 1295 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 1296 // based on the Non-secure read of the priority mask value 1297 // written to the register. 1298 1299 val = (val >> 1) | 0x80; 1300 } 1301 1302 val &= ~0U << (8 - PRIORITY_BITS); 1303 break; 1304 } 1305 1306 // Interrupt Group 0 Enable Register EL1 1307 case MISCREG_ICC_IGRPEN0: 1308 case MISCREG_ICC_IGRPEN0_EL1: { 1309 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 1310 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 1311 } 1312 1313 break; 1314 } 1315 1316 // Virtual Interrupt Group 0 Enable register 1317 case MISCREG_ICV_IGRPEN0_EL1: { 1318 bool enable = val & 0x1; 1319 ICH_VMCR_EL2 ich_vmcr_el2 = 1320 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1321 ich_vmcr_el2.VENG0 = enable; 1322 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1323 virtualUpdate(); 1324 return; 1325 } 1326 1327 // Interrupt Group 1 Enable register EL1 1328 case MISCREG_ICC_IGRPEN1: 1329 case MISCREG_ICC_IGRPEN1_EL1: { 1330 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 1331 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 1332 } 1333 1334 if (haveEL(EL3)) { 1335 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val; 1336 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = 1337 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3); 1338 1339 if (inSecureState()) { 1340 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S 1341 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable; 1342 } else { 1343 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS 1344 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable; 1345 } 1346 1347 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3, 1348 icc_igrpen1_el3); 1349 } 1350 1351 break; 1352 } 1353 1354 // Virtual Interrupt Group 1 Enable register 1355 case MISCREG_ICV_IGRPEN1_EL1: { 1356 bool enable = val & 0x1; 1357 ICH_VMCR_EL2 ich_vmcr_el2 = 1358 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1359 ich_vmcr_el2.VENG1 = enable; 1360 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1361 virtualUpdate(); 1362 return; 1363 } 1364 1365 // Interrupt Group 1 Enable register 1366 case MISCREG_ICC_MGRPEN1: 1367 case MISCREG_ICC_IGRPEN1_EL3: { 1368 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 1369 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = 1370 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1); 1371 1372 if (inSecureState()) { 1373 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S 1374 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S; 1375 } else { 1376 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS 1377 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS; 1378 } 1379 1380 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1); 1381 break; 1382 } 1383 1384 // Software Generated Interrupt Group 0 Register 1385 case MISCREG_ICC_SGI0R: 1386 case MISCREG_ICC_SGI0R_EL1: 1387 1388 // Software Generated Interrupt Group 1 Register 1389 case MISCREG_ICC_SGI1R: 1390 case MISCREG_ICC_SGI1R_EL1: 1391 1392 // Alias Software Generated Interrupt Group 1 Register 1393 case MISCREG_ICC_ASGI1R: 1394 case MISCREG_ICC_ASGI1R_EL1: { 1395 bool ns = !inSecureState(); 1396 Gicv3::GroupId group; 1397 1398 if (misc_reg == MISCREG_ICC_SGI1R_EL1) { 1399 group = ns ? Gicv3::G1NS : Gicv3::G1S; 1400 } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) { 1401 group = ns ? Gicv3::G1S : Gicv3::G1NS; 1402 } else { 1403 group = Gicv3::G0S; 1404 } 1405 1406 if (distributor->DS && group == Gicv3::G1S) { 1407 group = Gicv3::G0S; 1408 } 1409 1410 uint8_t aff3 = bits(val, 55, 48); 1411 uint8_t aff2 = bits(val, 39, 32); 1412 uint8_t aff1 = bits(val, 23, 16);; 1413 uint16_t target_list = bits(val, 15, 0); 1414 uint32_t int_id = bits(val, 27, 24); 1415 bool irm = bits(val, 40, 40); 1416 uint8_t rs = bits(val, 47, 44); 1417 1418 for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 1419 Gicv3Redistributor * redistributor_i = 1420 gic->getRedistributor(i); 1421 uint32_t affinity_i = redistributor_i->getAffinity(); 1422 1423 if (irm) { 1424 // Interrupts routed to all PEs in the system, 1425 // excluding "self" 1426 if (affinity_i == redistributor->getAffinity()) { 1427 continue; 1428 } 1429 } else { 1430 // Interrupts routed to the PEs specified by 1431 // Aff3.Aff2.Aff1.<target list> 1432 if ((affinity_i >> 8) != 1433 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { 1434 continue; 1435 } 1436 1437 uint8_t aff0_i = bits(affinity_i, 7, 0); 1438 1439 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 && 1440 ((0x1 << (aff0_i - rs * 16)) & target_list))) { 1441 continue; 1442 } 1443 } 1444 1445 redistributor_i->sendSGI(int_id, group, ns); 1446 } 1447 1448 break; 1449 } 1450 1451 // System Register Enable Register EL1 1452 case MISCREG_ICC_SRE: 1453 case MISCREG_ICC_SRE_EL1: 1454 // System Register Enable Register EL2 1455 case MISCREG_ICC_HSRE: 1456 case MISCREG_ICC_SRE_EL2: 1457 // System Register Enable Register EL3 1458 case MISCREG_ICC_MSRE: 1459 case MISCREG_ICC_SRE_EL3: 1460 // All bits are RAO/WI 1461 return; 1462 1463 // Hyp Control Register 1464 case MISCREG_ICH_HCR: 1465 case MISCREG_ICH_HCR_EL2: { 1466 ICH_HCR_EL2 requested_ich_hcr_el2 = val; 1467 ICH_HCR_EL2 ich_hcr_el2 = 1468 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 1469 1470 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 1471 { 1472 // EOIcount - Permitted behaviors are: 1473 // - Increment EOIcount. 1474 // - Leave EOIcount unchanged. 1475 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 1476 } 1477 1478 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 1479 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 1480 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 1481 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 1482 ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 1483 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 1484 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 1485 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 1486 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 1487 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 1488 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 1489 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 1490 ich_hcr_el2.En = requested_ich_hcr_el2.En; 1491 val = ich_hcr_el2; 1492 do_virtual_update = true; 1493 break; 1494 } 1495 1496 // List Registers 1497 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { 1498 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 1499 ICH_LRC requested_ich_lrc = val; 1500 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 1501 1502 ich_lrc.State = requested_ich_lrc.State; 1503 ich_lrc.HW = requested_ich_lrc.HW; 1504 ich_lrc.Group = requested_ich_lrc.Group; 1505 1506 // Priority, bits [23:16] 1507 // At least five bits must be implemented. 1508 // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 1509 // We implement 5 bits. 1510 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 1511 (ich_lrc.Priority & 0x07); 1512 1513 // pINTID, bits [12:0] 1514 // When ICH_LR<n>.HW is 0 this field has the following meaning: 1515 // - Bits[12:10] : RES0. 1516 // - Bit[9] : EOI. 1517 // - Bits[8:0] : RES0. 1518 // When ICH_LR<n>.HW is 1: 1519 // - This field is only required to implement enough bits to hold a 1520 // valid value for the implemented INTID size. Any unused higher 1521 // order bits are RES0. 1522 if (requested_ich_lrc.HW == 0) { 1523 ich_lrc.EOI = requested_ich_lrc.EOI; 1524 } else { 1525 ich_lrc.pINTID = requested_ich_lrc.pINTID; 1526 } 1527 1528 val = ich_lrc; 1529 do_virtual_update = true; 1530 break; 1531 } 1532 1533 // List Registers 1534 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 1535 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 1536 RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 1537 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 1538 do_virtual_update = true; 1539 break; 1540 } 1541 1542 // List Registers 1543 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64 1544 ICH_LR_EL2 requested_ich_lr_el2 = val; 1545 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 1546 1547 ich_lr_el2.State = requested_ich_lr_el2.State; 1548 ich_lr_el2.HW = requested_ich_lr_el2.HW; 1549 ich_lr_el2.Group = requested_ich_lr_el2.Group; 1550 1551 // Priority, bits [55:48] 1552 // At least five bits must be implemented. 1553 // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 1554 // We implement 5 bits. 1555 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 1556 (ich_lr_el2.Priority & 0x07); 1557 1558 // pINTID, bits [44:32] 1559 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 1560 // - Bits[44:42] : RES0. 1561 // - Bit[41] : EOI. 1562 // - Bits[40:32] : RES0. 1563 // When ICH_LR<n>_EL2.HW is 1: 1564 // - This field is only required to implement enough bits to hold a 1565 // valid value for the implemented INTID size. Any unused higher 1566 // order bits are RES0. 1567 if (requested_ich_lr_el2.HW == 0) { 1568 ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 1569 } else { 1570 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 1571 } 1572 1573 // vINTID, bits [31:0] 1574 // It is IMPLEMENTATION DEFINED how many bits are implemented, 1575 // though at least 16 bits must be implemented. 1576 // Unimplemented bits are RES0. 1577 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 1578 1579 val = ich_lr_el2; 1580 do_virtual_update = true; 1581 break; 1582 } 1583 1584 // Virtual Machine Control Register 1585 case MISCREG_ICH_VMCR: 1586 case MISCREG_ICH_VMCR_EL2: { 1587 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 1588 ICH_VMCR_EL2 ich_vmcr_el2 = 1589 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1590 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; 1591 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS; 1592 1593 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 1594 ich_vmcr_el2.VBPR0 = min_vpr0; 1595 } else { 1596 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 1597 } 1598 1599 uint8_t min_vpr1 = min_vpr0 + 1; 1600 1601 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 1602 ich_vmcr_el2.VBPR1 = min_vpr1; 1603 } else { 1604 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 1605 } 1606 1607 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 1608 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 1609 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 1610 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 1611 val = ich_vmcr_el2; 1612 break; 1613 } 1614 1615 // Hyp Active Priorities Group 0 Registers 1616 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3: 1617 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2: 1618 // Hyp Active Priorities Group 1 Registers 1619 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3: 1620 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2: 1621 break; 1622 1623 default: 1624 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 1625 misc_reg, miscRegName[misc_reg]); 1626 } 1627 1628 isa->setMiscRegNoEffect(misc_reg, val); 1629 1630 if (do_virtual_update) { 1631 virtualUpdate(); 1632 } 1633} 1634 1635int 1636Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const 1637{ 1638 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 1639 ICH_LR_EL2 ich_lr_el2 = 1640 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 1641 1642 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 1643 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 1644 (ich_lr_el2.vINTID == int_id)) { 1645 return lr_idx; 1646 } 1647 } 1648 1649 return -1; 1650} 1651 1652uint32_t 1653Gicv3CPUInterface::getHPPIR0() const 1654{ 1655 if (hppi.prio == 0xff) { 1656 return Gicv3::INTID_SPURIOUS; 1657 } 1658 1659 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 1660 1661 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) { 1662 // interrupt for the other state pending 1663 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 1664 } 1665 1666 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 1667 return Gicv3::INTID_SPURIOUS; 1668 } 1669 1670 if (irq_is_secure && !inSecureState()) { 1671 // Secure interrupts not visible in Non-secure 1672 return Gicv3::INTID_SPURIOUS; 1673 } 1674 1675 return hppi.intid; 1676} 1677 1678uint32_t 1679Gicv3CPUInterface::getHPPIR1() const 1680{ 1681 if (hppi.prio == 0xff) { 1682 return Gicv3::INTID_SPURIOUS; 1683 } 1684 1685 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 1686 if ((currEL() == EL3) && icc_ctlr_el3.RM) { 1687 if (hppi.group == Gicv3::G0S) { 1688 return Gicv3::INTID_SECURE; 1689 } else if (hppi.group == Gicv3::G1NS) { 1690 return Gicv3::INTID_NONSECURE; 1691 } 1692 } 1693 1694 if (hppi.group == Gicv3::G0S) { 1695 return Gicv3::INTID_SPURIOUS; 1696 } 1697 1698 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 1699 1700 if (irq_is_secure) { 1701 if (!inSecureState()) { 1702 // Secure interrupts not visible in Non-secure 1703 return Gicv3::INTID_SPURIOUS; 1704 } 1705 } else if (!isEL3OrMon() && inSecureState()) { 1706 // Group 1 non-secure interrupts not visible in Secure EL1 1707 return Gicv3::INTID_SPURIOUS; 1708 } 1709 1710 return hppi.intid; 1711} 1712 1713void 1714Gicv3CPUInterface::dropPriority(Gicv3::GroupId group) 1715{ 1716 int apr_misc_reg; 1717 RegVal apr; 1718 apr_misc_reg = group == Gicv3::G0S ? 1719 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 1720 apr = isa->readMiscRegNoEffect(apr_misc_reg); 1721 1722 if (apr) { 1723 apr &= apr - 1; 1724 isa->setMiscRegNoEffect(apr_misc_reg, apr); 1725 } 1726 1727 update(); 1728} 1729 1730uint8_t 1731Gicv3CPUInterface::virtualDropPriority() 1732{ 1733 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 1734 1735 for (int i = 0; i < apr_max; i++) { 1736 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 1737 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 1738 1739 if (!vapr0 && !vapr1) { 1740 continue; 1741 } 1742 1743 int vapr0_count = ctz32(vapr0); 1744 int vapr1_count = ctz32(vapr1); 1745 1746 if (vapr0_count <= vapr1_count) { 1747 vapr0 &= vapr0 - 1; 1748 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 1749 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 1750 } else { 1751 vapr1 &= vapr1 - 1; 1752 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 1753 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 1754 } 1755 } 1756 1757 return 0xff; 1758} 1759 1760void 1761Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 1762{ 1763 // Update active priority registers. 1764 uint32_t prio = hppi.prio & 0xf8; 1765 int apr_bit = prio >> (8 - PRIORITY_BITS); 1766 int reg_bit = apr_bit % 32; 1767 int apr_idx = group == Gicv3::G0S ? 1768 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 1769 RegVal apr = isa->readMiscRegNoEffect(apr_idx); 1770 apr |= (1 << reg_bit); 1771 isa->setMiscRegNoEffect(apr_idx, apr); 1772 1773 // Move interrupt state from pending to active. 1774 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1775 // SGI or PPI, redistributor 1776 redistributor->activateIRQ(int_id); 1777 redistributor->updateAndInformCPUInterface(); 1778 } else if (int_id < Gicv3::INTID_SECURE) { 1779 // SPI, distributor 1780 distributor->activateIRQ(int_id); 1781 distributor->updateAndInformCPUInterfaces(); 1782 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 1783 // LPI, Redistributor 1784 redistributor->setClrLPI(int_id, false); 1785 } 1786} 1787 1788void 1789Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 1790{ 1791 // Update active priority registers. 1792 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 1793 lr_idx); 1794 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 1795 uint8_t prio = ich_lr_el.Priority & 0xf8; 1796 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 1797 int reg_no = apr_bit / 32; 1798 int reg_bit = apr_bit % 32; 1799 int apr_idx = group == Gicv3::G0S ? 1800 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 1801 RegVal apr = isa->readMiscRegNoEffect(apr_idx); 1802 apr |= (1 << reg_bit); 1803 isa->setMiscRegNoEffect(apr_idx, apr); 1804 // Move interrupt state from pending to active. 1805 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 1806 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); 1807} 1808 1809void 1810Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 1811{ 1812 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1813 // SGI or PPI, redistributor 1814 redistributor->deactivateIRQ(int_id); 1815 redistributor->updateAndInformCPUInterface(); 1816 } else if (int_id < Gicv3::INTID_SECURE) { 1817 // SPI, distributor 1818 distributor->deactivateIRQ(int_id); 1819 distributor->updateAndInformCPUInterfaces(); 1820 } else { 1821 // LPI, redistributor, shouldn't deactivate 1822 redistributor->updateAndInformCPUInterface(); 1823 } 1824} 1825 1826void 1827Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 1828{ 1829 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 1830 lr_idx); 1831 1832 if (ich_lr_el2.HW) { 1833 // Deactivate the associated physical interrupt 1834 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 1835 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 1836 distributor->getIntGroup(ich_lr_el2.pINTID) : 1837 redistributor->getIntGroup(ich_lr_el2.pINTID); 1838 deactivateIRQ(ich_lr_el2.pINTID, group); 1839 } 1840 } 1841 1842 // Remove the active bit 1843 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 1844 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); 1845} 1846 1847/* 1848 * Returns the priority group field for the current BPR value for the group. 1849 * GroupBits() Pseudocode from spec. 1850 */ 1851uint32_t 1852Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) 1853{ 1854 ICC_CTLR_EL1 icc_ctlr_el1_s = 1855 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 1856 ICC_CTLR_EL1 icc_ctlr_el1_ns = 1857 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 1858 1859 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 1860 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 1861 group = Gicv3::G0S; 1862 } 1863 1864 int bpr; 1865 1866 if (group == Gicv3::G0S) { 1867 bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; 1868 } else { 1869 bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7; 1870 } 1871 1872 if (group == Gicv3::G1NS) { 1873 assert(bpr > 0); 1874 bpr--; 1875 } 1876 1877 return ~0U << (bpr + 1); 1878} 1879 1880uint32_t 1881Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const 1882{ 1883 ICH_VMCR_EL2 ich_vmcr_el2 = 1884 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1885 1886 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 1887 group = Gicv3::G0S; 1888 } 1889 1890 int bpr; 1891 1892 if (group == Gicv3::G0S) { 1893 bpr = ich_vmcr_el2.VBPR0; 1894 } else { 1895 bpr = ich_vmcr_el2.VBPR1; 1896 } 1897 1898 if (group == Gicv3::G1NS) { 1899 assert(bpr > 0); 1900 bpr--; 1901 } 1902 1903 return ~0U << (bpr + 1); 1904} 1905 1906bool 1907Gicv3CPUInterface::isEOISplitMode() const 1908{ 1909 if (isEL3OrMon()) { 1910 ICC_CTLR_EL3 icc_ctlr_el3 = 1911 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 1912 return icc_ctlr_el3.EOImode_EL3; 1913 } else { 1914 ICC_CTLR_EL1 icc_ctlr_el1 = 1915 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 1916 return icc_ctlr_el1.EOImode; 1917 } 1918} 1919 1920bool 1921Gicv3CPUInterface::virtualIsEOISplitMode() const 1922{ 1923 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1924 return ich_vmcr_el2.VEOIM; 1925} 1926 1927int 1928Gicv3CPUInterface::highestActiveGroup() const 1929{ 1930 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 1931 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 1932 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 1933 1934 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 1935 return Gicv3::G1NS; 1936 } 1937 1938 if (gq_ctz < g0_ctz) { 1939 return Gicv3::G1S; 1940 } 1941 1942 if (g0_ctz < 32) { 1943 return Gicv3::G0S; 1944 } 1945 1946 return -1; 1947} 1948 1949void 1950Gicv3CPUInterface::update() 1951{ 1952 bool signal_IRQ = false; 1953 bool signal_FIQ = false; 1954 1955 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 1956 /* 1957 * Secure enabled GIC sending a G1S IRQ to a secure disabled 1958 * CPU -> send G0 IRQ 1959 */ 1960 hppi.group = Gicv3::G0S; 1961 } 1962 1963 if (hppiCanPreempt()) { 1964 ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 1965 DPRINTF(GIC, "Gicv3CPUInterface::update(): " 1966 "posting int as %d!\n", int_type); 1967 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 1968 } 1969 1970 if (signal_IRQ) { 1971 gic->postInt(cpuId, ArmISA::INT_IRQ); 1972 } else { 1973 gic->deassertInt(cpuId, ArmISA::INT_IRQ); 1974 } 1975 1976 if (signal_FIQ) { 1977 gic->postInt(cpuId, ArmISA::INT_FIQ); 1978 } else { 1979 gic->deassertInt(cpuId, ArmISA::INT_FIQ); 1980 } 1981} 1982 1983void 1984Gicv3CPUInterface::virtualUpdate() 1985{ 1986 bool signal_IRQ = false; 1987 bool signal_FIQ = false; 1988 int lr_idx = getHPPVILR(); 1989 1990 if (lr_idx >= 0) { 1991 ICH_LR_EL2 ich_lr_el2 = 1992 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 1993 1994 if (hppviCanPreempt(lr_idx)) { 1995 if (ich_lr_el2.Group) { 1996 signal_IRQ = true; 1997 } else { 1998 signal_FIQ = true; 1999 } 2000 } 2001 } 2002 2003 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 2004 2005 if (ich_hcr_el2.En) { 2006 if (maintenanceInterruptStatus()) { 2007 maintenanceInterrupt->raise(); 2008 } 2009 } 2010 2011 if (signal_IRQ) { 2012 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 2013 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 2014 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 2015 } else { 2016 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 2017 } 2018 2019 if (signal_FIQ) { 2020 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 2021 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 2022 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 2023 } else { 2024 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 2025 } 2026} 2027 2028// Returns the index of the LR with the HPPI 2029int 2030Gicv3CPUInterface::getHPPVILR() const 2031{ 2032 int idx = -1; 2033 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 2034 2035 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { 2036 // VG0 and VG1 disabled... 2037 return idx; 2038 } 2039 2040 uint8_t highest_prio = 0xff; 2041 2042 for (int i = 0; i < 16; i++) { 2043 ICH_LR_EL2 ich_lr_el2 = 2044 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i); 2045 2046 if (ich_lr_el2.State != Gicv3::INT_PENDING) { 2047 continue; 2048 } 2049 2050 if (ich_lr_el2.Group) { 2051 // VG1 2052 if (!ich_vmcr_el2.VENG1) { 2053 continue; 2054 } 2055 } else { 2056 // VG0 2057 if (!ich_vmcr_el2.VENG0) { 2058 continue; 2059 } 2060 } 2061 2062 uint8_t prio = ich_lr_el2.Priority; 2063 2064 if (prio < highest_prio) { 2065 highest_prio = prio; 2066 idx = i; 2067 } 2068 } 2069 2070 return idx; 2071} 2072 2073bool 2074Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const 2075{ 2076 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 2077 if (!ich_hcr_el2.En) { 2078 // virtual interface is disabled 2079 return false; 2080 } 2081 2082 ICH_LR_EL2 ich_lr_el2 = 2083 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 2084 uint8_t prio = ich_lr_el2.Priority; 2085 uint8_t vpmr = 2086 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 2087 2088 if (prio >= vpmr) { 2089 // prioriry masked 2090 return false; 2091 } 2092 2093 uint8_t rprio = virtualHighestActivePriority(); 2094 2095 if (rprio == 0xff) { 2096 return true; 2097 } 2098 2099 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 2100 uint32_t prio_mask = virtualGroupPriorityMask(group); 2101 2102 if ((prio & prio_mask) < (rprio & prio_mask)) { 2103 return true; 2104 } 2105 2106 return false; 2107} 2108 2109uint8_t 2110Gicv3CPUInterface::virtualHighestActivePriority() const 2111{ 2112 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 2113 2114 for (int i = 0; i < num_aprs; i++) { 2115 RegVal vapr = 2116 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 2117 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 2118 2119 if (!vapr) { 2120 continue; 2121 } 2122 2123 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 2124 } 2125 2126 // no active interrups, return idle priority 2127 return 0xff; 2128} 2129 2130void 2131Gicv3CPUInterface::virtualIncrementEOICount() 2132{ 2133 // Increment the EOICOUNT field in ICH_HCR_EL2 2134 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 2135 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 2136 EOI_cout++; 2137 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 2138 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 2139} 2140 2141// spec section 4.6.2 2142ArmISA::InterruptTypes 2143Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const 2144{ 2145 bool is_fiq = false; 2146 2147 switch (group) { 2148 case Gicv3::G0S: 2149 is_fiq = true; 2150 break; 2151 2152 case Gicv3::G1S: 2153 is_fiq = (distributor->DS == 0) && 2154 (!inSecureState() || ((currEL() == EL3) && isAA64())); 2155 break; 2156 2157 case Gicv3::G1NS: 2158 is_fiq = (distributor->DS == 0) && inSecureState(); 2159 break; 2160 2161 default: 2162 panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 2163 } 2164 2165 if (is_fiq) { 2166 return ArmISA::INT_FIQ; 2167 } else { 2168 return ArmISA::INT_IRQ; 2169 } 2170} 2171 2172bool 2173Gicv3CPUInterface::hppiCanPreempt() 2174{ 2175 if (hppi.prio == 0xff) { 2176 // there is no pending interrupt 2177 return false; 2178 } 2179 2180 if (!groupEnabled(hppi.group)) { 2181 // group disabled at CPU interface 2182 return false; 2183 } 2184 2185 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 2186 // priority masked 2187 return false; 2188 } 2189 2190 uint8_t rprio = highestActivePriority(); 2191 2192 if (rprio == 0xff) { 2193 return true; 2194 } 2195 2196 uint32_t prio_mask = groupPriorityMask(hppi.group); 2197 2198 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 2199 return true; 2200 } 2201 2202 return false; 2203} 2204 2205uint8_t 2206Gicv3CPUInterface::highestActivePriority() const 2207{ 2208 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 2209 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 2210 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 2211 2212 if (apr) { 2213 return ctz32(apr) << (GIC_MIN_BPR + 1); 2214 } 2215 2216 // no active interrups, return idle priority 2217 return 0xff; 2218} 2219 2220bool 2221Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 2222{ 2223 switch (group) { 2224 case Gicv3::G0S: { 2225 ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 2226 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 2227 return icc_igrpen0_el1.Enable; 2228 } 2229 2230 case Gicv3::G1S: { 2231 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 2232 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 2233 return icc_igrpen1_el1_s.Enable; 2234 } 2235 2236 case Gicv3::G1NS: { 2237 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 2238 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 2239 return icc_igrpen1_el1_ns.Enable; 2240 } 2241 2242 default: 2243 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 2244 } 2245} 2246 2247bool 2248Gicv3CPUInterface::inSecureState() const 2249{ 2250 if (!gic->getSystem()->haveSecurity()) { 2251 return false; 2252 } 2253 2254 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2255 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 2256 return ArmISA::inSecureState(scr, cpsr); 2257} 2258 2259int 2260Gicv3CPUInterface::currEL() const 2261{ 2262 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2263 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 2264 2265 if (is_64) { 2266 return (ExceptionLevel)(uint8_t) cpsr.el; 2267 } else { 2268 switch (cpsr.mode) { 2269 case MODE_USER: 2270 return 0; 2271 2272 case MODE_HYP: 2273 return 2; 2274 2275 case MODE_MON: 2276 return 3; 2277 2278 default: 2279 return 1; 2280 } 2281 } 2282} 2283 2284bool 2285Gicv3CPUInterface::haveEL(ExceptionLevel el) const 2286{ 2287 switch (el) { 2288 case EL0: 2289 case EL1: 2290 return true; 2291 2292 case EL2: 2293 return gic->getSystem()->haveVirtualization(); 2294 2295 case EL3: 2296 return gic->getSystem()->haveSecurity(); 2297 2298 default: 2299 warn("Unimplemented Exception Level\n"); 2300 return false; 2301 } 2302} 2303 2304bool 2305Gicv3CPUInterface::isSecureBelowEL3() const 2306{ 2307 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 2308 return haveEL(EL3) && scr.ns == 0; 2309} 2310 2311bool 2312Gicv3CPUInterface::isAA64() const 2313{ 2314 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2315 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 2316} 2317 2318bool 2319Gicv3CPUInterface::isEL3OrMon() const 2320{ 2321 if (haveEL(EL3)) { 2322 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2323 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 2324 2325 if (is_64 && (cpsr.el == EL3)) { 2326 return true; 2327 } else if (!is_64 && (cpsr.mode == MODE_MON)) { 2328 return true; 2329 } 2330 } 2331 2332 return false; 2333} 2334 2335// Computes ICH_EISR_EL2 2336uint64_t 2337Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const 2338{ 2339 // ICH_EISR_EL2 2340 // Bits [63:16] - RES0 2341 // Status<n>, bit [n], for n = 0 to 15 2342 // EOI maintenance interrupt status bit for List register <n>: 2343 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 2344 // maintenance interrupt. 2345 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 2346 // interrupt that has not been handled. 2347 // 2348 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 2349 // of the following are true: 2350 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 2351 // - ICH_LR<n>_EL2.HW is 0. 2352 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. 2353 2354 uint64_t value = 0; 2355 2356 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 2357 ICH_LR_EL2 ich_lr_el2 = 2358 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 2359 2360 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 2361 !ich_lr_el2.HW && ich_lr_el2.EOI) { 2362 value |= (1 << lr_idx); 2363 } 2364 } 2365 2366 return value; 2367} 2368 2369Gicv3CPUInterface::ICH_MISR_EL2 2370Gicv3CPUInterface::maintenanceInterruptStatus() const 2371{ 2372 // Comments are copied from SPEC section 9.4.7 (ID012119) 2373 ICH_MISR_EL2 ich_misr_el2 = 0; 2374 ICH_HCR_EL2 ich_hcr_el2 = 2375 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 2376 ICH_VMCR_EL2 ich_vmcr_el2 = 2377 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 2378 2379 // End Of Interrupt. [bit 0] 2380 // This maintenance interrupt is asserted when at least one bit in 2381 // ICH_EISR_EL2 is 1. 2382 2383 if (eoiMaintenanceInterruptStatus()) { 2384 ich_misr_el2.EOI = 1; 2385 } 2386 2387 // Underflow. [bit 1] 2388 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 2389 // zero or one of the List register entries are marked as a valid 2390 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 2391 // do not equal 0x0. 2392 uint32_t num_valid_interrupts = 0; 2393 uint32_t num_pending_interrupts = 0; 2394 2395 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 2396 ICH_LR_EL2 ich_lr_el2 = 2397 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 2398 2399 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 2400 num_valid_interrupts++; 2401 } 2402 2403 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 2404 num_pending_interrupts++; 2405 } 2406 } 2407 2408 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 2409 ich_misr_el2.U = 1; 2410 } 2411 2412 // List Register Entry Not Present. [bit 2] 2413 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 2414 // and ICH_HCR_EL2.EOIcount is non-zero. 2415 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 2416 ich_misr_el2.LRENP = 1; 2417 } 2418 2419 // No Pending. [bit 3] 2420 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 2421 // no List register is in pending state. 2422 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 2423 ich_misr_el2.NP = 1; 2424 } 2425 2426 // vPE Group 0 Enabled. [bit 4] 2427 // This maintenance interrupt is asserted when 2428 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 2429 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 2430 ich_misr_el2.VGrp0E = 1; 2431 } 2432 2433 // vPE Group 0 Disabled. [bit 5] 2434 // This maintenance interrupt is asserted when 2435 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 2436 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 2437 ich_misr_el2.VGrp0D = 1; 2438 } 2439 2440 // vPE Group 1 Enabled. [bit 6] 2441 // This maintenance interrupt is asserted when 2442 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 2443 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 2444 ich_misr_el2.VGrp1E = 1; 2445 } 2446 2447 // vPE Group 1 Disabled. [bit 7] 2448 // This maintenance interrupt is asserted when 2449 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 2450 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 2451 ich_misr_el2.VGrp1D = 1; 2452 } 2453 2454 return ich_misr_el2; 2455} 2456 2457void 2458Gicv3CPUInterface::serialize(CheckpointOut & cp) const 2459{ 2460 SERIALIZE_SCALAR(hppi.intid); 2461 SERIALIZE_SCALAR(hppi.prio); 2462 SERIALIZE_ENUM(hppi.group); 2463} 2464 2465void 2466Gicv3CPUInterface::unserialize(CheckpointIn & cp) 2467{ 2468 UNSERIALIZE_SCALAR(hppi.intid); 2469 UNSERIALIZE_SCALAR(hppi.prio); 2470 UNSERIALIZE_ENUM(hppi.group); 2471} 2472