gic_v3_cpu_interface.cc revision 14254
113531Sjairo.balart@metempsy.com/* 214227Sgiacomo.travaglini@arm.com * Copyright (c) 2019 ARM Limited 314227Sgiacomo.travaglini@arm.com * All rights reserved 414227Sgiacomo.travaglini@arm.com * 514227Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614227Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714227Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814227Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914227Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014227Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114227Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214227Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314227Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 1513531Sjairo.balart@metempsy.com * All rights reserved. 1613531Sjairo.balart@metempsy.com * 1713531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1813531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1913531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 2013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 2113531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 2213531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2313531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2413531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2513531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2613531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913531Sjairo.balart@metempsy.com * 4013531Sjairo.balart@metempsy.com * Authors: Jairo Balart 4113531Sjairo.balart@metempsy.com */ 4213531Sjairo.balart@metempsy.com 4313531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 4413531Sjairo.balart@metempsy.com 4513531Sjairo.balart@metempsy.com#include "arch/arm/isa.hh" 4613531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 4713531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 4813531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 4913531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 5013531Sjairo.balart@metempsy.com 5113926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR; 5213926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; 5313926Sgiacomo.travaglini@arm.com 5413531Sjairo.balart@metempsy.comGicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 5513531Sjairo.balart@metempsy.com : BaseISADevice(), 5613531Sjairo.balart@metempsy.com gic(gic), 5713531Sjairo.balart@metempsy.com redistributor(nullptr), 5813531Sjairo.balart@metempsy.com distributor(nullptr), 5913531Sjairo.balart@metempsy.com cpuId(cpu_id) 6013531Sjairo.balart@metempsy.com{ 6113531Sjairo.balart@metempsy.com} 6213531Sjairo.balart@metempsy.com 6313531Sjairo.balart@metempsy.comvoid 6413531Sjairo.balart@metempsy.comGicv3CPUInterface::init() 6513531Sjairo.balart@metempsy.com{ 6613531Sjairo.balart@metempsy.com redistributor = gic->getRedistributor(cpuId); 6713531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 6813531Sjairo.balart@metempsy.com} 6913531Sjairo.balart@metempsy.com 7013531Sjairo.balart@metempsy.comvoid 7113531Sjairo.balart@metempsy.comGicv3CPUInterface::initState() 7213531Sjairo.balart@metempsy.com{ 7313531Sjairo.balart@metempsy.com reset(); 7413531Sjairo.balart@metempsy.com} 7513531Sjairo.balart@metempsy.com 7613531Sjairo.balart@metempsy.comvoid 7713531Sjairo.balart@metempsy.comGicv3CPUInterface::reset() 7813531Sjairo.balart@metempsy.com{ 7913531Sjairo.balart@metempsy.com hppi.prio = 0xff; 8013531Sjairo.balart@metempsy.com} 8113531Sjairo.balart@metempsy.com 8213826Sgiacomo.travaglini@arm.comvoid 8313826Sgiacomo.travaglini@arm.comGicv3CPUInterface::setThreadContext(ThreadContext *tc) 8413826Sgiacomo.travaglini@arm.com{ 8513826Sgiacomo.travaglini@arm.com maintenanceInterrupt = gic->params()->maint_int->get(tc); 8613826Sgiacomo.travaglini@arm.com} 8713826Sgiacomo.travaglini@arm.com 8813531Sjairo.balart@metempsy.combool 8913760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2FMO() const 9013531Sjairo.balart@metempsy.com{ 9113531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 9213531Sjairo.balart@metempsy.com 9313531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 9413531Sjairo.balart@metempsy.com return false; 9513531Sjairo.balart@metempsy.com } else if (hcr.tge) { 9613531Sjairo.balart@metempsy.com return true; 9713531Sjairo.balart@metempsy.com } else { 9813531Sjairo.balart@metempsy.com return hcr.fmo; 9913531Sjairo.balart@metempsy.com } 10013531Sjairo.balart@metempsy.com} 10113531Sjairo.balart@metempsy.com 10213531Sjairo.balart@metempsy.combool 10313760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2IMO() const 10413531Sjairo.balart@metempsy.com{ 10513531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 10613531Sjairo.balart@metempsy.com 10713531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 10813531Sjairo.balart@metempsy.com return false; 10913531Sjairo.balart@metempsy.com } else if (hcr.tge) { 11013531Sjairo.balart@metempsy.com return true; 11113531Sjairo.balart@metempsy.com } else { 11213531Sjairo.balart@metempsy.com return hcr.imo; 11313531Sjairo.balart@metempsy.com } 11413531Sjairo.balart@metempsy.com} 11513531Sjairo.balart@metempsy.com 11613580Sgabeblack@google.comRegVal 11713531Sjairo.balart@metempsy.comGicv3CPUInterface::readMiscReg(int misc_reg) 11813531Sjairo.balart@metempsy.com{ 11913580Sgabeblack@google.com RegVal value = isa->readMiscRegNoEffect(misc_reg); 12013531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 12113531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 12213531Sjairo.balart@metempsy.com 12313531Sjairo.balart@metempsy.com switch (misc_reg) { 12413760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 12513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 12613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: { 12713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 12813531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 12913531Sjairo.balart@metempsy.com } 13013531Sjairo.balart@metempsy.com 13114246Sgiacomo.travaglini@arm.com return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1); 13213531Sjairo.balart@metempsy.com } 13313531Sjairo.balart@metempsy.com 13413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 13513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 13613531Sjairo.balart@metempsy.com 13713531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 13813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 13913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 14013531Sjairo.balart@metempsy.com 14113531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 14313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 14413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14513531Sjairo.balart@metempsy.com return 0; 14613531Sjairo.balart@metempsy.com 14713760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 14813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 14913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: { 15013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 15113531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 15213531Sjairo.balart@metempsy.com } 15313531Sjairo.balart@metempsy.com 15413531Sjairo.balart@metempsy.com break; 15513531Sjairo.balart@metempsy.com } 15613531Sjairo.balart@metempsy.com 15713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 15813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 15913531Sjairo.balart@metempsy.com 16013531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 16113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 16213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 16313531Sjairo.balart@metempsy.com 16413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 16613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 16713531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16813531Sjairo.balart@metempsy.com return 0; 16913531Sjairo.balart@metempsy.com 17013760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable register EL1 17113531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 17213531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 17313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 17414057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN0_EL1); 17513531Sjairo.balart@metempsy.com } 17613531Sjairo.balart@metempsy.com 17713531Sjairo.balart@metempsy.com break; 17813531Sjairo.balart@metempsy.com } 17913531Sjairo.balart@metempsy.com 18014057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN0_EL1: { 18114057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 18214057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 18314057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG0; 18414057Sgiacomo.travaglini@arm.com break; 18514057Sgiacomo.travaglini@arm.com } 18614057Sgiacomo.travaglini@arm.com 18713760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 18813531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 18913531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 19013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 19114057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); 19213531Sjairo.balart@metempsy.com } 19313531Sjairo.balart@metempsy.com 19414247Sgiacomo.travaglini@arm.com value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1); 19513531Sjairo.balart@metempsy.com break; 19613531Sjairo.balart@metempsy.com } 19713531Sjairo.balart@metempsy.com 19814057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN1_EL1: { 19914057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 20014057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 20114057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG1; 20214057Sgiacomo.travaglini@arm.com break; 20314057Sgiacomo.travaglini@arm.com } 20414057Sgiacomo.travaglini@arm.com 20513760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL3 20613760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 20714254Sgiacomo.travaglini@arm.com case MISCREG_ICC_IGRPEN1_EL3: { 20814254Sgiacomo.travaglini@arm.com ICC_IGRPEN1_EL3 igrp_el3 = 0; 20914254Sgiacomo.travaglini@arm.com igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect( 21014254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_S)).Enable; 21114254Sgiacomo.travaglini@arm.com 21214254Sgiacomo.travaglini@arm.com igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect( 21314254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_NS)).Enable; 21414254Sgiacomo.travaglini@arm.com 21514254Sgiacomo.travaglini@arm.com value = igrp_el3; 21613739Sgiacomo.travaglini@arm.com break; 21714254Sgiacomo.travaglini@arm.com } 21813760Sjairo.balart@metempsy.com 21913760Sjairo.balart@metempsy.com // Running Priority Register 22013531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR: 22113531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR_EL1: { 22213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 22313760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 22413531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_RPR_EL1); 22513531Sjairo.balart@metempsy.com } 22613531Sjairo.balart@metempsy.com 22713531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 22813531Sjairo.balart@metempsy.com 22913531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 23013760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 23113760Sjairo.balart@metempsy.com // Spec section 4.8.1 23213760Sjairo.balart@metempsy.com // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 23313531Sjairo.balart@metempsy.com if ((rprio & 0x80) == 0) { 23413760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 23513760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x0 23613531Sjairo.balart@metempsy.com rprio = 0; 23713531Sjairo.balart@metempsy.com } else if (rprio != 0xff) { 23813760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 23913760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of 24013760Sjairo.balart@metempsy.com // the current value 24113531Sjairo.balart@metempsy.com rprio = (rprio << 1) & 0xff; 24213531Sjairo.balart@metempsy.com } 24313531Sjairo.balart@metempsy.com } 24413531Sjairo.balart@metempsy.com 24513531Sjairo.balart@metempsy.com value = rprio; 24613531Sjairo.balart@metempsy.com break; 24713531Sjairo.balart@metempsy.com } 24813531Sjairo.balart@metempsy.com 24913760Sjairo.balart@metempsy.com // Virtual Running Priority Register 25013531Sjairo.balart@metempsy.com case MISCREG_ICV_RPR_EL1: { 25113531Sjairo.balart@metempsy.com value = virtualHighestActivePriority(); 25213531Sjairo.balart@metempsy.com break; 25313531Sjairo.balart@metempsy.com } 25413531Sjairo.balart@metempsy.com 25513760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 0 25613531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0: 25713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0_EL1: { 25813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 25913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 26013531Sjairo.balart@metempsy.com } 26113531Sjairo.balart@metempsy.com 26213531Sjairo.balart@metempsy.com value = getHPPIR0(); 26313531Sjairo.balart@metempsy.com break; 26413531Sjairo.balart@metempsy.com } 26513531Sjairo.balart@metempsy.com 26613760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 0 26713531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR0_EL1: { 26813531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 26913531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 27013531Sjairo.balart@metempsy.com 27113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 27213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 27313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 27413531Sjairo.balart@metempsy.com Gicv3::GroupId group = 27513760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 27613531Sjairo.balart@metempsy.com 27713531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 27813760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 27913531Sjairo.balart@metempsy.com } 28013531Sjairo.balart@metempsy.com } 28113531Sjairo.balart@metempsy.com 28213531Sjairo.balart@metempsy.com break; 28313531Sjairo.balart@metempsy.com } 28413531Sjairo.balart@metempsy.com 28513760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 1 28613531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1: 28713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1_EL1: { 28813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 28913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 29013531Sjairo.balart@metempsy.com } 29113531Sjairo.balart@metempsy.com 29213531Sjairo.balart@metempsy.com value = getHPPIR1(); 29313531Sjairo.balart@metempsy.com break; 29413531Sjairo.balart@metempsy.com } 29513531Sjairo.balart@metempsy.com 29613760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 1 29713531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR1_EL1: { 29813531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 29913531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 30013531Sjairo.balart@metempsy.com 30113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 30213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 30313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 30413531Sjairo.balart@metempsy.com Gicv3::GroupId group = 30513760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 30613531Sjairo.balart@metempsy.com 30713531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 30813760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 30913531Sjairo.balart@metempsy.com } 31013531Sjairo.balart@metempsy.com } 31113531Sjairo.balart@metempsy.com 31213531Sjairo.balart@metempsy.com break; 31313531Sjairo.balart@metempsy.com } 31413531Sjairo.balart@metempsy.com 31513760Sjairo.balart@metempsy.com // Binary Point Register 0 31613531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 31714237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 31813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 31913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR0_EL1); 32013531Sjairo.balart@metempsy.com } 32113531Sjairo.balart@metempsy.com 32214237Sgiacomo.travaglini@arm.com value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 32314237Sgiacomo.travaglini@arm.com break; 32414237Sgiacomo.travaglini@arm.com } 32513531Sjairo.balart@metempsy.com 32613760Sjairo.balart@metempsy.com // Binary Point Register 1 32713531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 32813760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 32914237Sgiacomo.travaglini@arm.com value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS); 33014237Sgiacomo.travaglini@arm.com break; 33113760Sjairo.balart@metempsy.com } 33213760Sjairo.balart@metempsy.com 33314237Sgiacomo.travaglini@arm.com // Virtual Binary Point Register 0 33414237Sgiacomo.travaglini@arm.com case MISCREG_ICV_BPR0_EL1: { 33514237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 33614237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 33714237Sgiacomo.travaglini@arm.com 33814237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0; 33914237Sgiacomo.travaglini@arm.com break; 34014237Sgiacomo.travaglini@arm.com } 34114237Sgiacomo.travaglini@arm.com 34213760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 34313531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 34414237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 34514237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 34614237Sgiacomo.travaglini@arm.com 34714237Sgiacomo.travaglini@arm.com if (ich_vmcr_el2.VCBPR) { 34814237Sgiacomo.travaglini@arm.com // bpr0 + 1 saturated to 7, WI 34914237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0 + 1; 35014237Sgiacomo.travaglini@arm.com value = value < 7 ? value : 7; 35114237Sgiacomo.travaglini@arm.com } else { 35214237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR1; 35314237Sgiacomo.travaglini@arm.com } 35414237Sgiacomo.travaglini@arm.com 35514237Sgiacomo.travaglini@arm.com break; 35613531Sjairo.balart@metempsy.com } 35713531Sjairo.balart@metempsy.com 35813760Sjairo.balart@metempsy.com // Interrupt Priority Mask Register 35913531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 36013760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: 36113760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 36214057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_PMR_EL1); 36313531Sjairo.balart@metempsy.com } 36413531Sjairo.balart@metempsy.com 36513531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 36613760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 36713760Sjairo.balart@metempsy.com // Spec section 4.8.1 36813760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: 36913531Sjairo.balart@metempsy.com if ((value & 0x80) == 0) { 37013760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 37113760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x00. 37213531Sjairo.balart@metempsy.com value = 0; 37313531Sjairo.balart@metempsy.com } else if (value != 0xff) { 37413760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 37513760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of the 37613760Sjairo.balart@metempsy.com // current value. 37713531Sjairo.balart@metempsy.com value = (value << 1) & 0xff; 37813531Sjairo.balart@metempsy.com } 37913531Sjairo.balart@metempsy.com } 38013531Sjairo.balart@metempsy.com 38113531Sjairo.balart@metempsy.com break; 38213531Sjairo.balart@metempsy.com 38314057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 38414057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 38514057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 38614057Sgiacomo.travaglini@arm.com 38714057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VPMR; 38814057Sgiacomo.travaglini@arm.com break; 38914057Sgiacomo.travaglini@arm.com } 39014057Sgiacomo.travaglini@arm.com 39113760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 0 39213531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0: 39313760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0_EL1: { 39413531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 39513531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR0_EL1); 39613531Sjairo.balart@metempsy.com } 39713531Sjairo.balart@metempsy.com 39813531Sjairo.balart@metempsy.com uint32_t int_id; 39913531Sjairo.balart@metempsy.com 40013531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 40113531Sjairo.balart@metempsy.com int_id = getHPPIR0(); 40213531Sjairo.balart@metempsy.com 40313531Sjairo.balart@metempsy.com // avoid activation for special interrupts 40413923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 40513923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 40613531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 40713531Sjairo.balart@metempsy.com } 40813531Sjairo.balart@metempsy.com } else { 40913531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 41013531Sjairo.balart@metempsy.com } 41113531Sjairo.balart@metempsy.com 41213531Sjairo.balart@metempsy.com value = int_id; 41313531Sjairo.balart@metempsy.com break; 41413531Sjairo.balart@metempsy.com } 41513531Sjairo.balart@metempsy.com 41613760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 0 41713531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR0_EL1: { 41813531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 41913531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 42013531Sjairo.balart@metempsy.com 42113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 42213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 42313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 42413531Sjairo.balart@metempsy.com 42513760Sjairo.balart@metempsy.com if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 42613760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 42713531Sjairo.balart@metempsy.com 42813531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 42913760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 43013531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 43113531Sjairo.balart@metempsy.com } else { 43213531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 43313531Sjairo.balart@metempsy.com // - Move from pending to invalid... 43413531Sjairo.balart@metempsy.com // - Return de bogus id... 43513760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 43613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 43713760Sjairo.balart@metempsy.com ich_lr_el2); 43813531Sjairo.balart@metempsy.com } 43913531Sjairo.balart@metempsy.com } 44013531Sjairo.balart@metempsy.com } 44113531Sjairo.balart@metempsy.com 44213531Sjairo.balart@metempsy.com value = int_id; 44313531Sjairo.balart@metempsy.com virtualUpdate(); 44413531Sjairo.balart@metempsy.com break; 44513531Sjairo.balart@metempsy.com } 44613531Sjairo.balart@metempsy.com 44713760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 1 44813531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1: 44913760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1_EL1: { 45013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 45113531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR1_EL1); 45213531Sjairo.balart@metempsy.com } 45313531Sjairo.balart@metempsy.com 45413531Sjairo.balart@metempsy.com uint32_t int_id; 45513531Sjairo.balart@metempsy.com 45613531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 45713531Sjairo.balart@metempsy.com int_id = getHPPIR1(); 45813531Sjairo.balart@metempsy.com 45913531Sjairo.balart@metempsy.com // avoid activation for special interrupts 46013923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 46113923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 46213531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 46313531Sjairo.balart@metempsy.com } 46413531Sjairo.balart@metempsy.com } else { 46513531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 46613531Sjairo.balart@metempsy.com } 46713531Sjairo.balart@metempsy.com 46813531Sjairo.balart@metempsy.com value = int_id; 46913531Sjairo.balart@metempsy.com break; 47013531Sjairo.balart@metempsy.com } 47113531Sjairo.balart@metempsy.com 47213760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 1 47313531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR1_EL1: { 47413531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 47513531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 47613531Sjairo.balart@metempsy.com 47713531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 47813760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 47913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 48013531Sjairo.balart@metempsy.com 48113760Sjairo.balart@metempsy.com if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 48213760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 48313531Sjairo.balart@metempsy.com 48413531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 48513760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 48613531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 48713531Sjairo.balart@metempsy.com } else { 48813531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 48913531Sjairo.balart@metempsy.com // - Move from pending to invalid... 49013531Sjairo.balart@metempsy.com // - Return de bogus id... 49113760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 49213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 49313760Sjairo.balart@metempsy.com ich_lr_el2); 49413531Sjairo.balart@metempsy.com } 49513531Sjairo.balart@metempsy.com } 49613531Sjairo.balart@metempsy.com } 49713531Sjairo.balart@metempsy.com 49813531Sjairo.balart@metempsy.com value = int_id; 49913531Sjairo.balart@metempsy.com virtualUpdate(); 50013531Sjairo.balart@metempsy.com break; 50113531Sjairo.balart@metempsy.com } 50213531Sjairo.balart@metempsy.com 50313760Sjairo.balart@metempsy.com // System Register Enable Register EL1 50413531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 50513760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: { 50613531Sjairo.balart@metempsy.com /* 50713531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 50813531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 50913531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 51013531Sjairo.balart@metempsy.com */ 51113760Sjairo.balart@metempsy.com ICC_SRE_EL1 icc_sre_el1 = 0; 51213760Sjairo.balart@metempsy.com icc_sre_el1.SRE = 1; 51313760Sjairo.balart@metempsy.com icc_sre_el1.DIB = 1; 51413760Sjairo.balart@metempsy.com icc_sre_el1.DFB = 1; 51513760Sjairo.balart@metempsy.com value = icc_sre_el1; 51613760Sjairo.balart@metempsy.com break; 51713760Sjairo.balart@metempsy.com } 51813760Sjairo.balart@metempsy.com 51913760Sjairo.balart@metempsy.com // System Register Enable Register EL2 52013760Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 52113760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: { 52213531Sjairo.balart@metempsy.com /* 52313531Sjairo.balart@metempsy.com * Enable [3] == 1 52413760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) 52513531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 52613531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 52713531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 52813531Sjairo.balart@metempsy.com */ 52913760Sjairo.balart@metempsy.com ICC_SRE_EL2 icc_sre_el2 = 0; 53013760Sjairo.balart@metempsy.com icc_sre_el2.SRE = 1; 53113760Sjairo.balart@metempsy.com icc_sre_el2.DIB = 1; 53213760Sjairo.balart@metempsy.com icc_sre_el2.DFB = 1; 53313760Sjairo.balart@metempsy.com icc_sre_el2.Enable = 1; 53413760Sjairo.balart@metempsy.com value = icc_sre_el2; 53513531Sjairo.balart@metempsy.com break; 53613760Sjairo.balart@metempsy.com } 53713760Sjairo.balart@metempsy.com 53813760Sjairo.balart@metempsy.com // System Register Enable Register EL3 53913760Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 54013760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: { 54113760Sjairo.balart@metempsy.com /* 54213760Sjairo.balart@metempsy.com * Enable [3] == 1 54313760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 54413760Sjairo.balart@metempsy.com * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 54513760Sjairo.balart@metempsy.com * RAO/WI) 54613760Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 54713760Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 54813760Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 54913760Sjairo.balart@metempsy.com */ 55013760Sjairo.balart@metempsy.com ICC_SRE_EL3 icc_sre_el3 = 0; 55113760Sjairo.balart@metempsy.com icc_sre_el3.SRE = 1; 55213760Sjairo.balart@metempsy.com icc_sre_el3.DIB = 1; 55313760Sjairo.balart@metempsy.com icc_sre_el3.DFB = 1; 55413760Sjairo.balart@metempsy.com icc_sre_el3.Enable = 1; 55513760Sjairo.balart@metempsy.com value = icc_sre_el3; 55613760Sjairo.balart@metempsy.com break; 55713760Sjairo.balart@metempsy.com } 55813760Sjairo.balart@metempsy.com 55913760Sjairo.balart@metempsy.com // Control Register 56013531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 56113760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 56213760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 56313531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_CTLR_EL1); 56413531Sjairo.balart@metempsy.com } 56513531Sjairo.balart@metempsy.com 56614245Sgiacomo.travaglini@arm.com value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1); 56713760Sjairo.balart@metempsy.com // Enforce value for RO bits 56813760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 56913760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 57013760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 57113760Sjairo.balart@metempsy.com // generation System registers 57213760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 57313531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 57413531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 57513760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = value; 57613760Sjairo.balart@metempsy.com icc_ctlr_el1.ExtRange = 0; 57713760Sjairo.balart@metempsy.com icc_ctlr_el1.RSS = 1; 57813760Sjairo.balart@metempsy.com icc_ctlr_el1.A3V = 1; 57913760Sjairo.balart@metempsy.com icc_ctlr_el1.SEIS = 0; 58013760Sjairo.balart@metempsy.com icc_ctlr_el1.IDbits = 1; 58113760Sjairo.balart@metempsy.com icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 58213760Sjairo.balart@metempsy.com value = icc_ctlr_el1; 58313531Sjairo.balart@metempsy.com break; 58413531Sjairo.balart@metempsy.com } 58513531Sjairo.balart@metempsy.com 58613760Sjairo.balart@metempsy.com // Virtual Control Register 58713531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 58813760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = value; 58913760Sjairo.balart@metempsy.com icv_ctlr_el1.RSS = 0; 59013760Sjairo.balart@metempsy.com icv_ctlr_el1.A3V = 1; 59113760Sjairo.balart@metempsy.com icv_ctlr_el1.SEIS = 0; 59213760Sjairo.balart@metempsy.com icv_ctlr_el1.IDbits = 1; 59313760Sjairo.balart@metempsy.com icv_ctlr_el1.PRIbits = 7; 59413760Sjairo.balart@metempsy.com value = icv_ctlr_el1; 59513531Sjairo.balart@metempsy.com break; 59613531Sjairo.balart@metempsy.com } 59713531Sjairo.balart@metempsy.com 59813760Sjairo.balart@metempsy.com // Control Register 59913531Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 60013531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 60113760Sjairo.balart@metempsy.com // Enforce value for RO bits 60213760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 60313760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 60413760Sjairo.balart@metempsy.com // nDS [17], supports disabling of security 60513760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 60613760Sjairo.balart@metempsy.com // generation System registers 60713760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 60813531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 60913531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 61013760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = value; 61113760Sjairo.balart@metempsy.com icc_ctlr_el3.ExtRange = 0; 61213760Sjairo.balart@metempsy.com icc_ctlr_el3.RSS = 1; 61313760Sjairo.balart@metempsy.com icc_ctlr_el3.nDS = 0; 61413760Sjairo.balart@metempsy.com icc_ctlr_el3.A3V = 1; 61513760Sjairo.balart@metempsy.com icc_ctlr_el3.SEIS = 0; 61613760Sjairo.balart@metempsy.com icc_ctlr_el3.IDbits = 0; 61713760Sjairo.balart@metempsy.com icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 61813760Sjairo.balart@metempsy.com value = icc_ctlr_el3; 61913531Sjairo.balart@metempsy.com break; 62013531Sjairo.balart@metempsy.com } 62113531Sjairo.balart@metempsy.com 62213760Sjairo.balart@metempsy.com // Hyp Control Register 62313531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 62413531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: 62513531Sjairo.balart@metempsy.com break; 62613531Sjairo.balart@metempsy.com 62713760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 62813531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0: 62913531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2: 63013531Sjairo.balart@metempsy.com break; 63113531Sjairo.balart@metempsy.com 63214236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 63314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 63414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 63514236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 63614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 63714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 63814236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 63914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 64014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 64114236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 64214236Sgiacomo.travaglini@arm.com return 0; 64314236Sgiacomo.travaglini@arm.com 64413760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 64513531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0: 64613531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2: 64713531Sjairo.balart@metempsy.com break; 64813531Sjairo.balart@metempsy.com 64914236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 65014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 65114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 65214236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 65314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 65414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 65514236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 65614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 65714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 65814236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 65914236Sgiacomo.travaglini@arm.com return 0; 66014236Sgiacomo.travaglini@arm.com 66113760Sjairo.balart@metempsy.com // Maintenance Interrupt State Register 66213531Sjairo.balart@metempsy.com case MISCREG_ICH_MISR: 66313760Sjairo.balart@metempsy.com case MISCREG_ICH_MISR_EL2: 66413760Sjairo.balart@metempsy.com value = maintenanceInterruptStatus(); 66513760Sjairo.balart@metempsy.com break; 66613760Sjairo.balart@metempsy.com 66713760Sjairo.balart@metempsy.com // VGIC Type Register 66813760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR: 66913760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR_EL2: { 67013760Sjairo.balart@metempsy.com ICH_VTR_EL2 ich_vtr_el2 = value; 67113760Sjairo.balart@metempsy.com 67213760Sjairo.balart@metempsy.com ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 67313760Sjairo.balart@metempsy.com ich_vtr_el2.A3V = 1; 67413760Sjairo.balart@metempsy.com ich_vtr_el2.IDbits = 1; 67513760Sjairo.balart@metempsy.com ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 67613760Sjairo.balart@metempsy.com ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; 67713760Sjairo.balart@metempsy.com 67813760Sjairo.balart@metempsy.com value = ich_vtr_el2; 67913760Sjairo.balart@metempsy.com break; 68013531Sjairo.balart@metempsy.com } 68113531Sjairo.balart@metempsy.com 68213760Sjairo.balart@metempsy.com // End of Interrupt Status Register 68313531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR: 68413531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR_EL2: 68513760Sjairo.balart@metempsy.com value = eoiMaintenanceInterruptStatus(); 68613531Sjairo.balart@metempsy.com break; 68713531Sjairo.balart@metempsy.com 68813760Sjairo.balart@metempsy.com // Empty List Register Status Register 68913531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR: 69013531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR_EL2: 69113531Sjairo.balart@metempsy.com value = 0; 69213531Sjairo.balart@metempsy.com 69313531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 69413760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 69513531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 69613531Sjairo.balart@metempsy.com 69713760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 69813760Sjairo.balart@metempsy.com (ich_lr_el2.HW || !ich_lr_el2.EOI)) { 69913531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 70013531Sjairo.balart@metempsy.com } 70113531Sjairo.balart@metempsy.com } 70213531Sjairo.balart@metempsy.com 70313531Sjairo.balart@metempsy.com break; 70413531Sjairo.balart@metempsy.com 70513760Sjairo.balart@metempsy.com // List Registers 70613531Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 70713531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 70813531Sjairo.balart@metempsy.com value = value >> 32; 70913531Sjairo.balart@metempsy.com break; 71013531Sjairo.balart@metempsy.com 71113760Sjairo.balart@metempsy.com // List Registers 71213531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 71313531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 71413531Sjairo.balart@metempsy.com value = value & 0xffffffff; 71513531Sjairo.balart@metempsy.com break; 71613531Sjairo.balart@metempsy.com 71713760Sjairo.balart@metempsy.com // List Registers 71813531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 71913531Sjairo.balart@metempsy.com break; 72013531Sjairo.balart@metempsy.com 72113760Sjairo.balart@metempsy.com // Virtual Machine Control Register 72213531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 72313531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: 72413531Sjairo.balart@metempsy.com break; 72513531Sjairo.balart@metempsy.com 72613531Sjairo.balart@metempsy.com default: 72713760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 72813760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 72913531Sjairo.balart@metempsy.com } 73013531Sjairo.balart@metempsy.com 73113760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 73213760Sjairo.balart@metempsy.com miscRegName[misc_reg], value); 73313531Sjairo.balart@metempsy.com return value; 73413531Sjairo.balart@metempsy.com} 73513531Sjairo.balart@metempsy.com 73613531Sjairo.balart@metempsy.comvoid 73713580Sgabeblack@google.comGicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 73813531Sjairo.balart@metempsy.com{ 73913531Sjairo.balart@metempsy.com bool do_virtual_update = false; 74013760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 74113760Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 74213531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 74313531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 74413531Sjairo.balart@metempsy.com 74513531Sjairo.balart@metempsy.com switch (misc_reg) { 74613760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 74713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 74813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: 74913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 75013531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 75113531Sjairo.balart@metempsy.com } 75213531Sjairo.balart@metempsy.com 75314246Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val); 75414246Sgiacomo.travaglini@arm.com return; 75513531Sjairo.balart@metempsy.com 75613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 75713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 75813531Sjairo.balart@metempsy.com 75913531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 76013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 76113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 76213531Sjairo.balart@metempsy.com 76313531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 76413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 76513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 76613531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 76713531Sjairo.balart@metempsy.com break; 76813531Sjairo.balart@metempsy.com 76913760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 77013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 77113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: 77213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 77313531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 77413531Sjairo.balart@metempsy.com } 77513531Sjairo.balart@metempsy.com 77613531Sjairo.balart@metempsy.com break; 77713531Sjairo.balart@metempsy.com 77813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 77913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 78013531Sjairo.balart@metempsy.com 78113531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 78213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 78313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 78413531Sjairo.balart@metempsy.com 78513531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 78613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 78713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 78813531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 78913531Sjairo.balart@metempsy.com break; 79013531Sjairo.balart@metempsy.com 79113760Sjairo.balart@metempsy.com // End Of Interrupt Register 0 79213531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0: 79313531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 79413531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 79513531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 79613531Sjairo.balart@metempsy.com } 79713531Sjairo.balart@metempsy.com 79813531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 79913531Sjairo.balart@metempsy.com 80013531Sjairo.balart@metempsy.com // avoid activation for special interrupts 80113923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 80213923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 80313531Sjairo.balart@metempsy.com return; 80413531Sjairo.balart@metempsy.com } 80513531Sjairo.balart@metempsy.com 80613531Sjairo.balart@metempsy.com Gicv3::GroupId group = Gicv3::G0S; 80713531Sjairo.balart@metempsy.com 80813531Sjairo.balart@metempsy.com if (highestActiveGroup() != group) { 80913531Sjairo.balart@metempsy.com return; 81013531Sjairo.balart@metempsy.com } 81113531Sjairo.balart@metempsy.com 81213531Sjairo.balart@metempsy.com dropPriority(group); 81313531Sjairo.balart@metempsy.com 81413531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 81513531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 81613531Sjairo.balart@metempsy.com } 81713531Sjairo.balart@metempsy.com 81813531Sjairo.balart@metempsy.com break; 81913531Sjairo.balart@metempsy.com } 82013531Sjairo.balart@metempsy.com 82113760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 0 82213531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR0_EL1: { 82313531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 82413531Sjairo.balart@metempsy.com 82513531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 82613531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 82713531Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 82813531Sjairo.balart@metempsy.com return; 82913531Sjairo.balart@metempsy.com } 83013531Sjairo.balart@metempsy.com 83113531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 83213531Sjairo.balart@metempsy.com 83313531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 83413531Sjairo.balart@metempsy.com return; 83513531Sjairo.balart@metempsy.com } 83613531Sjairo.balart@metempsy.com 83713531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 83813531Sjairo.balart@metempsy.com 83913531Sjairo.balart@metempsy.com if (lr_idx < 0) { 84013531Sjairo.balart@metempsy.com // No LR found matching 84113531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 84213531Sjairo.balart@metempsy.com } else { 84313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 84413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 84513531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 84613760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 84713760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 84813531Sjairo.balart@metempsy.com 84913531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) { 85013760Sjairo.balart@metempsy.com //if (!virtualIsEOISplitMode()) 85113531Sjairo.balart@metempsy.com { 85213531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 85313531Sjairo.balart@metempsy.com } 85413531Sjairo.balart@metempsy.com } 85513531Sjairo.balart@metempsy.com } 85613531Sjairo.balart@metempsy.com 85713531Sjairo.balart@metempsy.com virtualUpdate(); 85813531Sjairo.balart@metempsy.com break; 85913531Sjairo.balart@metempsy.com } 86013531Sjairo.balart@metempsy.com 86113760Sjairo.balart@metempsy.com // End Of Interrupt Register 1 86213531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1: 86313760Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1_EL1: { 86413531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 86513531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 86613531Sjairo.balart@metempsy.com } 86713531Sjairo.balart@metempsy.com 86813531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 86913531Sjairo.balart@metempsy.com 87013531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 87113923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 87213923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 87313531Sjairo.balart@metempsy.com return; 87413531Sjairo.balart@metempsy.com } 87513531Sjairo.balart@metempsy.com 87613760Sjairo.balart@metempsy.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 87713531Sjairo.balart@metempsy.com 87813531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G0S) { 87913531Sjairo.balart@metempsy.com return; 88013531Sjairo.balart@metempsy.com } 88113531Sjairo.balart@metempsy.com 88213531Sjairo.balart@metempsy.com if (distributor->DS == 0) { 88313531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 88413531Sjairo.balart@metempsy.com return; 88513531Sjairo.balart@metempsy.com } else if (highestActiveGroup() == Gicv3::G1NS && 88613760Sjairo.balart@metempsy.com !(!inSecureState() or (currEL() == EL3))) { 88713531Sjairo.balart@metempsy.com return; 88813531Sjairo.balart@metempsy.com } 88913531Sjairo.balart@metempsy.com } 89013531Sjairo.balart@metempsy.com 89113531Sjairo.balart@metempsy.com dropPriority(group); 89213531Sjairo.balart@metempsy.com 89313531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 89413531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 89513531Sjairo.balart@metempsy.com } 89613531Sjairo.balart@metempsy.com 89713531Sjairo.balart@metempsy.com break; 89813531Sjairo.balart@metempsy.com } 89913531Sjairo.balart@metempsy.com 90013760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 1 90113531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR1_EL1: { 90213531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 90313531Sjairo.balart@metempsy.com 90413531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 90513531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 90613760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 90713531Sjairo.balart@metempsy.com return; 90813531Sjairo.balart@metempsy.com } 90913531Sjairo.balart@metempsy.com 91013531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 91113531Sjairo.balart@metempsy.com 91213531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 91313531Sjairo.balart@metempsy.com return; 91413531Sjairo.balart@metempsy.com } 91513531Sjairo.balart@metempsy.com 91613531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 91713531Sjairo.balart@metempsy.com 91813531Sjairo.balart@metempsy.com if (lr_idx < 0) { 91913760Sjairo.balart@metempsy.com // No matching LR found 92013531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 92113531Sjairo.balart@metempsy.com } else { 92213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 92313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 92413531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 92513760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 92613760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 92713531Sjairo.balart@metempsy.com 92813531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 92913531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 93013531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 93113531Sjairo.balart@metempsy.com } 93213531Sjairo.balart@metempsy.com } 93313531Sjairo.balart@metempsy.com } 93413531Sjairo.balart@metempsy.com 93513531Sjairo.balart@metempsy.com virtualUpdate(); 93613531Sjairo.balart@metempsy.com break; 93713531Sjairo.balart@metempsy.com } 93813531Sjairo.balart@metempsy.com 93913760Sjairo.balart@metempsy.com // Deactivate Interrupt Register 94013531Sjairo.balart@metempsy.com case MISCREG_ICC_DIR: 94113760Sjairo.balart@metempsy.com case MISCREG_ICC_DIR_EL1: { 94213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 94313760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 94413531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_DIR_EL1, val); 94513531Sjairo.balart@metempsy.com } 94613531Sjairo.balart@metempsy.com 94713531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 94813531Sjairo.balart@metempsy.com 94913760Sjairo.balart@metempsy.com // The following checks are as per spec pseudocode 95013760Sjairo.balart@metempsy.com // aarch64/support/ICC_DIR_EL1 95113760Sjairo.balart@metempsy.com 95213760Sjairo.balart@metempsy.com // Check for spurious ID 95313531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE) { 95413531Sjairo.balart@metempsy.com return; 95513531Sjairo.balart@metempsy.com } 95613531Sjairo.balart@metempsy.com 95713760Sjairo.balart@metempsy.com // EOI mode is not set, so don't deactivate 95813531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 95913531Sjairo.balart@metempsy.com return; 96013531Sjairo.balart@metempsy.com } 96113531Sjairo.balart@metempsy.com 96213531Sjairo.balart@metempsy.com Gicv3::GroupId group = 96313531Sjairo.balart@metempsy.com int_id >= 32 ? distributor->getIntGroup(int_id) : 96413531Sjairo.balart@metempsy.com redistributor->getIntGroup(int_id); 96513531Sjairo.balart@metempsy.com bool irq_is_grp0 = group == Gicv3::G0S; 96613531Sjairo.balart@metempsy.com bool single_sec_state = distributor->DS; 96713531Sjairo.balart@metempsy.com bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 96813531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 96913531Sjairo.balart@metempsy.com bool route_fiq_to_el3 = scr_el3.fiq; 97013531Sjairo.balart@metempsy.com bool route_irq_to_el3 = scr_el3.irq; 97113531Sjairo.balart@metempsy.com bool route_fiq_to_el2 = hcr_fmo; 97213531Sjairo.balart@metempsy.com bool route_irq_to_el2 = hcr_imo; 97313531Sjairo.balart@metempsy.com 97413531Sjairo.balart@metempsy.com switch (currEL()) { 97513531Sjairo.balart@metempsy.com case EL3: 97613531Sjairo.balart@metempsy.com break; 97713531Sjairo.balart@metempsy.com 97813531Sjairo.balart@metempsy.com case EL2: 97913531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 98013531Sjairo.balart@metempsy.com break; 98113531Sjairo.balart@metempsy.com } 98213531Sjairo.balart@metempsy.com 98313531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 98413531Sjairo.balart@metempsy.com break; 98513531Sjairo.balart@metempsy.com } 98613531Sjairo.balart@metempsy.com 98713531Sjairo.balart@metempsy.com return; 98813531Sjairo.balart@metempsy.com 98913531Sjairo.balart@metempsy.com case EL1: 99013531Sjairo.balart@metempsy.com if (!isSecureBelowEL3()) { 99113531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && 99213760Sjairo.balart@metempsy.com !route_fiq_to_el3 && !route_fiq_to_el2) { 99313531Sjairo.balart@metempsy.com break; 99413531Sjairo.balart@metempsy.com } 99513531Sjairo.balart@metempsy.com 99613531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && 99713760Sjairo.balart@metempsy.com !route_irq_to_el3 && !route_irq_to_el2) { 99813531Sjairo.balart@metempsy.com break; 99913531Sjairo.balart@metempsy.com } 100013531Sjairo.balart@metempsy.com } else { 100113531Sjairo.balart@metempsy.com if (irq_is_grp0 && !route_fiq_to_el3) { 100213531Sjairo.balart@metempsy.com break; 100313531Sjairo.balart@metempsy.com } 100413531Sjairo.balart@metempsy.com 100513531Sjairo.balart@metempsy.com if (!irq_is_grp0 && 100613760Sjairo.balart@metempsy.com (!irq_is_secure || !single_sec_state) && 100713760Sjairo.balart@metempsy.com !route_irq_to_el3) { 100813531Sjairo.balart@metempsy.com break; 100913531Sjairo.balart@metempsy.com } 101013531Sjairo.balart@metempsy.com } 101113531Sjairo.balart@metempsy.com 101213531Sjairo.balart@metempsy.com return; 101313531Sjairo.balart@metempsy.com 101413531Sjairo.balart@metempsy.com default: 101513531Sjairo.balart@metempsy.com break; 101613531Sjairo.balart@metempsy.com } 101713531Sjairo.balart@metempsy.com 101813531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 101913531Sjairo.balart@metempsy.com break; 102013531Sjairo.balart@metempsy.com } 102113531Sjairo.balart@metempsy.com 102213760Sjairo.balart@metempsy.com // Deactivate Virtual Interrupt Register 102313531Sjairo.balart@metempsy.com case MISCREG_ICV_DIR_EL1: { 102413531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 102513531Sjairo.balart@metempsy.com 102613531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 102713531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 102813760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 102913531Sjairo.balart@metempsy.com return; 103013531Sjairo.balart@metempsy.com } 103113531Sjairo.balart@metempsy.com 103213531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 103313531Sjairo.balart@metempsy.com return; 103413531Sjairo.balart@metempsy.com } 103513531Sjairo.balart@metempsy.com 103613531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 103713531Sjairo.balart@metempsy.com 103813531Sjairo.balart@metempsy.com if (lr_idx < 0) { 103913760Sjairo.balart@metempsy.com // No matching LR found 104013531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 104113531Sjairo.balart@metempsy.com } else { 104213531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 104313531Sjairo.balart@metempsy.com } 104413531Sjairo.balart@metempsy.com 104513531Sjairo.balart@metempsy.com virtualUpdate(); 104613531Sjairo.balart@metempsy.com break; 104713531Sjairo.balart@metempsy.com } 104813531Sjairo.balart@metempsy.com 104913760Sjairo.balart@metempsy.com // Binary Point Register 0 105013531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 105114237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 105214237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 105314237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 105414237Sgiacomo.travaglini@arm.com } 105514237Sgiacomo.travaglini@arm.com break; 105614237Sgiacomo.travaglini@arm.com } 105713760Sjairo.balart@metempsy.com // Binary Point Register 1 105813531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 105913760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 106014237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 106114237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 106214237Sgiacomo.travaglini@arm.com } 106314237Sgiacomo.travaglini@arm.com 106414237Sgiacomo.travaglini@arm.com val &= 0x7; 106514237Sgiacomo.travaglini@arm.com 106614237Sgiacomo.travaglini@arm.com if (isSecureBelowEL3()) { 106714237Sgiacomo.travaglini@arm.com // group == Gicv3::G1S 106814237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 106914237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 107014237Sgiacomo.travaglini@arm.com 107114237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR; 107214237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 107314237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val); 107414237Sgiacomo.travaglini@arm.com } else { 107514237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val); 107614237Sgiacomo.travaglini@arm.com } 107714237Sgiacomo.travaglini@arm.com return; 107814237Sgiacomo.travaglini@arm.com } else { 107914237Sgiacomo.travaglini@arm.com // group == Gicv3::G1NS 108014237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 108114237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 108214237Sgiacomo.travaglini@arm.com 108314237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS; 108414237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 108514237Sgiacomo.travaglini@arm.com // Non secure writes from EL1 and EL2 are ignored 108614237Sgiacomo.travaglini@arm.com } else { 108714237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val); 108814237Sgiacomo.travaglini@arm.com } 108914237Sgiacomo.travaglini@arm.com return; 109014237Sgiacomo.travaglini@arm.com } 109114237Sgiacomo.travaglini@arm.com 109214237Sgiacomo.travaglini@arm.com break; 109313531Sjairo.balart@metempsy.com } 109413531Sjairo.balart@metempsy.com 109513760Sjairo.balart@metempsy.com // Virtual Binary Point Register 0 109613531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 109713760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 109813531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 109913531Sjairo.balart@metempsy.com Gicv3::GroupId group = 110013531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 110113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 110213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 110313531Sjairo.balart@metempsy.com 110413760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 110513760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 110613531Sjairo.balart@metempsy.com return; 110713531Sjairo.balart@metempsy.com } 110813531Sjairo.balart@metempsy.com 110913531Sjairo.balart@metempsy.com uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 111013531Sjairo.balart@metempsy.com 111113531Sjairo.balart@metempsy.com if (group != Gicv3::G0S) { 111213531Sjairo.balart@metempsy.com min_VPBR++; 111313531Sjairo.balart@metempsy.com } 111413531Sjairo.balart@metempsy.com 111513531Sjairo.balart@metempsy.com if (val < min_VPBR) { 111613531Sjairo.balart@metempsy.com val = min_VPBR; 111713531Sjairo.balart@metempsy.com } 111813531Sjairo.balart@metempsy.com 111913531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 112013760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = val; 112113531Sjairo.balart@metempsy.com } else { 112213760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = val; 112313531Sjairo.balart@metempsy.com } 112413531Sjairo.balart@metempsy.com 112513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 112613531Sjairo.balart@metempsy.com do_virtual_update = true; 112713531Sjairo.balart@metempsy.com break; 112813531Sjairo.balart@metempsy.com } 112913531Sjairo.balart@metempsy.com 113013760Sjairo.balart@metempsy.com // Control Register EL1 113113531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 113213760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 113313760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 113413531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 113513531Sjairo.balart@metempsy.com } 113613531Sjairo.balart@metempsy.com 113713531Sjairo.balart@metempsy.com /* 113813760Sjairo.balart@metempsy.com * ExtRange is RO. 113913531Sjairo.balart@metempsy.com * RSS is RO. 114013531Sjairo.balart@metempsy.com * A3V is RO. 114113531Sjairo.balart@metempsy.com * SEIS is RO. 114213531Sjairo.balart@metempsy.com * IDbits is RO. 114313531Sjairo.balart@metempsy.com * PRIbits is RO. 114413531Sjairo.balart@metempsy.com */ 114513760Sjairo.balart@metempsy.com ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 114613760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 114714245Sgiacomo.travaglini@arm.com readBankedMiscReg(MISCREG_ICC_CTLR_EL1); 114813760Sjairo.balart@metempsy.com 114913760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 115013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 115113760Sjairo.balart@metempsy.com 115213760Sjairo.balart@metempsy.com // The following could be refactored but it is following 115313760Sjairo.balart@metempsy.com // spec description section 9.2.6 point by point. 115413760Sjairo.balart@metempsy.com 115513760Sjairo.balart@metempsy.com // PMHE 115613760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 115713760Sjairo.balart@metempsy.com // PMHE is alias of ICC_CTLR_EL3.PMHE 115813760Sjairo.balart@metempsy.com 115913760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 116013760Sjairo.balart@metempsy.com // PMHE is RO 116113760Sjairo.balart@metempsy.com } else if (distributor->DS == 1) { 116213760Sjairo.balart@metempsy.com // PMHE is RW 116313760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 116413760Sjairo.balart@metempsy.com icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 116513760Sjairo.balart@metempsy.com } 116613531Sjairo.balart@metempsy.com } else { 116713760Sjairo.balart@metempsy.com // PMHE is RW (by implementation choice) 116813760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 116913531Sjairo.balart@metempsy.com } 117013531Sjairo.balart@metempsy.com 117113760Sjairo.balart@metempsy.com // EOImode 117213760Sjairo.balart@metempsy.com icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 117313760Sjairo.balart@metempsy.com 117413760Sjairo.balart@metempsy.com if (inSecureState()) { 117513760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 117613760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 117713760Sjairo.balart@metempsy.com } else { 117813760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 117913760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 118013760Sjairo.balart@metempsy.com } 118113760Sjairo.balart@metempsy.com 118213760Sjairo.balart@metempsy.com // CBPR 118313760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 118413760Sjairo.balart@metempsy.com // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 118513760Sjairo.balart@metempsy.com 118613760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 118713760Sjairo.balart@metempsy.com // CBPR is RO 118813760Sjairo.balart@metempsy.com } else { 118913760Sjairo.balart@metempsy.com // CBPR is RW 119013760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 119113760Sjairo.balart@metempsy.com 119213760Sjairo.balart@metempsy.com if (inSecureState()) { 119313760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 119413760Sjairo.balart@metempsy.com } else { 119513760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 119613760Sjairo.balart@metempsy.com } 119713760Sjairo.balart@metempsy.com } 119813760Sjairo.balart@metempsy.com } else { 119913760Sjairo.balart@metempsy.com // CBPR is RW 120013760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 120113760Sjairo.balart@metempsy.com } 120213760Sjairo.balart@metempsy.com 120313760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 120413760Sjairo.balart@metempsy.com 120514245Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1); 120614245Sgiacomo.travaglini@arm.com return; 120713531Sjairo.balart@metempsy.com } 120813531Sjairo.balart@metempsy.com 120913760Sjairo.balart@metempsy.com // Virtual Control Register 121013531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 121113760Sjairo.balart@metempsy.com ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 121213760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = 121313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 121413760Sjairo.balart@metempsy.com icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 121513760Sjairo.balart@metempsy.com icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 121613760Sjairo.balart@metempsy.com val = icv_ctlr_el1; 121713760Sjairo.balart@metempsy.com 121813760Sjairo.balart@metempsy.com // Aliases 121913760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 122013760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 122113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 122213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 122313760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 122413760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 122513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 122613760Sjairo.balart@metempsy.com break; 122713760Sjairo.balart@metempsy.com } 122813760Sjairo.balart@metempsy.com 122913760Sjairo.balart@metempsy.com // Control Register EL3 123013760Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 123113760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 123213760Sjairo.balart@metempsy.com /* 123313760Sjairo.balart@metempsy.com * ExtRange is RO. 123413760Sjairo.balart@metempsy.com * RSS is RO. 123513760Sjairo.balart@metempsy.com * nDS is RO. 123613760Sjairo.balart@metempsy.com * A3V is RO. 123713760Sjairo.balart@metempsy.com * SEIS is RO. 123813760Sjairo.balart@metempsy.com * IDbits is RO. 123913760Sjairo.balart@metempsy.com * PRIbits is RO. 124013760Sjairo.balart@metempsy.com * PMHE is RAO/WI, priority-based routing is always used. 124113760Sjairo.balart@metempsy.com */ 124213760Sjairo.balart@metempsy.com ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; 124313760Sjairo.balart@metempsy.com 124413760Sjairo.balart@metempsy.com // Aliases 124513760Sjairo.balart@metempsy.com if (haveEL(EL3)) 124613760Sjairo.balart@metempsy.com { 124713760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 124813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 124913760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 125013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 125113760Sjairo.balart@metempsy.com 125213760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).EOImode is an alias of 125313760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1NS 125413760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 125513760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).EOImode is an alias of 125613760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1S 125713760Sjairo.balart@metempsy.com icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 125813760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 125913760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 126013760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 126113760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; 126213760Sjairo.balart@metempsy.com 126313760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 126413760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 126513760Sjairo.balart@metempsy.com icc_ctlr_el1_ns); 126613760Sjairo.balart@metempsy.com } 126713760Sjairo.balart@metempsy.com 126813760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 126913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 127013760Sjairo.balart@metempsy.com 127113760Sjairo.balart@metempsy.com icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 127213760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 127313760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 127413760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 127513760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 127613760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 127713760Sjairo.balart@metempsy.com 127813760Sjairo.balart@metempsy.com val = icc_ctlr_el3; 127913531Sjairo.balart@metempsy.com break; 128013531Sjairo.balart@metempsy.com } 128113531Sjairo.balart@metempsy.com 128213760Sjairo.balart@metempsy.com // Priority Mask Register 128313531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 128413760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: { 128513760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 128614057Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_PMR_EL1, val); 128713531Sjairo.balart@metempsy.com } 128813531Sjairo.balart@metempsy.com 128913531Sjairo.balart@metempsy.com val &= 0xff; 129013531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 129113531Sjairo.balart@metempsy.com 129213531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) { 129313760Sjairo.balart@metempsy.com // Spec section 4.8.1 129413760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: 129513580Sgabeblack@google.com RegVal old_icc_pmr_el1 = 129613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 129713531Sjairo.balart@metempsy.com 129813531Sjairo.balart@metempsy.com if (!(old_icc_pmr_el1 & 0x80)) { 129913760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 130013760Sjairo.balart@metempsy.com // 0x00-0x7F then WI 130113531Sjairo.balart@metempsy.com return; 130213531Sjairo.balart@metempsy.com } 130313531Sjairo.balart@metempsy.com 130413760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 130513760Sjairo.balart@metempsy.com // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 130613760Sjairo.balart@metempsy.com // based on the Non-secure read of the priority mask value 130713760Sjairo.balart@metempsy.com // written to the register. 130813760Sjairo.balart@metempsy.com 130913531Sjairo.balart@metempsy.com val = (val >> 1) | 0x80; 131013531Sjairo.balart@metempsy.com } 131113531Sjairo.balart@metempsy.com 131213531Sjairo.balart@metempsy.com val &= ~0U << (8 - PRIORITY_BITS); 131313531Sjairo.balart@metempsy.com break; 131413531Sjairo.balart@metempsy.com } 131513531Sjairo.balart@metempsy.com 131614057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 131714057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 131814057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 131914057Sgiacomo.travaglini@arm.com ich_vmcr_el2.VPMR = val & 0xff; 132014057Sgiacomo.travaglini@arm.com 132114057Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 132214057Sgiacomo.travaglini@arm.com virtualUpdate(); 132314057Sgiacomo.travaglini@arm.com return; 132414057Sgiacomo.travaglini@arm.com } 132514057Sgiacomo.travaglini@arm.com 132613760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable Register EL1 132713760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 132813760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 132913760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 133013760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 133113760Sjairo.balart@metempsy.com } 133213760Sjairo.balart@metempsy.com 133314248Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val); 133414248Sgiacomo.travaglini@arm.com updateDistributor(); 133514248Sgiacomo.travaglini@arm.com return; 133613760Sjairo.balart@metempsy.com } 133713760Sjairo.balart@metempsy.com 133813760Sjairo.balart@metempsy.com // Virtual Interrupt Group 0 Enable register 133913760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN0_EL1: { 134013760Sjairo.balart@metempsy.com bool enable = val & 0x1; 134113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 134213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 134313760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = enable; 134413740Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 134513740Sgiacomo.travaglini@arm.com virtualUpdate(); 134613740Sgiacomo.travaglini@arm.com return; 134713740Sgiacomo.travaglini@arm.com } 134813740Sgiacomo.travaglini@arm.com 134913760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 135013760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 135113760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 135213760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 135313760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 135413760Sjairo.balart@metempsy.com } 135513760Sjairo.balart@metempsy.com 135614247Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val); 135714248Sgiacomo.travaglini@arm.com updateDistributor(); 135814247Sgiacomo.travaglini@arm.com return; 135913531Sjairo.balart@metempsy.com } 136013531Sjairo.balart@metempsy.com 136113760Sjairo.balart@metempsy.com // Virtual Interrupt Group 1 Enable register 136213760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN1_EL1: { 136313531Sjairo.balart@metempsy.com bool enable = val & 0x1; 136413760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 136513531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 136613760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = enable; 136713531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 136813531Sjairo.balart@metempsy.com virtualUpdate(); 136913531Sjairo.balart@metempsy.com return; 137013531Sjairo.balart@metempsy.com } 137113531Sjairo.balart@metempsy.com 137213760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register 137313760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 137413760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: { 137513760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 137614254Sgiacomo.travaglini@arm.com 137714254Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect( 137814254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S); 137914254Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect( 138014254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS); 138114254Sgiacomo.travaglini@arm.com return; 138213531Sjairo.balart@metempsy.com } 138313531Sjairo.balart@metempsy.com 138413760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 0 Register 138513531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R: 138613531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R_EL1: 138714227Sgiacomo.travaglini@arm.com generateSGI(val, Gicv3::G0S); 138814227Sgiacomo.travaglini@arm.com break; 138913531Sjairo.balart@metempsy.com 139013760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 1 Register 139113531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI1R: 139214227Sgiacomo.travaglini@arm.com case MISCREG_ICC_SGI1R_EL1: { 139314227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 139414227Sgiacomo.travaglini@arm.com 139514227Sgiacomo.travaglini@arm.com generateSGI(val, group); 139614227Sgiacomo.travaglini@arm.com break; 139714227Sgiacomo.travaglini@arm.com } 139813531Sjairo.balart@metempsy.com 139913760Sjairo.balart@metempsy.com // Alias Software Generated Interrupt Group 1 Register 140013531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R: 140113531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R_EL1: { 140214227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S; 140314227Sgiacomo.travaglini@arm.com 140414227Sgiacomo.travaglini@arm.com generateSGI(val, group); 140514227Sgiacomo.travaglini@arm.com break; 140613531Sjairo.balart@metempsy.com } 140713531Sjairo.balart@metempsy.com 140813760Sjairo.balart@metempsy.com // System Register Enable Register EL1 140913531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 141013760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: 141113760Sjairo.balart@metempsy.com // System Register Enable Register EL2 141213531Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 141313760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: 141413760Sjairo.balart@metempsy.com // System Register Enable Register EL3 141513531Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 141613760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: 141713760Sjairo.balart@metempsy.com // All bits are RAO/WI 141813760Sjairo.balart@metempsy.com return; 141913760Sjairo.balart@metempsy.com 142013760Sjairo.balart@metempsy.com // Hyp Control Register 142113760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 142213760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: { 142313760Sjairo.balart@metempsy.com ICH_HCR_EL2 requested_ich_hcr_el2 = val; 142413760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 142513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 142613760Sjairo.balart@metempsy.com 142713760Sjairo.balart@metempsy.com if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 142813760Sjairo.balart@metempsy.com { 142913760Sjairo.balart@metempsy.com // EOIcount - Permitted behaviors are: 143013760Sjairo.balart@metempsy.com // - Increment EOIcount. 143113760Sjairo.balart@metempsy.com // - Leave EOIcount unchanged. 143213760Sjairo.balart@metempsy.com ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 143313531Sjairo.balart@metempsy.com } 143413531Sjairo.balart@metempsy.com 143513760Sjairo.balart@metempsy.com ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 143613760Sjairo.balart@metempsy.com ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 143713760Sjairo.balart@metempsy.com ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 143813760Sjairo.balart@metempsy.com ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 143913760Sjairo.balart@metempsy.com ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 144013760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 144113760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 144213760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 144313760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 144413760Sjairo.balart@metempsy.com ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 144513760Sjairo.balart@metempsy.com ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 144613760Sjairo.balart@metempsy.com ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 144713760Sjairo.balart@metempsy.com ich_hcr_el2.En = requested_ich_hcr_el2.En; 144813760Sjairo.balart@metempsy.com val = ich_hcr_el2; 144913531Sjairo.balart@metempsy.com do_virtual_update = true; 145013531Sjairo.balart@metempsy.com break; 145113760Sjairo.balart@metempsy.com } 145213760Sjairo.balart@metempsy.com 145313760Sjairo.balart@metempsy.com // List Registers 145413760Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { 145513531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 145613760Sjairo.balart@metempsy.com ICH_LRC requested_ich_lrc = val; 145713760Sjairo.balart@metempsy.com ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 145813760Sjairo.balart@metempsy.com 145913760Sjairo.balart@metempsy.com ich_lrc.State = requested_ich_lrc.State; 146013760Sjairo.balart@metempsy.com ich_lrc.HW = requested_ich_lrc.HW; 146113760Sjairo.balart@metempsy.com ich_lrc.Group = requested_ich_lrc.Group; 146213760Sjairo.balart@metempsy.com 146313760Sjairo.balart@metempsy.com // Priority, bits [23:16] 146413760Sjairo.balart@metempsy.com // At least five bits must be implemented. 146513760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 146613760Sjairo.balart@metempsy.com // We implement 5 bits. 146713760Sjairo.balart@metempsy.com ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 146813760Sjairo.balart@metempsy.com (ich_lrc.Priority & 0x07); 146913760Sjairo.balart@metempsy.com 147013760Sjairo.balart@metempsy.com // pINTID, bits [12:0] 147113760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 0 this field has the following meaning: 147213760Sjairo.balart@metempsy.com // - Bits[12:10] : RES0. 147313760Sjairo.balart@metempsy.com // - Bit[9] : EOI. 147413760Sjairo.balart@metempsy.com // - Bits[8:0] : RES0. 147513760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 1: 147613760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 147713760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 147813760Sjairo.balart@metempsy.com // order bits are RES0. 147913760Sjairo.balart@metempsy.com if (requested_ich_lrc.HW == 0) { 148013760Sjairo.balart@metempsy.com ich_lrc.EOI = requested_ich_lrc.EOI; 148113760Sjairo.balart@metempsy.com } else { 148213760Sjairo.balart@metempsy.com ich_lrc.pINTID = requested_ich_lrc.pINTID; 148313531Sjairo.balart@metempsy.com } 148413531Sjairo.balart@metempsy.com 148513760Sjairo.balart@metempsy.com val = ich_lrc; 148613760Sjairo.balart@metempsy.com do_virtual_update = true; 148713760Sjairo.balart@metempsy.com break; 148813760Sjairo.balart@metempsy.com } 148913760Sjairo.balart@metempsy.com 149013760Sjairo.balart@metempsy.com // List Registers 149113531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 149213531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 149313580Sgabeblack@google.com RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 149413531Sjairo.balart@metempsy.com val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 149513531Sjairo.balart@metempsy.com do_virtual_update = true; 149613531Sjairo.balart@metempsy.com break; 149713531Sjairo.balart@metempsy.com } 149813531Sjairo.balart@metempsy.com 149913760Sjairo.balart@metempsy.com // List Registers 150013531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64 150113760Sjairo.balart@metempsy.com ICH_LR_EL2 requested_ich_lr_el2 = val; 150213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 150313760Sjairo.balart@metempsy.com 150413760Sjairo.balart@metempsy.com ich_lr_el2.State = requested_ich_lr_el2.State; 150513760Sjairo.balart@metempsy.com ich_lr_el2.HW = requested_ich_lr_el2.HW; 150613760Sjairo.balart@metempsy.com ich_lr_el2.Group = requested_ich_lr_el2.Group; 150713760Sjairo.balart@metempsy.com 150813760Sjairo.balart@metempsy.com // Priority, bits [55:48] 150913760Sjairo.balart@metempsy.com // At least five bits must be implemented. 151013760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 151113760Sjairo.balart@metempsy.com // We implement 5 bits. 151213760Sjairo.balart@metempsy.com ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 151313760Sjairo.balart@metempsy.com (ich_lr_el2.Priority & 0x07); 151413760Sjairo.balart@metempsy.com 151513760Sjairo.balart@metempsy.com // pINTID, bits [44:32] 151613760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 151713760Sjairo.balart@metempsy.com // - Bits[44:42] : RES0. 151813760Sjairo.balart@metempsy.com // - Bit[41] : EOI. 151913760Sjairo.balart@metempsy.com // - Bits[40:32] : RES0. 152013760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 1: 152113760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 152213760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 152313760Sjairo.balart@metempsy.com // order bits are RES0. 152413760Sjairo.balart@metempsy.com if (requested_ich_lr_el2.HW == 0) { 152513760Sjairo.balart@metempsy.com ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 152613760Sjairo.balart@metempsy.com } else { 152713760Sjairo.balart@metempsy.com ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 152813760Sjairo.balart@metempsy.com } 152913760Sjairo.balart@metempsy.com 153013760Sjairo.balart@metempsy.com // vINTID, bits [31:0] 153113760Sjairo.balart@metempsy.com // It is IMPLEMENTATION DEFINED how many bits are implemented, 153213760Sjairo.balart@metempsy.com // though at least 16 bits must be implemented. 153313760Sjairo.balart@metempsy.com // Unimplemented bits are RES0. 153413760Sjairo.balart@metempsy.com ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 153513760Sjairo.balart@metempsy.com 153613760Sjairo.balart@metempsy.com val = ich_lr_el2; 153713531Sjairo.balart@metempsy.com do_virtual_update = true; 153813531Sjairo.balart@metempsy.com break; 153913531Sjairo.balart@metempsy.com } 154013531Sjairo.balart@metempsy.com 154113760Sjairo.balart@metempsy.com // Virtual Machine Control Register 154213531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 154313531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: { 154413760Sjairo.balart@metempsy.com ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 154513760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 154613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 154713760Sjairo.balart@metempsy.com ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; 154813531Sjairo.balart@metempsy.com uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS; 154913760Sjairo.balart@metempsy.com 155013760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 155113760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = min_vpr0; 155213760Sjairo.balart@metempsy.com } else { 155313760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 155413760Sjairo.balart@metempsy.com } 155513760Sjairo.balart@metempsy.com 155613531Sjairo.balart@metempsy.com uint8_t min_vpr1 = min_vpr0 + 1; 155713760Sjairo.balart@metempsy.com 155813760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 155913760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = min_vpr1; 156013760Sjairo.balart@metempsy.com } else { 156113760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 156213760Sjairo.balart@metempsy.com } 156313760Sjairo.balart@metempsy.com 156413760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 156513760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 156613760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 156713760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 156813760Sjairo.balart@metempsy.com val = ich_vmcr_el2; 156913531Sjairo.balart@metempsy.com break; 157013531Sjairo.balart@metempsy.com } 157113531Sjairo.balart@metempsy.com 157213760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 157314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0: 157414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0_EL2: 157514236Sgiacomo.travaglini@arm.com break; 157614236Sgiacomo.travaglini@arm.com 157714236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 157814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 157914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 158014236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 158114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 158214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 158314236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 158414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 158514236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 158614236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 158714236Sgiacomo.travaglini@arm.com return; 158814236Sgiacomo.travaglini@arm.com 158913760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 159014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0: 159114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0_EL2: 159213531Sjairo.balart@metempsy.com break; 159313531Sjairo.balart@metempsy.com 159414236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 159514236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 159614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 159714236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 159814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 159914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 160014236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 160114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 160214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 160314236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 160414236Sgiacomo.travaglini@arm.com return; 160514236Sgiacomo.travaglini@arm.com 160613531Sjairo.balart@metempsy.com default: 160713760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 160813760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 160913531Sjairo.balart@metempsy.com } 161013531Sjairo.balart@metempsy.com 161113531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(misc_reg, val); 161213531Sjairo.balart@metempsy.com 161313531Sjairo.balart@metempsy.com if (do_virtual_update) { 161413531Sjairo.balart@metempsy.com virtualUpdate(); 161513531Sjairo.balart@metempsy.com } 161613531Sjairo.balart@metempsy.com} 161713531Sjairo.balart@metempsy.com 161814243Sgiacomo.travaglini@arm.comRegVal 161914243Sgiacomo.travaglini@arm.comGicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const 162014243Sgiacomo.travaglini@arm.com{ 162114243Sgiacomo.travaglini@arm.com return isa->readMiscRegNoEffect( 162214243Sgiacomo.travaglini@arm.com isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3())); 162314243Sgiacomo.travaglini@arm.com} 162414243Sgiacomo.travaglini@arm.com 162514243Sgiacomo.travaglini@arm.comvoid 162614243Sgiacomo.travaglini@arm.comGicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const 162714243Sgiacomo.travaglini@arm.com{ 162814243Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect( 162914243Sgiacomo.travaglini@arm.com isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val); 163014243Sgiacomo.travaglini@arm.com} 163114243Sgiacomo.travaglini@arm.com 163213531Sjairo.balart@metempsy.comint 163313760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualFindActive(uint32_t int_id) const 163413531Sjairo.balart@metempsy.com{ 163513531Sjairo.balart@metempsy.com for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 163613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 163713531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 163813760Sjairo.balart@metempsy.com 163913760Sjairo.balart@metempsy.com if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 164013760Sjairo.balart@metempsy.com (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 164113760Sjairo.balart@metempsy.com (ich_lr_el2.vINTID == int_id)) { 164213531Sjairo.balart@metempsy.com return lr_idx; 164313531Sjairo.balart@metempsy.com } 164413531Sjairo.balart@metempsy.com } 164513531Sjairo.balart@metempsy.com 164613531Sjairo.balart@metempsy.com return -1; 164713531Sjairo.balart@metempsy.com} 164813531Sjairo.balart@metempsy.com 164913531Sjairo.balart@metempsy.comuint32_t 165013760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR0() const 165113531Sjairo.balart@metempsy.com{ 165214233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 165313531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 165413531Sjairo.balart@metempsy.com } 165513531Sjairo.balart@metempsy.com 165613531Sjairo.balart@metempsy.com bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 165713531Sjairo.balart@metempsy.com 165813531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) { 165913760Sjairo.balart@metempsy.com // interrupt for the other state pending 166013531Sjairo.balart@metempsy.com return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 166113531Sjairo.balart@metempsy.com } 166213531Sjairo.balart@metempsy.com 166313531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 166413531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 166513531Sjairo.balart@metempsy.com } 166613531Sjairo.balart@metempsy.com 166713531Sjairo.balart@metempsy.com if (irq_is_secure && !inSecureState()) { 166813531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 166913531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 167013531Sjairo.balart@metempsy.com } 167113531Sjairo.balart@metempsy.com 167213531Sjairo.balart@metempsy.com return hppi.intid; 167313531Sjairo.balart@metempsy.com} 167413531Sjairo.balart@metempsy.com 167513531Sjairo.balart@metempsy.comuint32_t 167613760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR1() const 167713531Sjairo.balart@metempsy.com{ 167814233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 167913531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 168013531Sjairo.balart@metempsy.com } 168113531Sjairo.balart@metempsy.com 168213760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 168313760Sjairo.balart@metempsy.com if ((currEL() == EL3) && icc_ctlr_el3.RM) { 168413531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 168513531Sjairo.balart@metempsy.com return Gicv3::INTID_SECURE; 168613531Sjairo.balart@metempsy.com } else if (hppi.group == Gicv3::G1NS) { 168713531Sjairo.balart@metempsy.com return Gicv3::INTID_NONSECURE; 168813531Sjairo.balart@metempsy.com } 168913531Sjairo.balart@metempsy.com } 169013531Sjairo.balart@metempsy.com 169113531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 169213531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169313531Sjairo.balart@metempsy.com } 169413531Sjairo.balart@metempsy.com 169513531Sjairo.balart@metempsy.com bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 169613531Sjairo.balart@metempsy.com 169713531Sjairo.balart@metempsy.com if (irq_is_secure) { 169813531Sjairo.balart@metempsy.com if (!inSecureState()) { 169913531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 170013531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170113531Sjairo.balart@metempsy.com } 170213531Sjairo.balart@metempsy.com } else if (!isEL3OrMon() && inSecureState()) { 170313531Sjairo.balart@metempsy.com // Group 1 non-secure interrupts not visible in Secure EL1 170413531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170513531Sjairo.balart@metempsy.com } 170613531Sjairo.balart@metempsy.com 170713531Sjairo.balart@metempsy.com return hppi.intid; 170813531Sjairo.balart@metempsy.com} 170913531Sjairo.balart@metempsy.com 171013531Sjairo.balart@metempsy.comvoid 171113531Sjairo.balart@metempsy.comGicv3CPUInterface::dropPriority(Gicv3::GroupId group) 171213531Sjairo.balart@metempsy.com{ 171314246Sgiacomo.travaglini@arm.com int apr_misc_reg = 0; 171414246Sgiacomo.travaglini@arm.com 171514246Sgiacomo.travaglini@arm.com switch (group) { 171614246Sgiacomo.travaglini@arm.com case Gicv3::G0S: 171714246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP0R0_EL1; 171814246Sgiacomo.travaglini@arm.com break; 171914246Sgiacomo.travaglini@arm.com case Gicv3::G1S: 172014246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S; 172114246Sgiacomo.travaglini@arm.com break; 172214246Sgiacomo.travaglini@arm.com case Gicv3::G1NS: 172314246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS; 172414246Sgiacomo.travaglini@arm.com break; 172514246Sgiacomo.travaglini@arm.com default: 172614246Sgiacomo.travaglini@arm.com panic("Invalid Gicv3::GroupId"); 172714246Sgiacomo.travaglini@arm.com } 172814246Sgiacomo.travaglini@arm.com 172914246Sgiacomo.travaglini@arm.com RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg); 173013531Sjairo.balart@metempsy.com 173113531Sjairo.balart@metempsy.com if (apr) { 173213531Sjairo.balart@metempsy.com apr &= apr - 1; 173313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_misc_reg, apr); 173413531Sjairo.balart@metempsy.com } 173513531Sjairo.balart@metempsy.com 173613531Sjairo.balart@metempsy.com update(); 173713531Sjairo.balart@metempsy.com} 173813531Sjairo.balart@metempsy.com 173913531Sjairo.balart@metempsy.comuint8_t 174013531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDropPriority() 174113531Sjairo.balart@metempsy.com{ 174213531Sjairo.balart@metempsy.com int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 174313531Sjairo.balart@metempsy.com 174413531Sjairo.balart@metempsy.com for (int i = 0; i < apr_max; i++) { 174513580Sgabeblack@google.com RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 174613580Sgabeblack@google.com RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 174713531Sjairo.balart@metempsy.com 174813531Sjairo.balart@metempsy.com if (!vapr0 && !vapr1) { 174913531Sjairo.balart@metempsy.com continue; 175013531Sjairo.balart@metempsy.com } 175113531Sjairo.balart@metempsy.com 175213531Sjairo.balart@metempsy.com int vapr0_count = ctz32(vapr0); 175313531Sjairo.balart@metempsy.com int vapr1_count = ctz32(vapr1); 175413531Sjairo.balart@metempsy.com 175513531Sjairo.balart@metempsy.com if (vapr0_count <= vapr1_count) { 175613531Sjairo.balart@metempsy.com vapr0 &= vapr0 - 1; 175713531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 175813531Sjairo.balart@metempsy.com return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 175913531Sjairo.balart@metempsy.com } else { 176013531Sjairo.balart@metempsy.com vapr1 &= vapr1 - 1; 176113531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 176213531Sjairo.balart@metempsy.com return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 176313531Sjairo.balart@metempsy.com } 176413531Sjairo.balart@metempsy.com } 176513531Sjairo.balart@metempsy.com 176613531Sjairo.balart@metempsy.com return 0xff; 176713531Sjairo.balart@metempsy.com} 176813531Sjairo.balart@metempsy.com 176913531Sjairo.balart@metempsy.comvoid 177014227Sgiacomo.travaglini@arm.comGicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group) 177114227Sgiacomo.travaglini@arm.com{ 177214227Sgiacomo.travaglini@arm.com uint8_t aff3 = bits(val, 55, 48); 177314227Sgiacomo.travaglini@arm.com uint8_t aff2 = bits(val, 39, 32); 177414227Sgiacomo.travaglini@arm.com uint8_t aff1 = bits(val, 23, 16);; 177514227Sgiacomo.travaglini@arm.com uint16_t target_list = bits(val, 15, 0); 177614227Sgiacomo.travaglini@arm.com uint32_t int_id = bits(val, 27, 24); 177714227Sgiacomo.travaglini@arm.com bool irm = bits(val, 40, 40); 177814227Sgiacomo.travaglini@arm.com uint8_t rs = bits(val, 47, 44); 177914227Sgiacomo.travaglini@arm.com 178014227Sgiacomo.travaglini@arm.com bool ns = !inSecureState(); 178114227Sgiacomo.travaglini@arm.com 178214227Sgiacomo.travaglini@arm.com for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 178314227Sgiacomo.travaglini@arm.com Gicv3Redistributor * redistributor_i = 178414227Sgiacomo.travaglini@arm.com gic->getRedistributor(i); 178514227Sgiacomo.travaglini@arm.com uint32_t affinity_i = redistributor_i->getAffinity(); 178614227Sgiacomo.travaglini@arm.com 178714227Sgiacomo.travaglini@arm.com if (irm) { 178814227Sgiacomo.travaglini@arm.com // Interrupts routed to all PEs in the system, 178914227Sgiacomo.travaglini@arm.com // excluding "self" 179014227Sgiacomo.travaglini@arm.com if (affinity_i == redistributor->getAffinity()) { 179114227Sgiacomo.travaglini@arm.com continue; 179214227Sgiacomo.travaglini@arm.com } 179314227Sgiacomo.travaglini@arm.com } else { 179414227Sgiacomo.travaglini@arm.com // Interrupts routed to the PEs specified by 179514227Sgiacomo.travaglini@arm.com // Aff3.Aff2.Aff1.<target list> 179614227Sgiacomo.travaglini@arm.com if ((affinity_i >> 8) != 179714227Sgiacomo.travaglini@arm.com ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { 179814227Sgiacomo.travaglini@arm.com continue; 179914227Sgiacomo.travaglini@arm.com } 180014227Sgiacomo.travaglini@arm.com 180114227Sgiacomo.travaglini@arm.com uint8_t aff0_i = bits(affinity_i, 7, 0); 180214227Sgiacomo.travaglini@arm.com 180314227Sgiacomo.travaglini@arm.com if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 && 180414227Sgiacomo.travaglini@arm.com ((0x1 << (aff0_i - rs * 16)) & target_list))) { 180514227Sgiacomo.travaglini@arm.com continue; 180614227Sgiacomo.travaglini@arm.com } 180714227Sgiacomo.travaglini@arm.com } 180814227Sgiacomo.travaglini@arm.com 180914227Sgiacomo.travaglini@arm.com redistributor_i->sendSGI(int_id, group, ns); 181014227Sgiacomo.travaglini@arm.com } 181114227Sgiacomo.travaglini@arm.com} 181214227Sgiacomo.travaglini@arm.com 181314227Sgiacomo.travaglini@arm.comvoid 181413531Sjairo.balart@metempsy.comGicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 181513531Sjairo.balart@metempsy.com{ 181613531Sjairo.balart@metempsy.com // Update active priority registers. 181713531Sjairo.balart@metempsy.com uint32_t prio = hppi.prio & 0xf8; 181813531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - PRIORITY_BITS); 181913531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 182014246Sgiacomo.travaglini@arm.com 182114246Sgiacomo.travaglini@arm.com int apr_idx = 0; 182214246Sgiacomo.travaglini@arm.com switch (group) { 182314246Sgiacomo.travaglini@arm.com case Gicv3::G0S: 182414246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP0R0_EL1; 182514246Sgiacomo.travaglini@arm.com break; 182614246Sgiacomo.travaglini@arm.com case Gicv3::G1S: 182714246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP1R0_EL1_S; 182814246Sgiacomo.travaglini@arm.com break; 182914246Sgiacomo.travaglini@arm.com case Gicv3::G1NS: 183014246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP1R0_EL1_NS; 183114246Sgiacomo.travaglini@arm.com break; 183214246Sgiacomo.travaglini@arm.com default: 183314246Sgiacomo.travaglini@arm.com panic("Invalid Gicv3::GroupId"); 183414246Sgiacomo.travaglini@arm.com } 183514246Sgiacomo.travaglini@arm.com 183613580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 183713531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 183813531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 183913531Sjairo.balart@metempsy.com 184013531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 184113531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 184213531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 184313531Sjairo.balart@metempsy.com redistributor->activateIRQ(int_id); 184413531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 184513531Sjairo.balart@metempsy.com // SPI, distributor 184613531Sjairo.balart@metempsy.com distributor->activateIRQ(int_id); 184713923Sgiacomo.travaglini@arm.com } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 184813923Sgiacomo.travaglini@arm.com // LPI, Redistributor 184913923Sgiacomo.travaglini@arm.com redistributor->setClrLPI(int_id, false); 185013531Sjairo.balart@metempsy.com } 185114231Sgiacomo.travaglini@arm.com 185214231Sgiacomo.travaglini@arm.com // By setting the priority to 0xff we are effectively 185314231Sgiacomo.travaglini@arm.com // making the int_id not pending anymore at the cpu 185414231Sgiacomo.travaglini@arm.com // interface. 185514231Sgiacomo.travaglini@arm.com hppi.prio = 0xff; 185614231Sgiacomo.travaglini@arm.com updateDistributor(); 185713531Sjairo.balart@metempsy.com} 185813531Sjairo.balart@metempsy.com 185913531Sjairo.balart@metempsy.comvoid 186013531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 186113531Sjairo.balart@metempsy.com{ 186213531Sjairo.balart@metempsy.com // Update active priority registers. 186313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 186413531Sjairo.balart@metempsy.com lr_idx); 186513760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 186613760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el.Priority & 0xf8; 186713531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 186813531Sjairo.balart@metempsy.com int reg_no = apr_bit / 32; 186913531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 187013531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 187113531Sjairo.balart@metempsy.com MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 187213580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 187313531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 187413531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 187513531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 187613760Sjairo.balart@metempsy.com ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 187713760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); 187813531Sjairo.balart@metempsy.com} 187913531Sjairo.balart@metempsy.com 188013531Sjairo.balart@metempsy.comvoid 188113531Sjairo.balart@metempsy.comGicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 188213531Sjairo.balart@metempsy.com{ 188313531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 188413531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 188513531Sjairo.balart@metempsy.com redistributor->deactivateIRQ(int_id); 188613531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 188713531Sjairo.balart@metempsy.com // SPI, distributor 188813531Sjairo.balart@metempsy.com distributor->deactivateIRQ(int_id); 188913531Sjairo.balart@metempsy.com } 189014231Sgiacomo.travaglini@arm.com 189114231Sgiacomo.travaglini@arm.com updateDistributor(); 189213531Sjairo.balart@metempsy.com} 189313531Sjairo.balart@metempsy.com 189413531Sjairo.balart@metempsy.comvoid 189513531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 189613531Sjairo.balart@metempsy.com{ 189713760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 189813531Sjairo.balart@metempsy.com lr_idx); 189913531Sjairo.balart@metempsy.com 190013760Sjairo.balart@metempsy.com if (ich_lr_el2.HW) { 190113531Sjairo.balart@metempsy.com // Deactivate the associated physical interrupt 190213760Sjairo.balart@metempsy.com if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 190313760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 190413760Sjairo.balart@metempsy.com distributor->getIntGroup(ich_lr_el2.pINTID) : 190513760Sjairo.balart@metempsy.com redistributor->getIntGroup(ich_lr_el2.pINTID); 190613760Sjairo.balart@metempsy.com deactivateIRQ(ich_lr_el2.pINTID, group); 190713531Sjairo.balart@metempsy.com } 190813531Sjairo.balart@metempsy.com } 190913531Sjairo.balart@metempsy.com 191013531Sjairo.balart@metempsy.com // Remove the active bit 191113760Sjairo.balart@metempsy.com ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 191213760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); 191313531Sjairo.balart@metempsy.com} 191413531Sjairo.balart@metempsy.com 191513531Sjairo.balart@metempsy.com/* 191613760Sjairo.balart@metempsy.com * Returns the priority group field for the current BPR value for the group. 191713760Sjairo.balart@metempsy.com * GroupBits() Pseudocode from spec. 191813531Sjairo.balart@metempsy.com */ 191913531Sjairo.balart@metempsy.comuint32_t 192013926Sgiacomo.travaglini@arm.comGicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) 192113531Sjairo.balart@metempsy.com{ 192213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 192313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 192413760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 192513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 192613760Sjairo.balart@metempsy.com 192713760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 192813760Sjairo.balart@metempsy.com (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 192913531Sjairo.balart@metempsy.com group = Gicv3::G0S; 193013531Sjairo.balart@metempsy.com } 193113531Sjairo.balart@metempsy.com 193213531Sjairo.balart@metempsy.com int bpr; 193313531Sjairo.balart@metempsy.com 193413531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 193513926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; 193614237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1S) { 193714237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1S) & 0x7; 193813531Sjairo.balart@metempsy.com } else { 193914237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1NS) & 0x7; 194013531Sjairo.balart@metempsy.com } 194113531Sjairo.balart@metempsy.com 194213531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 194313531Sjairo.balart@metempsy.com assert(bpr > 0); 194413531Sjairo.balart@metempsy.com bpr--; 194513531Sjairo.balart@metempsy.com } 194613531Sjairo.balart@metempsy.com 194713531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 194813531Sjairo.balart@metempsy.com} 194913531Sjairo.balart@metempsy.com 195013531Sjairo.balart@metempsy.comuint32_t 195113760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const 195213531Sjairo.balart@metempsy.com{ 195313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 195413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 195513531Sjairo.balart@metempsy.com 195613760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 195713531Sjairo.balart@metempsy.com group = Gicv3::G0S; 195813531Sjairo.balart@metempsy.com } 195913531Sjairo.balart@metempsy.com 196013531Sjairo.balart@metempsy.com int bpr; 196113531Sjairo.balart@metempsy.com 196213531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 196313760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR0; 196413531Sjairo.balart@metempsy.com } else { 196513760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR1; 196613531Sjairo.balart@metempsy.com } 196713531Sjairo.balart@metempsy.com 196813531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 196913531Sjairo.balart@metempsy.com assert(bpr > 0); 197013531Sjairo.balart@metempsy.com bpr--; 197113531Sjairo.balart@metempsy.com } 197213531Sjairo.balart@metempsy.com 197313531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 197413531Sjairo.balart@metempsy.com} 197513531Sjairo.balart@metempsy.com 197613531Sjairo.balart@metempsy.combool 197713760Sjairo.balart@metempsy.comGicv3CPUInterface::isEOISplitMode() const 197813531Sjairo.balart@metempsy.com{ 197913531Sjairo.balart@metempsy.com if (isEL3OrMon()) { 198013760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 198113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 198213760Sjairo.balart@metempsy.com return icc_ctlr_el3.EOImode_EL3; 198313531Sjairo.balart@metempsy.com } else { 198414245Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1 = 0; 198514245Sgiacomo.travaglini@arm.com if (inSecureState()) 198614245Sgiacomo.travaglini@arm.com icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 198714245Sgiacomo.travaglini@arm.com else 198814245Sgiacomo.travaglini@arm.com icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 198913760Sjairo.balart@metempsy.com return icc_ctlr_el1.EOImode; 199013531Sjairo.balart@metempsy.com } 199113531Sjairo.balart@metempsy.com} 199213531Sjairo.balart@metempsy.com 199313531Sjairo.balart@metempsy.combool 199413760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIsEOISplitMode() const 199513531Sjairo.balart@metempsy.com{ 199613760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 199713760Sjairo.balart@metempsy.com return ich_vmcr_el2.VEOIM; 199813531Sjairo.balart@metempsy.com} 199913531Sjairo.balart@metempsy.com 200013531Sjairo.balart@metempsy.comint 200113760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActiveGroup() const 200213531Sjairo.balart@metempsy.com{ 200313531Sjairo.balart@metempsy.com int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 200413531Sjairo.balart@metempsy.com int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 200513531Sjairo.balart@metempsy.com int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 200613531Sjairo.balart@metempsy.com 200713531Sjairo.balart@metempsy.com if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 200813531Sjairo.balart@metempsy.com return Gicv3::G1NS; 200913531Sjairo.balart@metempsy.com } 201013531Sjairo.balart@metempsy.com 201113531Sjairo.balart@metempsy.com if (gq_ctz < g0_ctz) { 201213531Sjairo.balart@metempsy.com return Gicv3::G1S; 201313531Sjairo.balart@metempsy.com } 201413531Sjairo.balart@metempsy.com 201513531Sjairo.balart@metempsy.com if (g0_ctz < 32) { 201613531Sjairo.balart@metempsy.com return Gicv3::G0S; 201713531Sjairo.balart@metempsy.com } 201813531Sjairo.balart@metempsy.com 201913531Sjairo.balart@metempsy.com return -1; 202013531Sjairo.balart@metempsy.com} 202113531Sjairo.balart@metempsy.com 202213531Sjairo.balart@metempsy.comvoid 202314231Sgiacomo.travaglini@arm.comGicv3CPUInterface::updateDistributor() 202414231Sgiacomo.travaglini@arm.com{ 202514231Sgiacomo.travaglini@arm.com distributor->update(); 202614231Sgiacomo.travaglini@arm.com} 202714231Sgiacomo.travaglini@arm.com 202814231Sgiacomo.travaglini@arm.comvoid 202913531Sjairo.balart@metempsy.comGicv3CPUInterface::update() 203013531Sjairo.balart@metempsy.com{ 203113531Sjairo.balart@metempsy.com bool signal_IRQ = false; 203213531Sjairo.balart@metempsy.com bool signal_FIQ = false; 203313531Sjairo.balart@metempsy.com 203413531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 203513531Sjairo.balart@metempsy.com /* 203613531Sjairo.balart@metempsy.com * Secure enabled GIC sending a G1S IRQ to a secure disabled 203713531Sjairo.balart@metempsy.com * CPU -> send G0 IRQ 203813531Sjairo.balart@metempsy.com */ 203913531Sjairo.balart@metempsy.com hppi.group = Gicv3::G0S; 204013531Sjairo.balart@metempsy.com } 204113531Sjairo.balart@metempsy.com 204213531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 204313531Sjairo.balart@metempsy.com ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 204413531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::update(): " 204513531Sjairo.balart@metempsy.com "posting int as %d!\n", int_type); 204613531Sjairo.balart@metempsy.com int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 204713531Sjairo.balart@metempsy.com } 204813531Sjairo.balart@metempsy.com 204913531Sjairo.balart@metempsy.com if (signal_IRQ) { 205013531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_IRQ); 205113531Sjairo.balart@metempsy.com } else { 205213531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_IRQ); 205313531Sjairo.balart@metempsy.com } 205413531Sjairo.balart@metempsy.com 205513531Sjairo.balart@metempsy.com if (signal_FIQ) { 205613531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_FIQ); 205713531Sjairo.balart@metempsy.com } else { 205813531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_FIQ); 205913531Sjairo.balart@metempsy.com } 206013531Sjairo.balart@metempsy.com} 206113531Sjairo.balart@metempsy.com 206213531Sjairo.balart@metempsy.comvoid 206313531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualUpdate() 206413531Sjairo.balart@metempsy.com{ 206513531Sjairo.balart@metempsy.com bool signal_IRQ = false; 206613531Sjairo.balart@metempsy.com bool signal_FIQ = false; 206713531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 206813531Sjairo.balart@metempsy.com 206913531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 207013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 207113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 207213531Sjairo.balart@metempsy.com 207313531Sjairo.balart@metempsy.com if (hppviCanPreempt(lr_idx)) { 207413760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 207513531Sjairo.balart@metempsy.com signal_IRQ = true; 207613531Sjairo.balart@metempsy.com } else { 207713531Sjairo.balart@metempsy.com signal_FIQ = true; 207813531Sjairo.balart@metempsy.com } 207913531Sjairo.balart@metempsy.com } 208013531Sjairo.balart@metempsy.com } 208113531Sjairo.balart@metempsy.com 208213760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 208313760Sjairo.balart@metempsy.com 208413760Sjairo.balart@metempsy.com if (ich_hcr_el2.En) { 208513531Sjairo.balart@metempsy.com if (maintenanceInterruptStatus()) { 208613826Sgiacomo.travaglini@arm.com maintenanceInterrupt->raise(); 208713531Sjairo.balart@metempsy.com } 208813531Sjairo.balart@metempsy.com } 208913531Sjairo.balart@metempsy.com 209013531Sjairo.balart@metempsy.com if (signal_IRQ) { 209113531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 209213531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 209313531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 209413531Sjairo.balart@metempsy.com } else { 209513531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 209613531Sjairo.balart@metempsy.com } 209713531Sjairo.balart@metempsy.com 209813531Sjairo.balart@metempsy.com if (signal_FIQ) { 209913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 210013531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 210113531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 210213531Sjairo.balart@metempsy.com } else { 210313531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 210413531Sjairo.balart@metempsy.com } 210513531Sjairo.balart@metempsy.com} 210613531Sjairo.balart@metempsy.com 210713760Sjairo.balart@metempsy.com// Returns the index of the LR with the HPPI 210813531Sjairo.balart@metempsy.comint 210913760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPVILR() const 211013531Sjairo.balart@metempsy.com{ 211113531Sjairo.balart@metempsy.com int idx = -1; 211213760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 211313760Sjairo.balart@metempsy.com 211413760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { 211513531Sjairo.balart@metempsy.com // VG0 and VG1 disabled... 211613531Sjairo.balart@metempsy.com return idx; 211713531Sjairo.balart@metempsy.com } 211813531Sjairo.balart@metempsy.com 211913531Sjairo.balart@metempsy.com uint8_t highest_prio = 0xff; 212013531Sjairo.balart@metempsy.com 212113531Sjairo.balart@metempsy.com for (int i = 0; i < 16; i++) { 212213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 212313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i); 212413760Sjairo.balart@metempsy.com 212513760Sjairo.balart@metempsy.com if (ich_lr_el2.State != Gicv3::INT_PENDING) { 212613531Sjairo.balart@metempsy.com continue; 212713531Sjairo.balart@metempsy.com } 212813531Sjairo.balart@metempsy.com 212913760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 213013531Sjairo.balart@metempsy.com // VG1 213113760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG1) { 213213531Sjairo.balart@metempsy.com continue; 213313531Sjairo.balart@metempsy.com } 213413531Sjairo.balart@metempsy.com } else { 213513531Sjairo.balart@metempsy.com // VG0 213613760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0) { 213713531Sjairo.balart@metempsy.com continue; 213813531Sjairo.balart@metempsy.com } 213913531Sjairo.balart@metempsy.com } 214013531Sjairo.balart@metempsy.com 214113760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 214213531Sjairo.balart@metempsy.com 214313531Sjairo.balart@metempsy.com if (prio < highest_prio) { 214413531Sjairo.balart@metempsy.com highest_prio = prio; 214513531Sjairo.balart@metempsy.com idx = i; 214613531Sjairo.balart@metempsy.com } 214713531Sjairo.balart@metempsy.com } 214813531Sjairo.balart@metempsy.com 214913531Sjairo.balart@metempsy.com return idx; 215013531Sjairo.balart@metempsy.com} 215113531Sjairo.balart@metempsy.com 215213531Sjairo.balart@metempsy.combool 215313760Sjairo.balart@metempsy.comGicv3CPUInterface::hppviCanPreempt(int lr_idx) const 215413531Sjairo.balart@metempsy.com{ 215513760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 215613760Sjairo.balart@metempsy.com if (!ich_hcr_el2.En) { 215713531Sjairo.balart@metempsy.com // virtual interface is disabled 215813531Sjairo.balart@metempsy.com return false; 215913531Sjairo.balart@metempsy.com } 216013531Sjairo.balart@metempsy.com 216113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 216213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 216313760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 216413531Sjairo.balart@metempsy.com uint8_t vpmr = 216513531Sjairo.balart@metempsy.com bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 216613531Sjairo.balart@metempsy.com 216713531Sjairo.balart@metempsy.com if (prio >= vpmr) { 216813531Sjairo.balart@metempsy.com // prioriry masked 216913531Sjairo.balart@metempsy.com return false; 217013531Sjairo.balart@metempsy.com } 217113531Sjairo.balart@metempsy.com 217213531Sjairo.balart@metempsy.com uint8_t rprio = virtualHighestActivePriority(); 217313531Sjairo.balart@metempsy.com 217413531Sjairo.balart@metempsy.com if (rprio == 0xff) { 217513531Sjairo.balart@metempsy.com return true; 217613531Sjairo.balart@metempsy.com } 217713531Sjairo.balart@metempsy.com 217813760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 217913531Sjairo.balart@metempsy.com uint32_t prio_mask = virtualGroupPriorityMask(group); 218013531Sjairo.balart@metempsy.com 218113531Sjairo.balart@metempsy.com if ((prio & prio_mask) < (rprio & prio_mask)) { 218213531Sjairo.balart@metempsy.com return true; 218313531Sjairo.balart@metempsy.com } 218413531Sjairo.balart@metempsy.com 218513531Sjairo.balart@metempsy.com return false; 218613531Sjairo.balart@metempsy.com} 218713531Sjairo.balart@metempsy.com 218813531Sjairo.balart@metempsy.comuint8_t 218913760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualHighestActivePriority() const 219013531Sjairo.balart@metempsy.com{ 219113531Sjairo.balart@metempsy.com uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 219213531Sjairo.balart@metempsy.com 219313531Sjairo.balart@metempsy.com for (int i = 0; i < num_aprs; i++) { 219413580Sgabeblack@google.com RegVal vapr = 219513531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 219613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 219713531Sjairo.balart@metempsy.com 219813531Sjairo.balart@metempsy.com if (!vapr) { 219913531Sjairo.balart@metempsy.com continue; 220013531Sjairo.balart@metempsy.com } 220113531Sjairo.balart@metempsy.com 220213531Sjairo.balart@metempsy.com return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 220313531Sjairo.balart@metempsy.com } 220413531Sjairo.balart@metempsy.com 220513531Sjairo.balart@metempsy.com // no active interrups, return idle priority 220613531Sjairo.balart@metempsy.com return 0xff; 220713531Sjairo.balart@metempsy.com} 220813531Sjairo.balart@metempsy.com 220913531Sjairo.balart@metempsy.comvoid 221013531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIncrementEOICount() 221113531Sjairo.balart@metempsy.com{ 221213531Sjairo.balart@metempsy.com // Increment the EOICOUNT field in ICH_HCR_EL2 221313580Sgabeblack@google.com RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 221413531Sjairo.balart@metempsy.com uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 221513531Sjairo.balart@metempsy.com EOI_cout++; 221613531Sjairo.balart@metempsy.com ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 221713531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 221813531Sjairo.balart@metempsy.com} 221913531Sjairo.balart@metempsy.com 222013760Sjairo.balart@metempsy.com// spec section 4.6.2 222113531Sjairo.balart@metempsy.comArmISA::InterruptTypes 222213760Sjairo.balart@metempsy.comGicv3CPUInterface::intSignalType(Gicv3::GroupId group) const 222313531Sjairo.balart@metempsy.com{ 222413531Sjairo.balart@metempsy.com bool is_fiq = false; 222513531Sjairo.balart@metempsy.com 222613531Sjairo.balart@metempsy.com switch (group) { 222713531Sjairo.balart@metempsy.com case Gicv3::G0S: 222813531Sjairo.balart@metempsy.com is_fiq = true; 222913531Sjairo.balart@metempsy.com break; 223013531Sjairo.balart@metempsy.com 223113531Sjairo.balart@metempsy.com case Gicv3::G1S: 223213531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && 223313531Sjairo.balart@metempsy.com (!inSecureState() || ((currEL() == EL3) && isAA64())); 223413531Sjairo.balart@metempsy.com break; 223513531Sjairo.balart@metempsy.com 223613531Sjairo.balart@metempsy.com case Gicv3::G1NS: 223713531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && inSecureState(); 223813531Sjairo.balart@metempsy.com break; 223913531Sjairo.balart@metempsy.com 224013531Sjairo.balart@metempsy.com default: 224113531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 224213531Sjairo.balart@metempsy.com } 224313531Sjairo.balart@metempsy.com 224413531Sjairo.balart@metempsy.com if (is_fiq) { 224513531Sjairo.balart@metempsy.com return ArmISA::INT_FIQ; 224613531Sjairo.balart@metempsy.com } else { 224713531Sjairo.balart@metempsy.com return ArmISA::INT_IRQ; 224813531Sjairo.balart@metempsy.com } 224913531Sjairo.balart@metempsy.com} 225013531Sjairo.balart@metempsy.com 225113531Sjairo.balart@metempsy.combool 225213926Sgiacomo.travaglini@arm.comGicv3CPUInterface::hppiCanPreempt() 225313531Sjairo.balart@metempsy.com{ 225413531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 225513531Sjairo.balart@metempsy.com // there is no pending interrupt 225613531Sjairo.balart@metempsy.com return false; 225713531Sjairo.balart@metempsy.com } 225813531Sjairo.balart@metempsy.com 225913531Sjairo.balart@metempsy.com if (!groupEnabled(hppi.group)) { 226013531Sjairo.balart@metempsy.com // group disabled at CPU interface 226113531Sjairo.balart@metempsy.com return false; 226213531Sjairo.balart@metempsy.com } 226313531Sjairo.balart@metempsy.com 226413531Sjairo.balart@metempsy.com if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 226513531Sjairo.balart@metempsy.com // priority masked 226613531Sjairo.balart@metempsy.com return false; 226713531Sjairo.balart@metempsy.com } 226813531Sjairo.balart@metempsy.com 226913531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 227013531Sjairo.balart@metempsy.com 227113531Sjairo.balart@metempsy.com if (rprio == 0xff) { 227213531Sjairo.balart@metempsy.com return true; 227313531Sjairo.balart@metempsy.com } 227413531Sjairo.balart@metempsy.com 227513531Sjairo.balart@metempsy.com uint32_t prio_mask = groupPriorityMask(hppi.group); 227613531Sjairo.balart@metempsy.com 227713531Sjairo.balart@metempsy.com if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 227813531Sjairo.balart@metempsy.com return true; 227913531Sjairo.balart@metempsy.com } 228013531Sjairo.balart@metempsy.com 228113531Sjairo.balart@metempsy.com return false; 228213531Sjairo.balart@metempsy.com} 228313531Sjairo.balart@metempsy.com 228413531Sjairo.balart@metempsy.comuint8_t 228513760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActivePriority() const 228613531Sjairo.balart@metempsy.com{ 228713531Sjairo.balart@metempsy.com uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 228813531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 228913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 229013531Sjairo.balart@metempsy.com 229113531Sjairo.balart@metempsy.com if (apr) { 229213531Sjairo.balart@metempsy.com return ctz32(apr) << (GIC_MIN_BPR + 1); 229313531Sjairo.balart@metempsy.com } 229413531Sjairo.balart@metempsy.com 229513531Sjairo.balart@metempsy.com // no active interrups, return idle priority 229613531Sjairo.balart@metempsy.com return 0xff; 229713531Sjairo.balart@metempsy.com} 229813531Sjairo.balart@metempsy.com 229913531Sjairo.balart@metempsy.combool 230013760Sjairo.balart@metempsy.comGicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 230113531Sjairo.balart@metempsy.com{ 230213531Sjairo.balart@metempsy.com switch (group) { 230313760Sjairo.balart@metempsy.com case Gicv3::G0S: { 230413760Sjairo.balart@metempsy.com ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 230513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 230614234Sgiacomo.travaglini@arm.com return icc_igrpen0_el1.Enable && distributor->EnableGrp0; 230713760Sjairo.balart@metempsy.com } 230813760Sjairo.balart@metempsy.com 230913760Sjairo.balart@metempsy.com case Gicv3::G1S: { 231013760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 231113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 231214234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S; 231313760Sjairo.balart@metempsy.com } 231413760Sjairo.balart@metempsy.com 231513760Sjairo.balart@metempsy.com case Gicv3::G1NS: { 231613760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 231713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 231814234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS; 231913760Sjairo.balart@metempsy.com } 232013531Sjairo.balart@metempsy.com 232113531Sjairo.balart@metempsy.com default: 232213531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 232313531Sjairo.balart@metempsy.com } 232413531Sjairo.balart@metempsy.com} 232513531Sjairo.balart@metempsy.com 232613531Sjairo.balart@metempsy.combool 232713760Sjairo.balart@metempsy.comGicv3CPUInterface::inSecureState() const 232813531Sjairo.balart@metempsy.com{ 232913531Sjairo.balart@metempsy.com if (!gic->getSystem()->haveSecurity()) { 233013531Sjairo.balart@metempsy.com return false; 233113531Sjairo.balart@metempsy.com } 233213531Sjairo.balart@metempsy.com 233313531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 233413531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 233513531Sjairo.balart@metempsy.com return ArmISA::inSecureState(scr, cpsr); 233613531Sjairo.balart@metempsy.com} 233713531Sjairo.balart@metempsy.com 233813531Sjairo.balart@metempsy.comint 233913760Sjairo.balart@metempsy.comGicv3CPUInterface::currEL() const 234013531Sjairo.balart@metempsy.com{ 234113531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 234213531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 234313531Sjairo.balart@metempsy.com 234413531Sjairo.balart@metempsy.com if (is_64) { 234513531Sjairo.balart@metempsy.com return (ExceptionLevel)(uint8_t) cpsr.el; 234613531Sjairo.balart@metempsy.com } else { 234713531Sjairo.balart@metempsy.com switch (cpsr.mode) { 234813531Sjairo.balart@metempsy.com case MODE_USER: 234913531Sjairo.balart@metempsy.com return 0; 235013531Sjairo.balart@metempsy.com 235113531Sjairo.balart@metempsy.com case MODE_HYP: 235213531Sjairo.balart@metempsy.com return 2; 235313531Sjairo.balart@metempsy.com 235413531Sjairo.balart@metempsy.com case MODE_MON: 235513531Sjairo.balart@metempsy.com return 3; 235613531Sjairo.balart@metempsy.com 235713531Sjairo.balart@metempsy.com default: 235813531Sjairo.balart@metempsy.com return 1; 235913531Sjairo.balart@metempsy.com } 236013531Sjairo.balart@metempsy.com } 236113531Sjairo.balart@metempsy.com} 236213531Sjairo.balart@metempsy.com 236313531Sjairo.balart@metempsy.combool 236413760Sjairo.balart@metempsy.comGicv3CPUInterface::haveEL(ExceptionLevel el) const 236513531Sjairo.balart@metempsy.com{ 236613531Sjairo.balart@metempsy.com switch (el) { 236713531Sjairo.balart@metempsy.com case EL0: 236813531Sjairo.balart@metempsy.com case EL1: 236913531Sjairo.balart@metempsy.com return true; 237013531Sjairo.balart@metempsy.com 237113531Sjairo.balart@metempsy.com case EL2: 237213531Sjairo.balart@metempsy.com return gic->getSystem()->haveVirtualization(); 237313531Sjairo.balart@metempsy.com 237413531Sjairo.balart@metempsy.com case EL3: 237513531Sjairo.balart@metempsy.com return gic->getSystem()->haveSecurity(); 237613531Sjairo.balart@metempsy.com 237713531Sjairo.balart@metempsy.com default: 237813531Sjairo.balart@metempsy.com warn("Unimplemented Exception Level\n"); 237913531Sjairo.balart@metempsy.com return false; 238013531Sjairo.balart@metempsy.com } 238113531Sjairo.balart@metempsy.com} 238213531Sjairo.balart@metempsy.com 238313531Sjairo.balart@metempsy.combool 238413760Sjairo.balart@metempsy.comGicv3CPUInterface::isSecureBelowEL3() const 238513531Sjairo.balart@metempsy.com{ 238613531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 238713531Sjairo.balart@metempsy.com return haveEL(EL3) && scr.ns == 0; 238813531Sjairo.balart@metempsy.com} 238913531Sjairo.balart@metempsy.com 239013531Sjairo.balart@metempsy.combool 239113760Sjairo.balart@metempsy.comGicv3CPUInterface::isAA64() const 239213531Sjairo.balart@metempsy.com{ 239313531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 239413531Sjairo.balart@metempsy.com return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 239513531Sjairo.balart@metempsy.com} 239613531Sjairo.balart@metempsy.com 239713531Sjairo.balart@metempsy.combool 239813760Sjairo.balart@metempsy.comGicv3CPUInterface::isEL3OrMon() const 239913531Sjairo.balart@metempsy.com{ 240013531Sjairo.balart@metempsy.com if (haveEL(EL3)) { 240113531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 240213531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 240313531Sjairo.balart@metempsy.com 240413531Sjairo.balart@metempsy.com if (is_64 && (cpsr.el == EL3)) { 240513531Sjairo.balart@metempsy.com return true; 240613531Sjairo.balart@metempsy.com } else if (!is_64 && (cpsr.mode == MODE_MON)) { 240713531Sjairo.balart@metempsy.com return true; 240813531Sjairo.balart@metempsy.com } 240913531Sjairo.balart@metempsy.com } 241013531Sjairo.balart@metempsy.com 241113531Sjairo.balart@metempsy.com return false; 241213531Sjairo.balart@metempsy.com} 241313531Sjairo.balart@metempsy.com 241413760Sjairo.balart@metempsy.com// Computes ICH_EISR_EL2 241513760Sjairo.balart@metempsy.comuint64_t 241613760Sjairo.balart@metempsy.comGicv3CPUInterface::eoiMaintenanceInterruptStatus() const 241713531Sjairo.balart@metempsy.com{ 241813760Sjairo.balart@metempsy.com // ICH_EISR_EL2 241913760Sjairo.balart@metempsy.com // Bits [63:16] - RES0 242013760Sjairo.balart@metempsy.com // Status<n>, bit [n], for n = 0 to 15 242113760Sjairo.balart@metempsy.com // EOI maintenance interrupt status bit for List register <n>: 242213760Sjairo.balart@metempsy.com // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 242313760Sjairo.balart@metempsy.com // maintenance interrupt. 242413760Sjairo.balart@metempsy.com // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 242513760Sjairo.balart@metempsy.com // interrupt that has not been handled. 242613760Sjairo.balart@metempsy.com // 242713760Sjairo.balart@metempsy.com // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 242813760Sjairo.balart@metempsy.com // of the following are true: 242913760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 243013760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.HW is 0. 243113760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. 243213760Sjairo.balart@metempsy.com 243313760Sjairo.balart@metempsy.com uint64_t value = 0; 243413531Sjairo.balart@metempsy.com 243513531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 243613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 243713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 243813760Sjairo.balart@metempsy.com 243913760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 244013760Sjairo.balart@metempsy.com !ich_lr_el2.HW && ich_lr_el2.EOI) { 244113531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 244213531Sjairo.balart@metempsy.com } 244313760Sjairo.balart@metempsy.com } 244413760Sjairo.balart@metempsy.com 244513760Sjairo.balart@metempsy.com return value; 244613760Sjairo.balart@metempsy.com} 244713760Sjairo.balart@metempsy.com 244813760Sjairo.balart@metempsy.comGicv3CPUInterface::ICH_MISR_EL2 244913760Sjairo.balart@metempsy.comGicv3CPUInterface::maintenanceInterruptStatus() const 245013760Sjairo.balart@metempsy.com{ 245113760Sjairo.balart@metempsy.com // Comments are copied from SPEC section 9.4.7 (ID012119) 245213760Sjairo.balart@metempsy.com ICH_MISR_EL2 ich_misr_el2 = 0; 245313760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 245413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 245513760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 245613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 245713760Sjairo.balart@metempsy.com 245813760Sjairo.balart@metempsy.com // End Of Interrupt. [bit 0] 245913760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when at least one bit in 246013760Sjairo.balart@metempsy.com // ICH_EISR_EL2 is 1. 246113760Sjairo.balart@metempsy.com 246213760Sjairo.balart@metempsy.com if (eoiMaintenanceInterruptStatus()) { 246313760Sjairo.balart@metempsy.com ich_misr_el2.EOI = 1; 246413760Sjairo.balart@metempsy.com } 246513760Sjairo.balart@metempsy.com 246613760Sjairo.balart@metempsy.com // Underflow. [bit 1] 246713760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 246813760Sjairo.balart@metempsy.com // zero or one of the List register entries are marked as a valid 246913760Sjairo.balart@metempsy.com // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 247013760Sjairo.balart@metempsy.com // do not equal 0x0. 247113760Sjairo.balart@metempsy.com uint32_t num_valid_interrupts = 0; 247213760Sjairo.balart@metempsy.com uint32_t num_pending_interrupts = 0; 247313760Sjairo.balart@metempsy.com 247413760Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 247513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 247613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 247713760Sjairo.balart@metempsy.com 247813760Sjairo.balart@metempsy.com if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 247913760Sjairo.balart@metempsy.com num_valid_interrupts++; 248013531Sjairo.balart@metempsy.com } 248113531Sjairo.balart@metempsy.com 248213760Sjairo.balart@metempsy.com if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 248313760Sjairo.balart@metempsy.com num_pending_interrupts++; 248413531Sjairo.balart@metempsy.com } 248513531Sjairo.balart@metempsy.com } 248613531Sjairo.balart@metempsy.com 248713760Sjairo.balart@metempsy.com if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 248813760Sjairo.balart@metempsy.com ich_misr_el2.U = 1; 248913531Sjairo.balart@metempsy.com } 249013531Sjairo.balart@metempsy.com 249113760Sjairo.balart@metempsy.com // List Register Entry Not Present. [bit 2] 249213760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 249313760Sjairo.balart@metempsy.com // and ICH_HCR_EL2.EOIcount is non-zero. 249413760Sjairo.balart@metempsy.com if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 249513760Sjairo.balart@metempsy.com ich_misr_el2.LRENP = 1; 249613531Sjairo.balart@metempsy.com } 249713531Sjairo.balart@metempsy.com 249813760Sjairo.balart@metempsy.com // No Pending. [bit 3] 249913760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 250013760Sjairo.balart@metempsy.com // no List register is in pending state. 250113760Sjairo.balart@metempsy.com if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 250213760Sjairo.balart@metempsy.com ich_misr_el2.NP = 1; 250313531Sjairo.balart@metempsy.com } 250413531Sjairo.balart@metempsy.com 250513760Sjairo.balart@metempsy.com // vPE Group 0 Enabled. [bit 4] 250613760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 250713760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 250813760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 250913760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0E = 1; 251013531Sjairo.balart@metempsy.com } 251113531Sjairo.balart@metempsy.com 251213760Sjairo.balart@metempsy.com // vPE Group 0 Disabled. [bit 5] 251313760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 251413760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 251513760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 251613760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0D = 1; 251713531Sjairo.balart@metempsy.com } 251813531Sjairo.balart@metempsy.com 251913760Sjairo.balart@metempsy.com // vPE Group 1 Enabled. [bit 6] 252013760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 252113760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 252213760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 252313760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1E = 1; 252413531Sjairo.balart@metempsy.com } 252513531Sjairo.balart@metempsy.com 252613760Sjairo.balart@metempsy.com // vPE Group 1 Disabled. [bit 7] 252713760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 252813760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 252913760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 253013760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1D = 1; 253113760Sjairo.balart@metempsy.com } 253213760Sjairo.balart@metempsy.com 253313760Sjairo.balart@metempsy.com return ich_misr_el2; 253413531Sjairo.balart@metempsy.com} 253513531Sjairo.balart@metempsy.com 253614237Sgiacomo.travaglini@arm.comRegVal 253714237Sgiacomo.travaglini@arm.comGicv3CPUInterface::bpr1(Gicv3::GroupId group) 253814237Sgiacomo.travaglini@arm.com{ 253914237Sgiacomo.travaglini@arm.com bool hcr_imo = getHCREL2IMO(); 254014237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 254114237Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_BPR1_EL1); 254214237Sgiacomo.travaglini@arm.com } 254314237Sgiacomo.travaglini@arm.com 254414237Sgiacomo.travaglini@arm.com RegVal bpr = 0; 254514237Sgiacomo.travaglini@arm.com 254614237Sgiacomo.travaglini@arm.com if (group == Gicv3::G1S) { 254714237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 254814237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 254914237Sgiacomo.travaglini@arm.com 255014237Sgiacomo.travaglini@arm.com if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 255114237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 255214237Sgiacomo.travaglini@arm.com } else { 255314237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S); 255414237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR; 255514237Sgiacomo.travaglini@arm.com } 255614237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1NS) { 255714237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 255814237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 255914237Sgiacomo.travaglini@arm.com 256014237Sgiacomo.travaglini@arm.com // Check if EL3 is implemented and this is a non secure accesses at 256114237Sgiacomo.travaglini@arm.com // EL1 and EL2 256214237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 256314237Sgiacomo.travaglini@arm.com // Reads return BPR0 + 1 saturated to 7, WI 256414237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1; 256514237Sgiacomo.travaglini@arm.com bpr = bpr < 7 ? bpr : 7; 256614237Sgiacomo.travaglini@arm.com } else { 256714237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS); 256814237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS; 256914237Sgiacomo.travaglini@arm.com } 257014237Sgiacomo.travaglini@arm.com } else { 257114237Sgiacomo.travaglini@arm.com panic("Should be used with G1S and G1NS only\n"); 257214237Sgiacomo.travaglini@arm.com } 257314237Sgiacomo.travaglini@arm.com 257414237Sgiacomo.travaglini@arm.com return bpr; 257514237Sgiacomo.travaglini@arm.com} 257614237Sgiacomo.travaglini@arm.com 257713531Sjairo.balart@metempsy.comvoid 257813531Sjairo.balart@metempsy.comGicv3CPUInterface::serialize(CheckpointOut & cp) const 257913531Sjairo.balart@metempsy.com{ 258013531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.intid); 258113531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.prio); 258213531Sjairo.balart@metempsy.com SERIALIZE_ENUM(hppi.group); 258313531Sjairo.balart@metempsy.com} 258413531Sjairo.balart@metempsy.com 258513531Sjairo.balart@metempsy.comvoid 258613531Sjairo.balart@metempsy.comGicv3CPUInterface::unserialize(CheckpointIn & cp) 258713531Sjairo.balart@metempsy.com{ 258813531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.intid); 258913531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.prio); 259013531Sjairo.balart@metempsy.com UNSERIALIZE_ENUM(hppi.group); 259113531Sjairo.balart@metempsy.com} 2592