gic_v3_cpu_interface.cc revision 14248
113531Sjairo.balart@metempsy.com/* 214227Sgiacomo.travaglini@arm.com * Copyright (c) 2019 ARM Limited 314227Sgiacomo.travaglini@arm.com * All rights reserved 414227Sgiacomo.travaglini@arm.com * 514227Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614227Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714227Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814227Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914227Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014227Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114227Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214227Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314227Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 1513531Sjairo.balart@metempsy.com * All rights reserved. 1613531Sjairo.balart@metempsy.com * 1713531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1813531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1913531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 2013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 2113531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 2213531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2313531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2413531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2513531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2613531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913531Sjairo.balart@metempsy.com * 4013531Sjairo.balart@metempsy.com * Authors: Jairo Balart 4113531Sjairo.balart@metempsy.com */ 4213531Sjairo.balart@metempsy.com 4313531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 4413531Sjairo.balart@metempsy.com 4513531Sjairo.balart@metempsy.com#include "arch/arm/isa.hh" 4613531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 4713531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 4813531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 4913531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 5013531Sjairo.balart@metempsy.com 5113926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR; 5213926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; 5313926Sgiacomo.travaglini@arm.com 5413531Sjairo.balart@metempsy.comGicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 5513531Sjairo.balart@metempsy.com : BaseISADevice(), 5613531Sjairo.balart@metempsy.com gic(gic), 5713531Sjairo.balart@metempsy.com redistributor(nullptr), 5813531Sjairo.balart@metempsy.com distributor(nullptr), 5913531Sjairo.balart@metempsy.com cpuId(cpu_id) 6013531Sjairo.balart@metempsy.com{ 6113531Sjairo.balart@metempsy.com} 6213531Sjairo.balart@metempsy.com 6313531Sjairo.balart@metempsy.comvoid 6413531Sjairo.balart@metempsy.comGicv3CPUInterface::init() 6513531Sjairo.balart@metempsy.com{ 6613531Sjairo.balart@metempsy.com redistributor = gic->getRedistributor(cpuId); 6713531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 6813531Sjairo.balart@metempsy.com} 6913531Sjairo.balart@metempsy.com 7013531Sjairo.balart@metempsy.comvoid 7113531Sjairo.balart@metempsy.comGicv3CPUInterface::initState() 7213531Sjairo.balart@metempsy.com{ 7313531Sjairo.balart@metempsy.com reset(); 7413531Sjairo.balart@metempsy.com} 7513531Sjairo.balart@metempsy.com 7613531Sjairo.balart@metempsy.comvoid 7713531Sjairo.balart@metempsy.comGicv3CPUInterface::reset() 7813531Sjairo.balart@metempsy.com{ 7913531Sjairo.balart@metempsy.com hppi.prio = 0xff; 8013531Sjairo.balart@metempsy.com} 8113531Sjairo.balart@metempsy.com 8213826Sgiacomo.travaglini@arm.comvoid 8313826Sgiacomo.travaglini@arm.comGicv3CPUInterface::setThreadContext(ThreadContext *tc) 8413826Sgiacomo.travaglini@arm.com{ 8513826Sgiacomo.travaglini@arm.com maintenanceInterrupt = gic->params()->maint_int->get(tc); 8613826Sgiacomo.travaglini@arm.com} 8713826Sgiacomo.travaglini@arm.com 8813531Sjairo.balart@metempsy.combool 8913760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2FMO() const 9013531Sjairo.balart@metempsy.com{ 9113531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 9213531Sjairo.balart@metempsy.com 9313531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 9413531Sjairo.balart@metempsy.com return false; 9513531Sjairo.balart@metempsy.com } else if (hcr.tge) { 9613531Sjairo.balart@metempsy.com return true; 9713531Sjairo.balart@metempsy.com } else { 9813531Sjairo.balart@metempsy.com return hcr.fmo; 9913531Sjairo.balart@metempsy.com } 10013531Sjairo.balart@metempsy.com} 10113531Sjairo.balart@metempsy.com 10213531Sjairo.balart@metempsy.combool 10313760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2IMO() const 10413531Sjairo.balart@metempsy.com{ 10513531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 10613531Sjairo.balart@metempsy.com 10713531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 10813531Sjairo.balart@metempsy.com return false; 10913531Sjairo.balart@metempsy.com } else if (hcr.tge) { 11013531Sjairo.balart@metempsy.com return true; 11113531Sjairo.balart@metempsy.com } else { 11213531Sjairo.balart@metempsy.com return hcr.imo; 11313531Sjairo.balart@metempsy.com } 11413531Sjairo.balart@metempsy.com} 11513531Sjairo.balart@metempsy.com 11613580Sgabeblack@google.comRegVal 11713531Sjairo.balart@metempsy.comGicv3CPUInterface::readMiscReg(int misc_reg) 11813531Sjairo.balart@metempsy.com{ 11913580Sgabeblack@google.com RegVal value = isa->readMiscRegNoEffect(misc_reg); 12013531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 12113531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 12213531Sjairo.balart@metempsy.com 12313531Sjairo.balart@metempsy.com switch (misc_reg) { 12413760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 12513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 12613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: { 12713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 12813531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 12913531Sjairo.balart@metempsy.com } 13013531Sjairo.balart@metempsy.com 13114246Sgiacomo.travaglini@arm.com return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1); 13213531Sjairo.balart@metempsy.com } 13313531Sjairo.balart@metempsy.com 13413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 13513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 13613531Sjairo.balart@metempsy.com 13713531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 13813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 13913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 14013531Sjairo.balart@metempsy.com 14113531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 14313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 14413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14513531Sjairo.balart@metempsy.com return 0; 14613531Sjairo.balart@metempsy.com 14713760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 14813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 14913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: { 15013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 15113531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 15213531Sjairo.balart@metempsy.com } 15313531Sjairo.balart@metempsy.com 15413531Sjairo.balart@metempsy.com break; 15513531Sjairo.balart@metempsy.com } 15613531Sjairo.balart@metempsy.com 15713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 15813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 15913531Sjairo.balart@metempsy.com 16013531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 16113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 16213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 16313531Sjairo.balart@metempsy.com 16413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 16613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 16713531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16813531Sjairo.balart@metempsy.com return 0; 16913531Sjairo.balart@metempsy.com 17013760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable register EL1 17113531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 17213531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 17313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 17414057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN0_EL1); 17513531Sjairo.balart@metempsy.com } 17613531Sjairo.balart@metempsy.com 17713531Sjairo.balart@metempsy.com break; 17813531Sjairo.balart@metempsy.com } 17913531Sjairo.balart@metempsy.com 18014057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN0_EL1: { 18114057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 18214057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 18314057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG0; 18414057Sgiacomo.travaglini@arm.com break; 18514057Sgiacomo.travaglini@arm.com } 18614057Sgiacomo.travaglini@arm.com 18713760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 18813531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 18913531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 19013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 19114057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); 19213531Sjairo.balart@metempsy.com } 19313531Sjairo.balart@metempsy.com 19414247Sgiacomo.travaglini@arm.com value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1); 19513531Sjairo.balart@metempsy.com break; 19613531Sjairo.balart@metempsy.com } 19713531Sjairo.balart@metempsy.com 19814057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN1_EL1: { 19914057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 20014057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 20114057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG1; 20214057Sgiacomo.travaglini@arm.com break; 20314057Sgiacomo.travaglini@arm.com } 20414057Sgiacomo.travaglini@arm.com 20513760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL3 20613760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 20713760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: 20813739Sgiacomo.travaglini@arm.com break; 20913760Sjairo.balart@metempsy.com 21013760Sjairo.balart@metempsy.com // Running Priority Register 21113531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR: 21213531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR_EL1: { 21313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 21413760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 21513531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_RPR_EL1); 21613531Sjairo.balart@metempsy.com } 21713531Sjairo.balart@metempsy.com 21813531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 21913531Sjairo.balart@metempsy.com 22013531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 22113760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 22213760Sjairo.balart@metempsy.com // Spec section 4.8.1 22313760Sjairo.balart@metempsy.com // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 22413531Sjairo.balart@metempsy.com if ((rprio & 0x80) == 0) { 22513760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 22613760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x0 22713531Sjairo.balart@metempsy.com rprio = 0; 22813531Sjairo.balart@metempsy.com } else if (rprio != 0xff) { 22913760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 23013760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of 23113760Sjairo.balart@metempsy.com // the current value 23213531Sjairo.balart@metempsy.com rprio = (rprio << 1) & 0xff; 23313531Sjairo.balart@metempsy.com } 23413531Sjairo.balart@metempsy.com } 23513531Sjairo.balart@metempsy.com 23613531Sjairo.balart@metempsy.com value = rprio; 23713531Sjairo.balart@metempsy.com break; 23813531Sjairo.balart@metempsy.com } 23913531Sjairo.balart@metempsy.com 24013760Sjairo.balart@metempsy.com // Virtual Running Priority Register 24113531Sjairo.balart@metempsy.com case MISCREG_ICV_RPR_EL1: { 24213531Sjairo.balart@metempsy.com value = virtualHighestActivePriority(); 24313531Sjairo.balart@metempsy.com break; 24413531Sjairo.balart@metempsy.com } 24513531Sjairo.balart@metempsy.com 24613760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 0 24713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0: 24813531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0_EL1: { 24913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 25013531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 25113531Sjairo.balart@metempsy.com } 25213531Sjairo.balart@metempsy.com 25313531Sjairo.balart@metempsy.com value = getHPPIR0(); 25413531Sjairo.balart@metempsy.com break; 25513531Sjairo.balart@metempsy.com } 25613531Sjairo.balart@metempsy.com 25713760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 0 25813531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR0_EL1: { 25913531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 26013531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 26113531Sjairo.balart@metempsy.com 26213531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 26313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 26413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 26513531Sjairo.balart@metempsy.com Gicv3::GroupId group = 26613760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 26713531Sjairo.balart@metempsy.com 26813531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 26913760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 27013531Sjairo.balart@metempsy.com } 27113531Sjairo.balart@metempsy.com } 27213531Sjairo.balart@metempsy.com 27313531Sjairo.balart@metempsy.com break; 27413531Sjairo.balart@metempsy.com } 27513531Sjairo.balart@metempsy.com 27613760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 1 27713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1: 27813531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1_EL1: { 27913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 28013531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 28113531Sjairo.balart@metempsy.com } 28213531Sjairo.balart@metempsy.com 28313531Sjairo.balart@metempsy.com value = getHPPIR1(); 28413531Sjairo.balart@metempsy.com break; 28513531Sjairo.balart@metempsy.com } 28613531Sjairo.balart@metempsy.com 28713760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 1 28813531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR1_EL1: { 28913531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 29013531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 29113531Sjairo.balart@metempsy.com 29213531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 29313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 29413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 29513531Sjairo.balart@metempsy.com Gicv3::GroupId group = 29613760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 29713531Sjairo.balart@metempsy.com 29813531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 29913760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 30013531Sjairo.balart@metempsy.com } 30113531Sjairo.balart@metempsy.com } 30213531Sjairo.balart@metempsy.com 30313531Sjairo.balart@metempsy.com break; 30413531Sjairo.balart@metempsy.com } 30513531Sjairo.balart@metempsy.com 30613760Sjairo.balart@metempsy.com // Binary Point Register 0 30713531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 30814237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 30913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 31013531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR0_EL1); 31113531Sjairo.balart@metempsy.com } 31213531Sjairo.balart@metempsy.com 31314237Sgiacomo.travaglini@arm.com value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 31414237Sgiacomo.travaglini@arm.com break; 31514237Sgiacomo.travaglini@arm.com } 31613531Sjairo.balart@metempsy.com 31713760Sjairo.balart@metempsy.com // Binary Point Register 1 31813531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 31913760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 32014237Sgiacomo.travaglini@arm.com value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS); 32114237Sgiacomo.travaglini@arm.com break; 32213760Sjairo.balart@metempsy.com } 32313760Sjairo.balart@metempsy.com 32414237Sgiacomo.travaglini@arm.com // Virtual Binary Point Register 0 32514237Sgiacomo.travaglini@arm.com case MISCREG_ICV_BPR0_EL1: { 32614237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 32714237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 32814237Sgiacomo.travaglini@arm.com 32914237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0; 33014237Sgiacomo.travaglini@arm.com break; 33114237Sgiacomo.travaglini@arm.com } 33214237Sgiacomo.travaglini@arm.com 33313760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 33413531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 33514237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 33614237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 33714237Sgiacomo.travaglini@arm.com 33814237Sgiacomo.travaglini@arm.com if (ich_vmcr_el2.VCBPR) { 33914237Sgiacomo.travaglini@arm.com // bpr0 + 1 saturated to 7, WI 34014237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0 + 1; 34114237Sgiacomo.travaglini@arm.com value = value < 7 ? value : 7; 34214237Sgiacomo.travaglini@arm.com } else { 34314237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR1; 34414237Sgiacomo.travaglini@arm.com } 34514237Sgiacomo.travaglini@arm.com 34614237Sgiacomo.travaglini@arm.com break; 34713531Sjairo.balart@metempsy.com } 34813531Sjairo.balart@metempsy.com 34913760Sjairo.balart@metempsy.com // Interrupt Priority Mask Register 35013531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 35113760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: 35213760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 35314057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_PMR_EL1); 35413531Sjairo.balart@metempsy.com } 35513531Sjairo.balart@metempsy.com 35613531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 35713760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 35813760Sjairo.balart@metempsy.com // Spec section 4.8.1 35913760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: 36013531Sjairo.balart@metempsy.com if ((value & 0x80) == 0) { 36113760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 36213760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x00. 36313531Sjairo.balart@metempsy.com value = 0; 36413531Sjairo.balart@metempsy.com } else if (value != 0xff) { 36513760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 36613760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of the 36713760Sjairo.balart@metempsy.com // current value. 36813531Sjairo.balart@metempsy.com value = (value << 1) & 0xff; 36913531Sjairo.balart@metempsy.com } 37013531Sjairo.balart@metempsy.com } 37113531Sjairo.balart@metempsy.com 37213531Sjairo.balart@metempsy.com break; 37313531Sjairo.balart@metempsy.com 37414057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 37514057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 37614057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 37714057Sgiacomo.travaglini@arm.com 37814057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VPMR; 37914057Sgiacomo.travaglini@arm.com break; 38014057Sgiacomo.travaglini@arm.com } 38114057Sgiacomo.travaglini@arm.com 38213760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 0 38313531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0: 38413760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0_EL1: { 38513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 38613531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR0_EL1); 38713531Sjairo.balart@metempsy.com } 38813531Sjairo.balart@metempsy.com 38913531Sjairo.balart@metempsy.com uint32_t int_id; 39013531Sjairo.balart@metempsy.com 39113531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 39213531Sjairo.balart@metempsy.com int_id = getHPPIR0(); 39313531Sjairo.balart@metempsy.com 39413531Sjairo.balart@metempsy.com // avoid activation for special interrupts 39513923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 39613923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 39713531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 39813531Sjairo.balart@metempsy.com } 39913531Sjairo.balart@metempsy.com } else { 40013531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 40113531Sjairo.balart@metempsy.com } 40213531Sjairo.balart@metempsy.com 40313531Sjairo.balart@metempsy.com value = int_id; 40413531Sjairo.balart@metempsy.com break; 40513531Sjairo.balart@metempsy.com } 40613531Sjairo.balart@metempsy.com 40713760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 0 40813531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR0_EL1: { 40913531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 41013531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 41113531Sjairo.balart@metempsy.com 41213531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 41313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 41413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 41513531Sjairo.balart@metempsy.com 41613760Sjairo.balart@metempsy.com if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 41713760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 41813531Sjairo.balart@metempsy.com 41913531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 42013760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 42113531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 42213531Sjairo.balart@metempsy.com } else { 42313531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 42413531Sjairo.balart@metempsy.com // - Move from pending to invalid... 42513531Sjairo.balart@metempsy.com // - Return de bogus id... 42613760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 42713531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 42813760Sjairo.balart@metempsy.com ich_lr_el2); 42913531Sjairo.balart@metempsy.com } 43013531Sjairo.balart@metempsy.com } 43113531Sjairo.balart@metempsy.com } 43213531Sjairo.balart@metempsy.com 43313531Sjairo.balart@metempsy.com value = int_id; 43413531Sjairo.balart@metempsy.com virtualUpdate(); 43513531Sjairo.balart@metempsy.com break; 43613531Sjairo.balart@metempsy.com } 43713531Sjairo.balart@metempsy.com 43813760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 1 43913531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1: 44013760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1_EL1: { 44113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 44213531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR1_EL1); 44313531Sjairo.balart@metempsy.com } 44413531Sjairo.balart@metempsy.com 44513531Sjairo.balart@metempsy.com uint32_t int_id; 44613531Sjairo.balart@metempsy.com 44713531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 44813531Sjairo.balart@metempsy.com int_id = getHPPIR1(); 44913531Sjairo.balart@metempsy.com 45013531Sjairo.balart@metempsy.com // avoid activation for special interrupts 45113923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 45213923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 45313531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 45413531Sjairo.balart@metempsy.com } 45513531Sjairo.balart@metempsy.com } else { 45613531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 45713531Sjairo.balart@metempsy.com } 45813531Sjairo.balart@metempsy.com 45913531Sjairo.balart@metempsy.com value = int_id; 46013531Sjairo.balart@metempsy.com break; 46113531Sjairo.balart@metempsy.com } 46213531Sjairo.balart@metempsy.com 46313760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 1 46413531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR1_EL1: { 46513531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 46613531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 46713531Sjairo.balart@metempsy.com 46813531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 46913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 47013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 47113531Sjairo.balart@metempsy.com 47213760Sjairo.balart@metempsy.com if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 47313760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 47413531Sjairo.balart@metempsy.com 47513531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 47613760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 47713531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 47813531Sjairo.balart@metempsy.com } else { 47913531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 48013531Sjairo.balart@metempsy.com // - Move from pending to invalid... 48113531Sjairo.balart@metempsy.com // - Return de bogus id... 48213760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 48313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 48413760Sjairo.balart@metempsy.com ich_lr_el2); 48513531Sjairo.balart@metempsy.com } 48613531Sjairo.balart@metempsy.com } 48713531Sjairo.balart@metempsy.com } 48813531Sjairo.balart@metempsy.com 48913531Sjairo.balart@metempsy.com value = int_id; 49013531Sjairo.balart@metempsy.com virtualUpdate(); 49113531Sjairo.balart@metempsy.com break; 49213531Sjairo.balart@metempsy.com } 49313531Sjairo.balart@metempsy.com 49413760Sjairo.balart@metempsy.com // System Register Enable Register EL1 49513531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 49613760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: { 49713531Sjairo.balart@metempsy.com /* 49813531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 49913531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 50013531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 50113531Sjairo.balart@metempsy.com */ 50213760Sjairo.balart@metempsy.com ICC_SRE_EL1 icc_sre_el1 = 0; 50313760Sjairo.balart@metempsy.com icc_sre_el1.SRE = 1; 50413760Sjairo.balart@metempsy.com icc_sre_el1.DIB = 1; 50513760Sjairo.balart@metempsy.com icc_sre_el1.DFB = 1; 50613760Sjairo.balart@metempsy.com value = icc_sre_el1; 50713760Sjairo.balart@metempsy.com break; 50813760Sjairo.balart@metempsy.com } 50913760Sjairo.balart@metempsy.com 51013760Sjairo.balart@metempsy.com // System Register Enable Register EL2 51113760Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 51213760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: { 51313531Sjairo.balart@metempsy.com /* 51413531Sjairo.balart@metempsy.com * Enable [3] == 1 51513760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) 51613531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 51713531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 51813531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 51913531Sjairo.balart@metempsy.com */ 52013760Sjairo.balart@metempsy.com ICC_SRE_EL2 icc_sre_el2 = 0; 52113760Sjairo.balart@metempsy.com icc_sre_el2.SRE = 1; 52213760Sjairo.balart@metempsy.com icc_sre_el2.DIB = 1; 52313760Sjairo.balart@metempsy.com icc_sre_el2.DFB = 1; 52413760Sjairo.balart@metempsy.com icc_sre_el2.Enable = 1; 52513760Sjairo.balart@metempsy.com value = icc_sre_el2; 52613531Sjairo.balart@metempsy.com break; 52713760Sjairo.balart@metempsy.com } 52813760Sjairo.balart@metempsy.com 52913760Sjairo.balart@metempsy.com // System Register Enable Register EL3 53013760Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 53113760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: { 53213760Sjairo.balart@metempsy.com /* 53313760Sjairo.balart@metempsy.com * Enable [3] == 1 53413760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 53513760Sjairo.balart@metempsy.com * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 53613760Sjairo.balart@metempsy.com * RAO/WI) 53713760Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 53813760Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 53913760Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 54013760Sjairo.balart@metempsy.com */ 54113760Sjairo.balart@metempsy.com ICC_SRE_EL3 icc_sre_el3 = 0; 54213760Sjairo.balart@metempsy.com icc_sre_el3.SRE = 1; 54313760Sjairo.balart@metempsy.com icc_sre_el3.DIB = 1; 54413760Sjairo.balart@metempsy.com icc_sre_el3.DFB = 1; 54513760Sjairo.balart@metempsy.com icc_sre_el3.Enable = 1; 54613760Sjairo.balart@metempsy.com value = icc_sre_el3; 54713760Sjairo.balart@metempsy.com break; 54813760Sjairo.balart@metempsy.com } 54913760Sjairo.balart@metempsy.com 55013760Sjairo.balart@metempsy.com // Control Register 55113531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 55213760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 55313760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 55413531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_CTLR_EL1); 55513531Sjairo.balart@metempsy.com } 55613531Sjairo.balart@metempsy.com 55714245Sgiacomo.travaglini@arm.com value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1); 55813760Sjairo.balart@metempsy.com // Enforce value for RO bits 55913760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 56013760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 56113760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 56213760Sjairo.balart@metempsy.com // generation System registers 56313760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 56413531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 56513531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 56613760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = value; 56713760Sjairo.balart@metempsy.com icc_ctlr_el1.ExtRange = 0; 56813760Sjairo.balart@metempsy.com icc_ctlr_el1.RSS = 1; 56913760Sjairo.balart@metempsy.com icc_ctlr_el1.A3V = 1; 57013760Sjairo.balart@metempsy.com icc_ctlr_el1.SEIS = 0; 57113760Sjairo.balart@metempsy.com icc_ctlr_el1.IDbits = 1; 57213760Sjairo.balart@metempsy.com icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 57313760Sjairo.balart@metempsy.com value = icc_ctlr_el1; 57413531Sjairo.balart@metempsy.com break; 57513531Sjairo.balart@metempsy.com } 57613531Sjairo.balart@metempsy.com 57713760Sjairo.balart@metempsy.com // Virtual Control Register 57813531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 57913760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = value; 58013760Sjairo.balart@metempsy.com icv_ctlr_el1.RSS = 0; 58113760Sjairo.balart@metempsy.com icv_ctlr_el1.A3V = 1; 58213760Sjairo.balart@metempsy.com icv_ctlr_el1.SEIS = 0; 58313760Sjairo.balart@metempsy.com icv_ctlr_el1.IDbits = 1; 58413760Sjairo.balart@metempsy.com icv_ctlr_el1.PRIbits = 7; 58513760Sjairo.balart@metempsy.com value = icv_ctlr_el1; 58613531Sjairo.balart@metempsy.com break; 58713531Sjairo.balart@metempsy.com } 58813531Sjairo.balart@metempsy.com 58913760Sjairo.balart@metempsy.com // Control Register 59013531Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 59113531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 59213760Sjairo.balart@metempsy.com // Enforce value for RO bits 59313760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 59413760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 59513760Sjairo.balart@metempsy.com // nDS [17], supports disabling of security 59613760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 59713760Sjairo.balart@metempsy.com // generation System registers 59813760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 59913531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 60013531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 60113760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = value; 60213760Sjairo.balart@metempsy.com icc_ctlr_el3.ExtRange = 0; 60313760Sjairo.balart@metempsy.com icc_ctlr_el3.RSS = 1; 60413760Sjairo.balart@metempsy.com icc_ctlr_el3.nDS = 0; 60513760Sjairo.balart@metempsy.com icc_ctlr_el3.A3V = 1; 60613760Sjairo.balart@metempsy.com icc_ctlr_el3.SEIS = 0; 60713760Sjairo.balart@metempsy.com icc_ctlr_el3.IDbits = 0; 60813760Sjairo.balart@metempsy.com icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 60913760Sjairo.balart@metempsy.com value = icc_ctlr_el3; 61013531Sjairo.balart@metempsy.com break; 61113531Sjairo.balart@metempsy.com } 61213531Sjairo.balart@metempsy.com 61313760Sjairo.balart@metempsy.com // Hyp Control Register 61413531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 61513531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: 61613531Sjairo.balart@metempsy.com break; 61713531Sjairo.balart@metempsy.com 61813760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 61913531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0: 62013531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2: 62113531Sjairo.balart@metempsy.com break; 62213531Sjairo.balart@metempsy.com 62314236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 62414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 62514236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 62614236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 62714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 62814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 62914236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 63014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 63114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 63214236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 63314236Sgiacomo.travaglini@arm.com return 0; 63414236Sgiacomo.travaglini@arm.com 63513760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 63613531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0: 63713531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2: 63813531Sjairo.balart@metempsy.com break; 63913531Sjairo.balart@metempsy.com 64014236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 64114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 64214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 64314236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 64414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 64514236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 64614236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 64714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 64814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 64914236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 65014236Sgiacomo.travaglini@arm.com return 0; 65114236Sgiacomo.travaglini@arm.com 65213760Sjairo.balart@metempsy.com // Maintenance Interrupt State Register 65313531Sjairo.balart@metempsy.com case MISCREG_ICH_MISR: 65413760Sjairo.balart@metempsy.com case MISCREG_ICH_MISR_EL2: 65513760Sjairo.balart@metempsy.com value = maintenanceInterruptStatus(); 65613760Sjairo.balart@metempsy.com break; 65713760Sjairo.balart@metempsy.com 65813760Sjairo.balart@metempsy.com // VGIC Type Register 65913760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR: 66013760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR_EL2: { 66113760Sjairo.balart@metempsy.com ICH_VTR_EL2 ich_vtr_el2 = value; 66213760Sjairo.balart@metempsy.com 66313760Sjairo.balart@metempsy.com ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 66413760Sjairo.balart@metempsy.com ich_vtr_el2.A3V = 1; 66513760Sjairo.balart@metempsy.com ich_vtr_el2.IDbits = 1; 66613760Sjairo.balart@metempsy.com ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 66713760Sjairo.balart@metempsy.com ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; 66813760Sjairo.balart@metempsy.com 66913760Sjairo.balart@metempsy.com value = ich_vtr_el2; 67013760Sjairo.balart@metempsy.com break; 67113531Sjairo.balart@metempsy.com } 67213531Sjairo.balart@metempsy.com 67313760Sjairo.balart@metempsy.com // End of Interrupt Status Register 67413531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR: 67513531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR_EL2: 67613760Sjairo.balart@metempsy.com value = eoiMaintenanceInterruptStatus(); 67713531Sjairo.balart@metempsy.com break; 67813531Sjairo.balart@metempsy.com 67913760Sjairo.balart@metempsy.com // Empty List Register Status Register 68013531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR: 68113531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR_EL2: 68213531Sjairo.balart@metempsy.com value = 0; 68313531Sjairo.balart@metempsy.com 68413531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 68513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 68613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 68713531Sjairo.balart@metempsy.com 68813760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 68913760Sjairo.balart@metempsy.com (ich_lr_el2.HW || !ich_lr_el2.EOI)) { 69013531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 69113531Sjairo.balart@metempsy.com } 69213531Sjairo.balart@metempsy.com } 69313531Sjairo.balart@metempsy.com 69413531Sjairo.balart@metempsy.com break; 69513531Sjairo.balart@metempsy.com 69613760Sjairo.balart@metempsy.com // List Registers 69713531Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 69813531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 69913531Sjairo.balart@metempsy.com value = value >> 32; 70013531Sjairo.balart@metempsy.com break; 70113531Sjairo.balart@metempsy.com 70213760Sjairo.balart@metempsy.com // List Registers 70313531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 70413531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 70513531Sjairo.balart@metempsy.com value = value & 0xffffffff; 70613531Sjairo.balart@metempsy.com break; 70713531Sjairo.balart@metempsy.com 70813760Sjairo.balart@metempsy.com // List Registers 70913531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 71013531Sjairo.balart@metempsy.com break; 71113531Sjairo.balart@metempsy.com 71213760Sjairo.balart@metempsy.com // Virtual Machine Control Register 71313531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 71413531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: 71513531Sjairo.balart@metempsy.com break; 71613531Sjairo.balart@metempsy.com 71713531Sjairo.balart@metempsy.com default: 71813760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 71913760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 72013531Sjairo.balart@metempsy.com } 72113531Sjairo.balart@metempsy.com 72213760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 72313760Sjairo.balart@metempsy.com miscRegName[misc_reg], value); 72413531Sjairo.balart@metempsy.com return value; 72513531Sjairo.balart@metempsy.com} 72613531Sjairo.balart@metempsy.com 72713531Sjairo.balart@metempsy.comvoid 72813580Sgabeblack@google.comGicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 72913531Sjairo.balart@metempsy.com{ 73013531Sjairo.balart@metempsy.com bool do_virtual_update = false; 73113760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 73213760Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 73313531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 73413531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 73513531Sjairo.balart@metempsy.com 73613531Sjairo.balart@metempsy.com switch (misc_reg) { 73713760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 73813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 73913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: 74013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 74113531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 74213531Sjairo.balart@metempsy.com } 74313531Sjairo.balart@metempsy.com 74414246Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val); 74514246Sgiacomo.travaglini@arm.com return; 74613531Sjairo.balart@metempsy.com 74713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 74813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 74913531Sjairo.balart@metempsy.com 75013531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 75113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 75213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 75313531Sjairo.balart@metempsy.com 75413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 75513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 75613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 75713531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 75813531Sjairo.balart@metempsy.com break; 75913531Sjairo.balart@metempsy.com 76013760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 76113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 76213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: 76313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 76413531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 76513531Sjairo.balart@metempsy.com } 76613531Sjairo.balart@metempsy.com 76713531Sjairo.balart@metempsy.com break; 76813531Sjairo.balart@metempsy.com 76913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 77013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 77113531Sjairo.balart@metempsy.com 77213531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 77313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 77413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 77513531Sjairo.balart@metempsy.com 77613531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 77713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 77813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 77913531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 78013531Sjairo.balart@metempsy.com break; 78113531Sjairo.balart@metempsy.com 78213760Sjairo.balart@metempsy.com // End Of Interrupt Register 0 78313531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0: 78413531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 78513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 78613531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 78713531Sjairo.balart@metempsy.com } 78813531Sjairo.balart@metempsy.com 78913531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 79013531Sjairo.balart@metempsy.com 79113531Sjairo.balart@metempsy.com // avoid activation for special interrupts 79213923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 79313923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 79413531Sjairo.balart@metempsy.com return; 79513531Sjairo.balart@metempsy.com } 79613531Sjairo.balart@metempsy.com 79713531Sjairo.balart@metempsy.com Gicv3::GroupId group = Gicv3::G0S; 79813531Sjairo.balart@metempsy.com 79913531Sjairo.balart@metempsy.com if (highestActiveGroup() != group) { 80013531Sjairo.balart@metempsy.com return; 80113531Sjairo.balart@metempsy.com } 80213531Sjairo.balart@metempsy.com 80313531Sjairo.balart@metempsy.com dropPriority(group); 80413531Sjairo.balart@metempsy.com 80513531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 80613531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 80713531Sjairo.balart@metempsy.com } 80813531Sjairo.balart@metempsy.com 80913531Sjairo.balart@metempsy.com break; 81013531Sjairo.balart@metempsy.com } 81113531Sjairo.balart@metempsy.com 81213760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 0 81313531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR0_EL1: { 81413531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 81513531Sjairo.balart@metempsy.com 81613531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 81713531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 81813531Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 81913531Sjairo.balart@metempsy.com return; 82013531Sjairo.balart@metempsy.com } 82113531Sjairo.balart@metempsy.com 82213531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 82313531Sjairo.balart@metempsy.com 82413531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 82513531Sjairo.balart@metempsy.com return; 82613531Sjairo.balart@metempsy.com } 82713531Sjairo.balart@metempsy.com 82813531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 82913531Sjairo.balart@metempsy.com 83013531Sjairo.balart@metempsy.com if (lr_idx < 0) { 83113531Sjairo.balart@metempsy.com // No LR found matching 83213531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 83313531Sjairo.balart@metempsy.com } else { 83413760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 83513531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 83613531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 83713760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 83813760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 83913531Sjairo.balart@metempsy.com 84013531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) { 84113760Sjairo.balart@metempsy.com //if (!virtualIsEOISplitMode()) 84213531Sjairo.balart@metempsy.com { 84313531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 84413531Sjairo.balart@metempsy.com } 84513531Sjairo.balart@metempsy.com } 84613531Sjairo.balart@metempsy.com } 84713531Sjairo.balart@metempsy.com 84813531Sjairo.balart@metempsy.com virtualUpdate(); 84913531Sjairo.balart@metempsy.com break; 85013531Sjairo.balart@metempsy.com } 85113531Sjairo.balart@metempsy.com 85213760Sjairo.balart@metempsy.com // End Of Interrupt Register 1 85313531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1: 85413760Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1_EL1: { 85513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 85613531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 85713531Sjairo.balart@metempsy.com } 85813531Sjairo.balart@metempsy.com 85913531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 86013531Sjairo.balart@metempsy.com 86113531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 86213923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 86313923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 86413531Sjairo.balart@metempsy.com return; 86513531Sjairo.balart@metempsy.com } 86613531Sjairo.balart@metempsy.com 86713760Sjairo.balart@metempsy.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 86813531Sjairo.balart@metempsy.com 86913531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G0S) { 87013531Sjairo.balart@metempsy.com return; 87113531Sjairo.balart@metempsy.com } 87213531Sjairo.balart@metempsy.com 87313531Sjairo.balart@metempsy.com if (distributor->DS == 0) { 87413531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 87513531Sjairo.balart@metempsy.com return; 87613531Sjairo.balart@metempsy.com } else if (highestActiveGroup() == Gicv3::G1NS && 87713760Sjairo.balart@metempsy.com !(!inSecureState() or (currEL() == EL3))) { 87813531Sjairo.balart@metempsy.com return; 87913531Sjairo.balart@metempsy.com } 88013531Sjairo.balart@metempsy.com } 88113531Sjairo.balart@metempsy.com 88213531Sjairo.balart@metempsy.com dropPriority(group); 88313531Sjairo.balart@metempsy.com 88413531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 88513531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 88613531Sjairo.balart@metempsy.com } 88713531Sjairo.balart@metempsy.com 88813531Sjairo.balart@metempsy.com break; 88913531Sjairo.balart@metempsy.com } 89013531Sjairo.balart@metempsy.com 89113760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 1 89213531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR1_EL1: { 89313531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 89413531Sjairo.balart@metempsy.com 89513531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 89613531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 89713760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 89813531Sjairo.balart@metempsy.com return; 89913531Sjairo.balart@metempsy.com } 90013531Sjairo.balart@metempsy.com 90113531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 90213531Sjairo.balart@metempsy.com 90313531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 90413531Sjairo.balart@metempsy.com return; 90513531Sjairo.balart@metempsy.com } 90613531Sjairo.balart@metempsy.com 90713531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 90813531Sjairo.balart@metempsy.com 90913531Sjairo.balart@metempsy.com if (lr_idx < 0) { 91013760Sjairo.balart@metempsy.com // No matching LR found 91113531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 91213531Sjairo.balart@metempsy.com } else { 91313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 91413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 91513531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 91613760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 91713760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 91813531Sjairo.balart@metempsy.com 91913531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 92013531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 92113531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 92213531Sjairo.balart@metempsy.com } 92313531Sjairo.balart@metempsy.com } 92413531Sjairo.balart@metempsy.com } 92513531Sjairo.balart@metempsy.com 92613531Sjairo.balart@metempsy.com virtualUpdate(); 92713531Sjairo.balart@metempsy.com break; 92813531Sjairo.balart@metempsy.com } 92913531Sjairo.balart@metempsy.com 93013760Sjairo.balart@metempsy.com // Deactivate Interrupt Register 93113531Sjairo.balart@metempsy.com case MISCREG_ICC_DIR: 93213760Sjairo.balart@metempsy.com case MISCREG_ICC_DIR_EL1: { 93313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 93413760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 93513531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_DIR_EL1, val); 93613531Sjairo.balart@metempsy.com } 93713531Sjairo.balart@metempsy.com 93813531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 93913531Sjairo.balart@metempsy.com 94013760Sjairo.balart@metempsy.com // The following checks are as per spec pseudocode 94113760Sjairo.balart@metempsy.com // aarch64/support/ICC_DIR_EL1 94213760Sjairo.balart@metempsy.com 94313760Sjairo.balart@metempsy.com // Check for spurious ID 94413531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE) { 94513531Sjairo.balart@metempsy.com return; 94613531Sjairo.balart@metempsy.com } 94713531Sjairo.balart@metempsy.com 94813760Sjairo.balart@metempsy.com // EOI mode is not set, so don't deactivate 94913531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 95013531Sjairo.balart@metempsy.com return; 95113531Sjairo.balart@metempsy.com } 95213531Sjairo.balart@metempsy.com 95313531Sjairo.balart@metempsy.com Gicv3::GroupId group = 95413531Sjairo.balart@metempsy.com int_id >= 32 ? distributor->getIntGroup(int_id) : 95513531Sjairo.balart@metempsy.com redistributor->getIntGroup(int_id); 95613531Sjairo.balart@metempsy.com bool irq_is_grp0 = group == Gicv3::G0S; 95713531Sjairo.balart@metempsy.com bool single_sec_state = distributor->DS; 95813531Sjairo.balart@metempsy.com bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 95913531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 96013531Sjairo.balart@metempsy.com bool route_fiq_to_el3 = scr_el3.fiq; 96113531Sjairo.balart@metempsy.com bool route_irq_to_el3 = scr_el3.irq; 96213531Sjairo.balart@metempsy.com bool route_fiq_to_el2 = hcr_fmo; 96313531Sjairo.balart@metempsy.com bool route_irq_to_el2 = hcr_imo; 96413531Sjairo.balart@metempsy.com 96513531Sjairo.balart@metempsy.com switch (currEL()) { 96613531Sjairo.balart@metempsy.com case EL3: 96713531Sjairo.balart@metempsy.com break; 96813531Sjairo.balart@metempsy.com 96913531Sjairo.balart@metempsy.com case EL2: 97013531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 97113531Sjairo.balart@metempsy.com break; 97213531Sjairo.balart@metempsy.com } 97313531Sjairo.balart@metempsy.com 97413531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 97513531Sjairo.balart@metempsy.com break; 97613531Sjairo.balart@metempsy.com } 97713531Sjairo.balart@metempsy.com 97813531Sjairo.balart@metempsy.com return; 97913531Sjairo.balart@metempsy.com 98013531Sjairo.balart@metempsy.com case EL1: 98113531Sjairo.balart@metempsy.com if (!isSecureBelowEL3()) { 98213531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && 98313760Sjairo.balart@metempsy.com !route_fiq_to_el3 && !route_fiq_to_el2) { 98413531Sjairo.balart@metempsy.com break; 98513531Sjairo.balart@metempsy.com } 98613531Sjairo.balart@metempsy.com 98713531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && 98813760Sjairo.balart@metempsy.com !route_irq_to_el3 && !route_irq_to_el2) { 98913531Sjairo.balart@metempsy.com break; 99013531Sjairo.balart@metempsy.com } 99113531Sjairo.balart@metempsy.com } else { 99213531Sjairo.balart@metempsy.com if (irq_is_grp0 && !route_fiq_to_el3) { 99313531Sjairo.balart@metempsy.com break; 99413531Sjairo.balart@metempsy.com } 99513531Sjairo.balart@metempsy.com 99613531Sjairo.balart@metempsy.com if (!irq_is_grp0 && 99713760Sjairo.balart@metempsy.com (!irq_is_secure || !single_sec_state) && 99813760Sjairo.balart@metempsy.com !route_irq_to_el3) { 99913531Sjairo.balart@metempsy.com break; 100013531Sjairo.balart@metempsy.com } 100113531Sjairo.balart@metempsy.com } 100213531Sjairo.balart@metempsy.com 100313531Sjairo.balart@metempsy.com return; 100413531Sjairo.balart@metempsy.com 100513531Sjairo.balart@metempsy.com default: 100613531Sjairo.balart@metempsy.com break; 100713531Sjairo.balart@metempsy.com } 100813531Sjairo.balart@metempsy.com 100913531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 101013531Sjairo.balart@metempsy.com break; 101113531Sjairo.balart@metempsy.com } 101213531Sjairo.balart@metempsy.com 101313760Sjairo.balart@metempsy.com // Deactivate Virtual Interrupt Register 101413531Sjairo.balart@metempsy.com case MISCREG_ICV_DIR_EL1: { 101513531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 101613531Sjairo.balart@metempsy.com 101713531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 101813531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 101913760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 102013531Sjairo.balart@metempsy.com return; 102113531Sjairo.balart@metempsy.com } 102213531Sjairo.balart@metempsy.com 102313531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 102413531Sjairo.balart@metempsy.com return; 102513531Sjairo.balart@metempsy.com } 102613531Sjairo.balart@metempsy.com 102713531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 102813531Sjairo.balart@metempsy.com 102913531Sjairo.balart@metempsy.com if (lr_idx < 0) { 103013760Sjairo.balart@metempsy.com // No matching LR found 103113531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 103213531Sjairo.balart@metempsy.com } else { 103313531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 103413531Sjairo.balart@metempsy.com } 103513531Sjairo.balart@metempsy.com 103613531Sjairo.balart@metempsy.com virtualUpdate(); 103713531Sjairo.balart@metempsy.com break; 103813531Sjairo.balart@metempsy.com } 103913531Sjairo.balart@metempsy.com 104013760Sjairo.balart@metempsy.com // Binary Point Register 0 104113531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 104214237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 104314237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 104414237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 104514237Sgiacomo.travaglini@arm.com } 104614237Sgiacomo.travaglini@arm.com break; 104714237Sgiacomo.travaglini@arm.com } 104813760Sjairo.balart@metempsy.com // Binary Point Register 1 104913531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 105013760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 105114237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 105214237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 105314237Sgiacomo.travaglini@arm.com } 105414237Sgiacomo.travaglini@arm.com 105514237Sgiacomo.travaglini@arm.com val &= 0x7; 105614237Sgiacomo.travaglini@arm.com 105714237Sgiacomo.travaglini@arm.com if (isSecureBelowEL3()) { 105814237Sgiacomo.travaglini@arm.com // group == Gicv3::G1S 105914237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 106014237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 106114237Sgiacomo.travaglini@arm.com 106214237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR; 106314237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 106414237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val); 106514237Sgiacomo.travaglini@arm.com } else { 106614237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val); 106714237Sgiacomo.travaglini@arm.com } 106814237Sgiacomo.travaglini@arm.com return; 106914237Sgiacomo.travaglini@arm.com } else { 107014237Sgiacomo.travaglini@arm.com // group == Gicv3::G1NS 107114237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 107214237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 107314237Sgiacomo.travaglini@arm.com 107414237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS; 107514237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 107614237Sgiacomo.travaglini@arm.com // Non secure writes from EL1 and EL2 are ignored 107714237Sgiacomo.travaglini@arm.com } else { 107814237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val); 107914237Sgiacomo.travaglini@arm.com } 108014237Sgiacomo.travaglini@arm.com return; 108114237Sgiacomo.travaglini@arm.com } 108214237Sgiacomo.travaglini@arm.com 108314237Sgiacomo.travaglini@arm.com break; 108413531Sjairo.balart@metempsy.com } 108513531Sjairo.balart@metempsy.com 108613760Sjairo.balart@metempsy.com // Virtual Binary Point Register 0 108713531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 108813760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 108913531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 109013531Sjairo.balart@metempsy.com Gicv3::GroupId group = 109113531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 109213760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 109313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 109413531Sjairo.balart@metempsy.com 109513760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 109613760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 109713531Sjairo.balart@metempsy.com return; 109813531Sjairo.balart@metempsy.com } 109913531Sjairo.balart@metempsy.com 110013531Sjairo.balart@metempsy.com uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 110113531Sjairo.balart@metempsy.com 110213531Sjairo.balart@metempsy.com if (group != Gicv3::G0S) { 110313531Sjairo.balart@metempsy.com min_VPBR++; 110413531Sjairo.balart@metempsy.com } 110513531Sjairo.balart@metempsy.com 110613531Sjairo.balart@metempsy.com if (val < min_VPBR) { 110713531Sjairo.balart@metempsy.com val = min_VPBR; 110813531Sjairo.balart@metempsy.com } 110913531Sjairo.balart@metempsy.com 111013531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 111113760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = val; 111213531Sjairo.balart@metempsy.com } else { 111313760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = val; 111413531Sjairo.balart@metempsy.com } 111513531Sjairo.balart@metempsy.com 111613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 111713531Sjairo.balart@metempsy.com do_virtual_update = true; 111813531Sjairo.balart@metempsy.com break; 111913531Sjairo.balart@metempsy.com } 112013531Sjairo.balart@metempsy.com 112113760Sjairo.balart@metempsy.com // Control Register EL1 112213531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 112313760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 112413760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 112513531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 112613531Sjairo.balart@metempsy.com } 112713531Sjairo.balart@metempsy.com 112813531Sjairo.balart@metempsy.com /* 112913760Sjairo.balart@metempsy.com * ExtRange is RO. 113013531Sjairo.balart@metempsy.com * RSS is RO. 113113531Sjairo.balart@metempsy.com * A3V is RO. 113213531Sjairo.balart@metempsy.com * SEIS is RO. 113313531Sjairo.balart@metempsy.com * IDbits is RO. 113413531Sjairo.balart@metempsy.com * PRIbits is RO. 113513531Sjairo.balart@metempsy.com */ 113613760Sjairo.balart@metempsy.com ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 113713760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 113814245Sgiacomo.travaglini@arm.com readBankedMiscReg(MISCREG_ICC_CTLR_EL1); 113913760Sjairo.balart@metempsy.com 114013760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 114113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 114213760Sjairo.balart@metempsy.com 114313760Sjairo.balart@metempsy.com // The following could be refactored but it is following 114413760Sjairo.balart@metempsy.com // spec description section 9.2.6 point by point. 114513760Sjairo.balart@metempsy.com 114613760Sjairo.balart@metempsy.com // PMHE 114713760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 114813760Sjairo.balart@metempsy.com // PMHE is alias of ICC_CTLR_EL3.PMHE 114913760Sjairo.balart@metempsy.com 115013760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 115113760Sjairo.balart@metempsy.com // PMHE is RO 115213760Sjairo.balart@metempsy.com } else if (distributor->DS == 1) { 115313760Sjairo.balart@metempsy.com // PMHE is RW 115413760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 115513760Sjairo.balart@metempsy.com icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 115613760Sjairo.balart@metempsy.com } 115713531Sjairo.balart@metempsy.com } else { 115813760Sjairo.balart@metempsy.com // PMHE is RW (by implementation choice) 115913760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 116013531Sjairo.balart@metempsy.com } 116113531Sjairo.balart@metempsy.com 116213760Sjairo.balart@metempsy.com // EOImode 116313760Sjairo.balart@metempsy.com icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 116413760Sjairo.balart@metempsy.com 116513760Sjairo.balart@metempsy.com if (inSecureState()) { 116613760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 116713760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 116813760Sjairo.balart@metempsy.com } else { 116913760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 117013760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 117113760Sjairo.balart@metempsy.com } 117213760Sjairo.balart@metempsy.com 117313760Sjairo.balart@metempsy.com // CBPR 117413760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 117513760Sjairo.balart@metempsy.com // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 117613760Sjairo.balart@metempsy.com 117713760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 117813760Sjairo.balart@metempsy.com // CBPR is RO 117913760Sjairo.balart@metempsy.com } else { 118013760Sjairo.balart@metempsy.com // CBPR is RW 118113760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 118213760Sjairo.balart@metempsy.com 118313760Sjairo.balart@metempsy.com if (inSecureState()) { 118413760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 118513760Sjairo.balart@metempsy.com } else { 118613760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 118713760Sjairo.balart@metempsy.com } 118813760Sjairo.balart@metempsy.com } 118913760Sjairo.balart@metempsy.com } else { 119013760Sjairo.balart@metempsy.com // CBPR is RW 119113760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 119213760Sjairo.balart@metempsy.com } 119313760Sjairo.balart@metempsy.com 119413760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 119513760Sjairo.balart@metempsy.com 119614245Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1); 119714245Sgiacomo.travaglini@arm.com return; 119813531Sjairo.balart@metempsy.com } 119913531Sjairo.balart@metempsy.com 120013760Sjairo.balart@metempsy.com // Virtual Control Register 120113531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 120213760Sjairo.balart@metempsy.com ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 120313760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = 120413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 120513760Sjairo.balart@metempsy.com icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 120613760Sjairo.balart@metempsy.com icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 120713760Sjairo.balart@metempsy.com val = icv_ctlr_el1; 120813760Sjairo.balart@metempsy.com 120913760Sjairo.balart@metempsy.com // Aliases 121013760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 121113760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 121213760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 121313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 121413760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 121513760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 121613760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 121713760Sjairo.balart@metempsy.com break; 121813760Sjairo.balart@metempsy.com } 121913760Sjairo.balart@metempsy.com 122013760Sjairo.balart@metempsy.com // Control Register EL3 122113760Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 122213760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 122313760Sjairo.balart@metempsy.com /* 122413760Sjairo.balart@metempsy.com * ExtRange is RO. 122513760Sjairo.balart@metempsy.com * RSS is RO. 122613760Sjairo.balart@metempsy.com * nDS is RO. 122713760Sjairo.balart@metempsy.com * A3V is RO. 122813760Sjairo.balart@metempsy.com * SEIS is RO. 122913760Sjairo.balart@metempsy.com * IDbits is RO. 123013760Sjairo.balart@metempsy.com * PRIbits is RO. 123113760Sjairo.balart@metempsy.com * PMHE is RAO/WI, priority-based routing is always used. 123213760Sjairo.balart@metempsy.com */ 123313760Sjairo.balart@metempsy.com ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; 123413760Sjairo.balart@metempsy.com 123513760Sjairo.balart@metempsy.com // Aliases 123613760Sjairo.balart@metempsy.com if (haveEL(EL3)) 123713760Sjairo.balart@metempsy.com { 123813760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 123913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 124013760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 124113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 124213760Sjairo.balart@metempsy.com 124313760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).EOImode is an alias of 124413760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1NS 124513760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 124613760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).EOImode is an alias of 124713760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1S 124813760Sjairo.balart@metempsy.com icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 124913760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 125013760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 125113760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 125213760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; 125313760Sjairo.balart@metempsy.com 125413760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 125513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 125613760Sjairo.balart@metempsy.com icc_ctlr_el1_ns); 125713760Sjairo.balart@metempsy.com } 125813760Sjairo.balart@metempsy.com 125913760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 126013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 126113760Sjairo.balart@metempsy.com 126213760Sjairo.balart@metempsy.com icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 126313760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 126413760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 126513760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 126613760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 126713760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 126813760Sjairo.balart@metempsy.com 126913760Sjairo.balart@metempsy.com val = icc_ctlr_el3; 127013531Sjairo.balart@metempsy.com break; 127113531Sjairo.balart@metempsy.com } 127213531Sjairo.balart@metempsy.com 127313760Sjairo.balart@metempsy.com // Priority Mask Register 127413531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 127513760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: { 127613760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 127714057Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_PMR_EL1, val); 127813531Sjairo.balart@metempsy.com } 127913531Sjairo.balart@metempsy.com 128013531Sjairo.balart@metempsy.com val &= 0xff; 128113531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 128213531Sjairo.balart@metempsy.com 128313531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) { 128413760Sjairo.balart@metempsy.com // Spec section 4.8.1 128513760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: 128613580Sgabeblack@google.com RegVal old_icc_pmr_el1 = 128713531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 128813531Sjairo.balart@metempsy.com 128913531Sjairo.balart@metempsy.com if (!(old_icc_pmr_el1 & 0x80)) { 129013760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 129113760Sjairo.balart@metempsy.com // 0x00-0x7F then WI 129213531Sjairo.balart@metempsy.com return; 129313531Sjairo.balart@metempsy.com } 129413531Sjairo.balart@metempsy.com 129513760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 129613760Sjairo.balart@metempsy.com // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 129713760Sjairo.balart@metempsy.com // based on the Non-secure read of the priority mask value 129813760Sjairo.balart@metempsy.com // written to the register. 129913760Sjairo.balart@metempsy.com 130013531Sjairo.balart@metempsy.com val = (val >> 1) | 0x80; 130113531Sjairo.balart@metempsy.com } 130213531Sjairo.balart@metempsy.com 130313531Sjairo.balart@metempsy.com val &= ~0U << (8 - PRIORITY_BITS); 130413531Sjairo.balart@metempsy.com break; 130513531Sjairo.balart@metempsy.com } 130613531Sjairo.balart@metempsy.com 130714057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 130814057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 130914057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 131014057Sgiacomo.travaglini@arm.com ich_vmcr_el2.VPMR = val & 0xff; 131114057Sgiacomo.travaglini@arm.com 131214057Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 131314057Sgiacomo.travaglini@arm.com virtualUpdate(); 131414057Sgiacomo.travaglini@arm.com return; 131514057Sgiacomo.travaglini@arm.com } 131614057Sgiacomo.travaglini@arm.com 131713760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable Register EL1 131813760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 131913760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 132013760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 132113760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 132213760Sjairo.balart@metempsy.com } 132313760Sjairo.balart@metempsy.com 132414248Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val); 132514248Sgiacomo.travaglini@arm.com updateDistributor(); 132614248Sgiacomo.travaglini@arm.com return; 132713760Sjairo.balart@metempsy.com } 132813760Sjairo.balart@metempsy.com 132913760Sjairo.balart@metempsy.com // Virtual Interrupt Group 0 Enable register 133013760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN0_EL1: { 133113760Sjairo.balart@metempsy.com bool enable = val & 0x1; 133213760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 133313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 133413760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = enable; 133513740Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 133613740Sgiacomo.travaglini@arm.com virtualUpdate(); 133713740Sgiacomo.travaglini@arm.com return; 133813740Sgiacomo.travaglini@arm.com } 133913740Sgiacomo.travaglini@arm.com 134013760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 134113760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 134213760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 134313760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 134413760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 134513760Sjairo.balart@metempsy.com } 134613760Sjairo.balart@metempsy.com 134713760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 134813760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val; 134913760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = 135013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3); 135113760Sjairo.balart@metempsy.com 135213760Sjairo.balart@metempsy.com if (inSecureState()) { 135313760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S 135413760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable; 135513760Sjairo.balart@metempsy.com } else { 135613760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS 135713760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable; 135813760Sjairo.balart@metempsy.com } 135913760Sjairo.balart@metempsy.com 136013760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3, 136113760Sjairo.balart@metempsy.com icc_igrpen1_el3); 136213531Sjairo.balart@metempsy.com } 136313531Sjairo.balart@metempsy.com 136414247Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val); 136514248Sgiacomo.travaglini@arm.com updateDistributor(); 136614247Sgiacomo.travaglini@arm.com return; 136713531Sjairo.balart@metempsy.com } 136813531Sjairo.balart@metempsy.com 136913760Sjairo.balart@metempsy.com // Virtual Interrupt Group 1 Enable register 137013760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN1_EL1: { 137113531Sjairo.balart@metempsy.com bool enable = val & 0x1; 137213760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 137313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 137413760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = enable; 137513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 137613531Sjairo.balart@metempsy.com virtualUpdate(); 137713531Sjairo.balart@metempsy.com return; 137813531Sjairo.balart@metempsy.com } 137913531Sjairo.balart@metempsy.com 138013760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register 138113760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 138213760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: { 138313760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 138413760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = 138513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1); 138613760Sjairo.balart@metempsy.com 138713760Sjairo.balart@metempsy.com if (inSecureState()) { 138813760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S 138913760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S; 139013760Sjairo.balart@metempsy.com } else { 139113760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS 139213760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS; 139313531Sjairo.balart@metempsy.com } 139413531Sjairo.balart@metempsy.com 139513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1); 139613531Sjairo.balart@metempsy.com break; 139713531Sjairo.balart@metempsy.com } 139813531Sjairo.balart@metempsy.com 139913760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 0 Register 140013531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R: 140113531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R_EL1: 140214227Sgiacomo.travaglini@arm.com generateSGI(val, Gicv3::G0S); 140314227Sgiacomo.travaglini@arm.com break; 140413531Sjairo.balart@metempsy.com 140513760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 1 Register 140613531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI1R: 140714227Sgiacomo.travaglini@arm.com case MISCREG_ICC_SGI1R_EL1: { 140814227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 140914227Sgiacomo.travaglini@arm.com 141014227Sgiacomo.travaglini@arm.com generateSGI(val, group); 141114227Sgiacomo.travaglini@arm.com break; 141214227Sgiacomo.travaglini@arm.com } 141313531Sjairo.balart@metempsy.com 141413760Sjairo.balart@metempsy.com // Alias Software Generated Interrupt Group 1 Register 141513531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R: 141613531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R_EL1: { 141714227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S; 141814227Sgiacomo.travaglini@arm.com 141914227Sgiacomo.travaglini@arm.com generateSGI(val, group); 142014227Sgiacomo.travaglini@arm.com break; 142113531Sjairo.balart@metempsy.com } 142213531Sjairo.balart@metempsy.com 142313760Sjairo.balart@metempsy.com // System Register Enable Register EL1 142413531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 142513760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: 142613760Sjairo.balart@metempsy.com // System Register Enable Register EL2 142713531Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 142813760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: 142913760Sjairo.balart@metempsy.com // System Register Enable Register EL3 143013531Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 143113760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: 143213760Sjairo.balart@metempsy.com // All bits are RAO/WI 143313760Sjairo.balart@metempsy.com return; 143413760Sjairo.balart@metempsy.com 143513760Sjairo.balart@metempsy.com // Hyp Control Register 143613760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 143713760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: { 143813760Sjairo.balart@metempsy.com ICH_HCR_EL2 requested_ich_hcr_el2 = val; 143913760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 144013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 144113760Sjairo.balart@metempsy.com 144213760Sjairo.balart@metempsy.com if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 144313760Sjairo.balart@metempsy.com { 144413760Sjairo.balart@metempsy.com // EOIcount - Permitted behaviors are: 144513760Sjairo.balart@metempsy.com // - Increment EOIcount. 144613760Sjairo.balart@metempsy.com // - Leave EOIcount unchanged. 144713760Sjairo.balart@metempsy.com ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 144813531Sjairo.balart@metempsy.com } 144913531Sjairo.balart@metempsy.com 145013760Sjairo.balart@metempsy.com ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 145113760Sjairo.balart@metempsy.com ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 145213760Sjairo.balart@metempsy.com ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 145313760Sjairo.balart@metempsy.com ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 145413760Sjairo.balart@metempsy.com ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 145513760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 145613760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 145713760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 145813760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 145913760Sjairo.balart@metempsy.com ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 146013760Sjairo.balart@metempsy.com ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 146113760Sjairo.balart@metempsy.com ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 146213760Sjairo.balart@metempsy.com ich_hcr_el2.En = requested_ich_hcr_el2.En; 146313760Sjairo.balart@metempsy.com val = ich_hcr_el2; 146413531Sjairo.balart@metempsy.com do_virtual_update = true; 146513531Sjairo.balart@metempsy.com break; 146613760Sjairo.balart@metempsy.com } 146713760Sjairo.balart@metempsy.com 146813760Sjairo.balart@metempsy.com // List Registers 146913760Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { 147013531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 147113760Sjairo.balart@metempsy.com ICH_LRC requested_ich_lrc = val; 147213760Sjairo.balart@metempsy.com ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 147313760Sjairo.balart@metempsy.com 147413760Sjairo.balart@metempsy.com ich_lrc.State = requested_ich_lrc.State; 147513760Sjairo.balart@metempsy.com ich_lrc.HW = requested_ich_lrc.HW; 147613760Sjairo.balart@metempsy.com ich_lrc.Group = requested_ich_lrc.Group; 147713760Sjairo.balart@metempsy.com 147813760Sjairo.balart@metempsy.com // Priority, bits [23:16] 147913760Sjairo.balart@metempsy.com // At least five bits must be implemented. 148013760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 148113760Sjairo.balart@metempsy.com // We implement 5 bits. 148213760Sjairo.balart@metempsy.com ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 148313760Sjairo.balart@metempsy.com (ich_lrc.Priority & 0x07); 148413760Sjairo.balart@metempsy.com 148513760Sjairo.balart@metempsy.com // pINTID, bits [12:0] 148613760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 0 this field has the following meaning: 148713760Sjairo.balart@metempsy.com // - Bits[12:10] : RES0. 148813760Sjairo.balart@metempsy.com // - Bit[9] : EOI. 148913760Sjairo.balart@metempsy.com // - Bits[8:0] : RES0. 149013760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 1: 149113760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 149213760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 149313760Sjairo.balart@metempsy.com // order bits are RES0. 149413760Sjairo.balart@metempsy.com if (requested_ich_lrc.HW == 0) { 149513760Sjairo.balart@metempsy.com ich_lrc.EOI = requested_ich_lrc.EOI; 149613760Sjairo.balart@metempsy.com } else { 149713760Sjairo.balart@metempsy.com ich_lrc.pINTID = requested_ich_lrc.pINTID; 149813531Sjairo.balart@metempsy.com } 149913531Sjairo.balart@metempsy.com 150013760Sjairo.balart@metempsy.com val = ich_lrc; 150113760Sjairo.balart@metempsy.com do_virtual_update = true; 150213760Sjairo.balart@metempsy.com break; 150313760Sjairo.balart@metempsy.com } 150413760Sjairo.balart@metempsy.com 150513760Sjairo.balart@metempsy.com // List Registers 150613531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 150713531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 150813580Sgabeblack@google.com RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 150913531Sjairo.balart@metempsy.com val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 151013531Sjairo.balart@metempsy.com do_virtual_update = true; 151113531Sjairo.balart@metempsy.com break; 151213531Sjairo.balart@metempsy.com } 151313531Sjairo.balart@metempsy.com 151413760Sjairo.balart@metempsy.com // List Registers 151513531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64 151613760Sjairo.balart@metempsy.com ICH_LR_EL2 requested_ich_lr_el2 = val; 151713760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 151813760Sjairo.balart@metempsy.com 151913760Sjairo.balart@metempsy.com ich_lr_el2.State = requested_ich_lr_el2.State; 152013760Sjairo.balart@metempsy.com ich_lr_el2.HW = requested_ich_lr_el2.HW; 152113760Sjairo.balart@metempsy.com ich_lr_el2.Group = requested_ich_lr_el2.Group; 152213760Sjairo.balart@metempsy.com 152313760Sjairo.balart@metempsy.com // Priority, bits [55:48] 152413760Sjairo.balart@metempsy.com // At least five bits must be implemented. 152513760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 152613760Sjairo.balart@metempsy.com // We implement 5 bits. 152713760Sjairo.balart@metempsy.com ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 152813760Sjairo.balart@metempsy.com (ich_lr_el2.Priority & 0x07); 152913760Sjairo.balart@metempsy.com 153013760Sjairo.balart@metempsy.com // pINTID, bits [44:32] 153113760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 153213760Sjairo.balart@metempsy.com // - Bits[44:42] : RES0. 153313760Sjairo.balart@metempsy.com // - Bit[41] : EOI. 153413760Sjairo.balart@metempsy.com // - Bits[40:32] : RES0. 153513760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 1: 153613760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 153713760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 153813760Sjairo.balart@metempsy.com // order bits are RES0. 153913760Sjairo.balart@metempsy.com if (requested_ich_lr_el2.HW == 0) { 154013760Sjairo.balart@metempsy.com ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 154113760Sjairo.balart@metempsy.com } else { 154213760Sjairo.balart@metempsy.com ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 154313760Sjairo.balart@metempsy.com } 154413760Sjairo.balart@metempsy.com 154513760Sjairo.balart@metempsy.com // vINTID, bits [31:0] 154613760Sjairo.balart@metempsy.com // It is IMPLEMENTATION DEFINED how many bits are implemented, 154713760Sjairo.balart@metempsy.com // though at least 16 bits must be implemented. 154813760Sjairo.balart@metempsy.com // Unimplemented bits are RES0. 154913760Sjairo.balart@metempsy.com ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 155013760Sjairo.balart@metempsy.com 155113760Sjairo.balart@metempsy.com val = ich_lr_el2; 155213531Sjairo.balart@metempsy.com do_virtual_update = true; 155313531Sjairo.balart@metempsy.com break; 155413531Sjairo.balart@metempsy.com } 155513531Sjairo.balart@metempsy.com 155613760Sjairo.balart@metempsy.com // Virtual Machine Control Register 155713531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 155813531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: { 155913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 156013760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 156113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 156213760Sjairo.balart@metempsy.com ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; 156313531Sjairo.balart@metempsy.com uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS; 156413760Sjairo.balart@metempsy.com 156513760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 156613760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = min_vpr0; 156713760Sjairo.balart@metempsy.com } else { 156813760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 156913760Sjairo.balart@metempsy.com } 157013760Sjairo.balart@metempsy.com 157113531Sjairo.balart@metempsy.com uint8_t min_vpr1 = min_vpr0 + 1; 157213760Sjairo.balart@metempsy.com 157313760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 157413760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = min_vpr1; 157513760Sjairo.balart@metempsy.com } else { 157613760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 157713760Sjairo.balart@metempsy.com } 157813760Sjairo.balart@metempsy.com 157913760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 158013760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 158113760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 158213760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 158313760Sjairo.balart@metempsy.com val = ich_vmcr_el2; 158413531Sjairo.balart@metempsy.com break; 158513531Sjairo.balart@metempsy.com } 158613531Sjairo.balart@metempsy.com 158713760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 158814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0: 158914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0_EL2: 159014236Sgiacomo.travaglini@arm.com break; 159114236Sgiacomo.travaglini@arm.com 159214236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 159314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 159414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 159514236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 159614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 159714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 159814236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 159914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 160014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 160114236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 160214236Sgiacomo.travaglini@arm.com return; 160314236Sgiacomo.travaglini@arm.com 160413760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 160514236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0: 160614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0_EL2: 160713531Sjairo.balart@metempsy.com break; 160813531Sjairo.balart@metempsy.com 160914236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 161014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 161114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 161214236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 161314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 161414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 161514236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 161614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 161714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 161814236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 161914236Sgiacomo.travaglini@arm.com return; 162014236Sgiacomo.travaglini@arm.com 162113531Sjairo.balart@metempsy.com default: 162213760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 162313760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 162413531Sjairo.balart@metempsy.com } 162513531Sjairo.balart@metempsy.com 162613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(misc_reg, val); 162713531Sjairo.balart@metempsy.com 162813531Sjairo.balart@metempsy.com if (do_virtual_update) { 162913531Sjairo.balart@metempsy.com virtualUpdate(); 163013531Sjairo.balart@metempsy.com } 163113531Sjairo.balart@metempsy.com} 163213531Sjairo.balart@metempsy.com 163314243Sgiacomo.travaglini@arm.comRegVal 163414243Sgiacomo.travaglini@arm.comGicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const 163514243Sgiacomo.travaglini@arm.com{ 163614243Sgiacomo.travaglini@arm.com return isa->readMiscRegNoEffect( 163714243Sgiacomo.travaglini@arm.com isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3())); 163814243Sgiacomo.travaglini@arm.com} 163914243Sgiacomo.travaglini@arm.com 164014243Sgiacomo.travaglini@arm.comvoid 164114243Sgiacomo.travaglini@arm.comGicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const 164214243Sgiacomo.travaglini@arm.com{ 164314243Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect( 164414243Sgiacomo.travaglini@arm.com isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val); 164514243Sgiacomo.travaglini@arm.com} 164614243Sgiacomo.travaglini@arm.com 164713531Sjairo.balart@metempsy.comint 164813760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualFindActive(uint32_t int_id) const 164913531Sjairo.balart@metempsy.com{ 165013531Sjairo.balart@metempsy.com for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 165113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 165213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 165313760Sjairo.balart@metempsy.com 165413760Sjairo.balart@metempsy.com if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 165513760Sjairo.balart@metempsy.com (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 165613760Sjairo.balart@metempsy.com (ich_lr_el2.vINTID == int_id)) { 165713531Sjairo.balart@metempsy.com return lr_idx; 165813531Sjairo.balart@metempsy.com } 165913531Sjairo.balart@metempsy.com } 166013531Sjairo.balart@metempsy.com 166113531Sjairo.balart@metempsy.com return -1; 166213531Sjairo.balart@metempsy.com} 166313531Sjairo.balart@metempsy.com 166413531Sjairo.balart@metempsy.comuint32_t 166513760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR0() const 166613531Sjairo.balart@metempsy.com{ 166714233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 166813531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 166913531Sjairo.balart@metempsy.com } 167013531Sjairo.balart@metempsy.com 167113531Sjairo.balart@metempsy.com bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 167213531Sjairo.balart@metempsy.com 167313531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) { 167413760Sjairo.balart@metempsy.com // interrupt for the other state pending 167513531Sjairo.balart@metempsy.com return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 167613531Sjairo.balart@metempsy.com } 167713531Sjairo.balart@metempsy.com 167813531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 167913531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 168013531Sjairo.balart@metempsy.com } 168113531Sjairo.balart@metempsy.com 168213531Sjairo.balart@metempsy.com if (irq_is_secure && !inSecureState()) { 168313531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 168413531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 168513531Sjairo.balart@metempsy.com } 168613531Sjairo.balart@metempsy.com 168713531Sjairo.balart@metempsy.com return hppi.intid; 168813531Sjairo.balart@metempsy.com} 168913531Sjairo.balart@metempsy.com 169013531Sjairo.balart@metempsy.comuint32_t 169113760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR1() const 169213531Sjairo.balart@metempsy.com{ 169314233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 169413531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169513531Sjairo.balart@metempsy.com } 169613531Sjairo.balart@metempsy.com 169713760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 169813760Sjairo.balart@metempsy.com if ((currEL() == EL3) && icc_ctlr_el3.RM) { 169913531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 170013531Sjairo.balart@metempsy.com return Gicv3::INTID_SECURE; 170113531Sjairo.balart@metempsy.com } else if (hppi.group == Gicv3::G1NS) { 170213531Sjairo.balart@metempsy.com return Gicv3::INTID_NONSECURE; 170313531Sjairo.balart@metempsy.com } 170413531Sjairo.balart@metempsy.com } 170513531Sjairo.balart@metempsy.com 170613531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 170713531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170813531Sjairo.balart@metempsy.com } 170913531Sjairo.balart@metempsy.com 171013531Sjairo.balart@metempsy.com bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 171113531Sjairo.balart@metempsy.com 171213531Sjairo.balart@metempsy.com if (irq_is_secure) { 171313531Sjairo.balart@metempsy.com if (!inSecureState()) { 171413531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 171513531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 171613531Sjairo.balart@metempsy.com } 171713531Sjairo.balart@metempsy.com } else if (!isEL3OrMon() && inSecureState()) { 171813531Sjairo.balart@metempsy.com // Group 1 non-secure interrupts not visible in Secure EL1 171913531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 172013531Sjairo.balart@metempsy.com } 172113531Sjairo.balart@metempsy.com 172213531Sjairo.balart@metempsy.com return hppi.intid; 172313531Sjairo.balart@metempsy.com} 172413531Sjairo.balart@metempsy.com 172513531Sjairo.balart@metempsy.comvoid 172613531Sjairo.balart@metempsy.comGicv3CPUInterface::dropPriority(Gicv3::GroupId group) 172713531Sjairo.balart@metempsy.com{ 172814246Sgiacomo.travaglini@arm.com int apr_misc_reg = 0; 172914246Sgiacomo.travaglini@arm.com 173014246Sgiacomo.travaglini@arm.com switch (group) { 173114246Sgiacomo.travaglini@arm.com case Gicv3::G0S: 173214246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP0R0_EL1; 173314246Sgiacomo.travaglini@arm.com break; 173414246Sgiacomo.travaglini@arm.com case Gicv3::G1S: 173514246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S; 173614246Sgiacomo.travaglini@arm.com break; 173714246Sgiacomo.travaglini@arm.com case Gicv3::G1NS: 173814246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS; 173914246Sgiacomo.travaglini@arm.com break; 174014246Sgiacomo.travaglini@arm.com default: 174114246Sgiacomo.travaglini@arm.com panic("Invalid Gicv3::GroupId"); 174214246Sgiacomo.travaglini@arm.com } 174314246Sgiacomo.travaglini@arm.com 174414246Sgiacomo.travaglini@arm.com RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg); 174513531Sjairo.balart@metempsy.com 174613531Sjairo.balart@metempsy.com if (apr) { 174713531Sjairo.balart@metempsy.com apr &= apr - 1; 174813531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_misc_reg, apr); 174913531Sjairo.balart@metempsy.com } 175013531Sjairo.balart@metempsy.com 175113531Sjairo.balart@metempsy.com update(); 175213531Sjairo.balart@metempsy.com} 175313531Sjairo.balart@metempsy.com 175413531Sjairo.balart@metempsy.comuint8_t 175513531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDropPriority() 175613531Sjairo.balart@metempsy.com{ 175713531Sjairo.balart@metempsy.com int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 175813531Sjairo.balart@metempsy.com 175913531Sjairo.balart@metempsy.com for (int i = 0; i < apr_max; i++) { 176013580Sgabeblack@google.com RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 176113580Sgabeblack@google.com RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 176213531Sjairo.balart@metempsy.com 176313531Sjairo.balart@metempsy.com if (!vapr0 && !vapr1) { 176413531Sjairo.balart@metempsy.com continue; 176513531Sjairo.balart@metempsy.com } 176613531Sjairo.balart@metempsy.com 176713531Sjairo.balart@metempsy.com int vapr0_count = ctz32(vapr0); 176813531Sjairo.balart@metempsy.com int vapr1_count = ctz32(vapr1); 176913531Sjairo.balart@metempsy.com 177013531Sjairo.balart@metempsy.com if (vapr0_count <= vapr1_count) { 177113531Sjairo.balart@metempsy.com vapr0 &= vapr0 - 1; 177213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 177313531Sjairo.balart@metempsy.com return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 177413531Sjairo.balart@metempsy.com } else { 177513531Sjairo.balart@metempsy.com vapr1 &= vapr1 - 1; 177613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 177713531Sjairo.balart@metempsy.com return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 177813531Sjairo.balart@metempsy.com } 177913531Sjairo.balart@metempsy.com } 178013531Sjairo.balart@metempsy.com 178113531Sjairo.balart@metempsy.com return 0xff; 178213531Sjairo.balart@metempsy.com} 178313531Sjairo.balart@metempsy.com 178413531Sjairo.balart@metempsy.comvoid 178514227Sgiacomo.travaglini@arm.comGicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group) 178614227Sgiacomo.travaglini@arm.com{ 178714227Sgiacomo.travaglini@arm.com uint8_t aff3 = bits(val, 55, 48); 178814227Sgiacomo.travaglini@arm.com uint8_t aff2 = bits(val, 39, 32); 178914227Sgiacomo.travaglini@arm.com uint8_t aff1 = bits(val, 23, 16);; 179014227Sgiacomo.travaglini@arm.com uint16_t target_list = bits(val, 15, 0); 179114227Sgiacomo.travaglini@arm.com uint32_t int_id = bits(val, 27, 24); 179214227Sgiacomo.travaglini@arm.com bool irm = bits(val, 40, 40); 179314227Sgiacomo.travaglini@arm.com uint8_t rs = bits(val, 47, 44); 179414227Sgiacomo.travaglini@arm.com 179514227Sgiacomo.travaglini@arm.com bool ns = !inSecureState(); 179614227Sgiacomo.travaglini@arm.com 179714227Sgiacomo.travaglini@arm.com for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 179814227Sgiacomo.travaglini@arm.com Gicv3Redistributor * redistributor_i = 179914227Sgiacomo.travaglini@arm.com gic->getRedistributor(i); 180014227Sgiacomo.travaglini@arm.com uint32_t affinity_i = redistributor_i->getAffinity(); 180114227Sgiacomo.travaglini@arm.com 180214227Sgiacomo.travaglini@arm.com if (irm) { 180314227Sgiacomo.travaglini@arm.com // Interrupts routed to all PEs in the system, 180414227Sgiacomo.travaglini@arm.com // excluding "self" 180514227Sgiacomo.travaglini@arm.com if (affinity_i == redistributor->getAffinity()) { 180614227Sgiacomo.travaglini@arm.com continue; 180714227Sgiacomo.travaglini@arm.com } 180814227Sgiacomo.travaglini@arm.com } else { 180914227Sgiacomo.travaglini@arm.com // Interrupts routed to the PEs specified by 181014227Sgiacomo.travaglini@arm.com // Aff3.Aff2.Aff1.<target list> 181114227Sgiacomo.travaglini@arm.com if ((affinity_i >> 8) != 181214227Sgiacomo.travaglini@arm.com ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { 181314227Sgiacomo.travaglini@arm.com continue; 181414227Sgiacomo.travaglini@arm.com } 181514227Sgiacomo.travaglini@arm.com 181614227Sgiacomo.travaglini@arm.com uint8_t aff0_i = bits(affinity_i, 7, 0); 181714227Sgiacomo.travaglini@arm.com 181814227Sgiacomo.travaglini@arm.com if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 && 181914227Sgiacomo.travaglini@arm.com ((0x1 << (aff0_i - rs * 16)) & target_list))) { 182014227Sgiacomo.travaglini@arm.com continue; 182114227Sgiacomo.travaglini@arm.com } 182214227Sgiacomo.travaglini@arm.com } 182314227Sgiacomo.travaglini@arm.com 182414227Sgiacomo.travaglini@arm.com redistributor_i->sendSGI(int_id, group, ns); 182514227Sgiacomo.travaglini@arm.com } 182614227Sgiacomo.travaglini@arm.com} 182714227Sgiacomo.travaglini@arm.com 182814227Sgiacomo.travaglini@arm.comvoid 182913531Sjairo.balart@metempsy.comGicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 183013531Sjairo.balart@metempsy.com{ 183113531Sjairo.balart@metempsy.com // Update active priority registers. 183213531Sjairo.balart@metempsy.com uint32_t prio = hppi.prio & 0xf8; 183313531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - PRIORITY_BITS); 183413531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 183514246Sgiacomo.travaglini@arm.com 183614246Sgiacomo.travaglini@arm.com int apr_idx = 0; 183714246Sgiacomo.travaglini@arm.com switch (group) { 183814246Sgiacomo.travaglini@arm.com case Gicv3::G0S: 183914246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP0R0_EL1; 184014246Sgiacomo.travaglini@arm.com break; 184114246Sgiacomo.travaglini@arm.com case Gicv3::G1S: 184214246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP1R0_EL1_S; 184314246Sgiacomo.travaglini@arm.com break; 184414246Sgiacomo.travaglini@arm.com case Gicv3::G1NS: 184514246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP1R0_EL1_NS; 184614246Sgiacomo.travaglini@arm.com break; 184714246Sgiacomo.travaglini@arm.com default: 184814246Sgiacomo.travaglini@arm.com panic("Invalid Gicv3::GroupId"); 184914246Sgiacomo.travaglini@arm.com } 185014246Sgiacomo.travaglini@arm.com 185113580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 185213531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 185313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 185413531Sjairo.balart@metempsy.com 185513531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 185613531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 185713531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 185813531Sjairo.balart@metempsy.com redistributor->activateIRQ(int_id); 185913531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 186013531Sjairo.balart@metempsy.com // SPI, distributor 186113531Sjairo.balart@metempsy.com distributor->activateIRQ(int_id); 186213923Sgiacomo.travaglini@arm.com } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 186313923Sgiacomo.travaglini@arm.com // LPI, Redistributor 186413923Sgiacomo.travaglini@arm.com redistributor->setClrLPI(int_id, false); 186513531Sjairo.balart@metempsy.com } 186614231Sgiacomo.travaglini@arm.com 186714231Sgiacomo.travaglini@arm.com // By setting the priority to 0xff we are effectively 186814231Sgiacomo.travaglini@arm.com // making the int_id not pending anymore at the cpu 186914231Sgiacomo.travaglini@arm.com // interface. 187014231Sgiacomo.travaglini@arm.com hppi.prio = 0xff; 187114231Sgiacomo.travaglini@arm.com updateDistributor(); 187213531Sjairo.balart@metempsy.com} 187313531Sjairo.balart@metempsy.com 187413531Sjairo.balart@metempsy.comvoid 187513531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 187613531Sjairo.balart@metempsy.com{ 187713531Sjairo.balart@metempsy.com // Update active priority registers. 187813760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 187913531Sjairo.balart@metempsy.com lr_idx); 188013760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 188113760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el.Priority & 0xf8; 188213531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 188313531Sjairo.balart@metempsy.com int reg_no = apr_bit / 32; 188413531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 188513531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 188613531Sjairo.balart@metempsy.com MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 188713580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 188813531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 188913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 189013531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 189113760Sjairo.balart@metempsy.com ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 189213760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); 189313531Sjairo.balart@metempsy.com} 189413531Sjairo.balart@metempsy.com 189513531Sjairo.balart@metempsy.comvoid 189613531Sjairo.balart@metempsy.comGicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 189713531Sjairo.balart@metempsy.com{ 189813531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 189913531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 190013531Sjairo.balart@metempsy.com redistributor->deactivateIRQ(int_id); 190113531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 190213531Sjairo.balart@metempsy.com // SPI, distributor 190313531Sjairo.balart@metempsy.com distributor->deactivateIRQ(int_id); 190413531Sjairo.balart@metempsy.com } 190514231Sgiacomo.travaglini@arm.com 190614231Sgiacomo.travaglini@arm.com updateDistributor(); 190713531Sjairo.balart@metempsy.com} 190813531Sjairo.balart@metempsy.com 190913531Sjairo.balart@metempsy.comvoid 191013531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 191113531Sjairo.balart@metempsy.com{ 191213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 191313531Sjairo.balart@metempsy.com lr_idx); 191413531Sjairo.balart@metempsy.com 191513760Sjairo.balart@metempsy.com if (ich_lr_el2.HW) { 191613531Sjairo.balart@metempsy.com // Deactivate the associated physical interrupt 191713760Sjairo.balart@metempsy.com if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 191813760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 191913760Sjairo.balart@metempsy.com distributor->getIntGroup(ich_lr_el2.pINTID) : 192013760Sjairo.balart@metempsy.com redistributor->getIntGroup(ich_lr_el2.pINTID); 192113760Sjairo.balart@metempsy.com deactivateIRQ(ich_lr_el2.pINTID, group); 192213531Sjairo.balart@metempsy.com } 192313531Sjairo.balart@metempsy.com } 192413531Sjairo.balart@metempsy.com 192513531Sjairo.balart@metempsy.com // Remove the active bit 192613760Sjairo.balart@metempsy.com ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 192713760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); 192813531Sjairo.balart@metempsy.com} 192913531Sjairo.balart@metempsy.com 193013531Sjairo.balart@metempsy.com/* 193113760Sjairo.balart@metempsy.com * Returns the priority group field for the current BPR value for the group. 193213760Sjairo.balart@metempsy.com * GroupBits() Pseudocode from spec. 193313531Sjairo.balart@metempsy.com */ 193413531Sjairo.balart@metempsy.comuint32_t 193513926Sgiacomo.travaglini@arm.comGicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) 193613531Sjairo.balart@metempsy.com{ 193713760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 193813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 193913760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 194013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 194113760Sjairo.balart@metempsy.com 194213760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 194313760Sjairo.balart@metempsy.com (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 194413531Sjairo.balart@metempsy.com group = Gicv3::G0S; 194513531Sjairo.balart@metempsy.com } 194613531Sjairo.balart@metempsy.com 194713531Sjairo.balart@metempsy.com int bpr; 194813531Sjairo.balart@metempsy.com 194913531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 195013926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; 195114237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1S) { 195214237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1S) & 0x7; 195313531Sjairo.balart@metempsy.com } else { 195414237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1NS) & 0x7; 195513531Sjairo.balart@metempsy.com } 195613531Sjairo.balart@metempsy.com 195713531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 195813531Sjairo.balart@metempsy.com assert(bpr > 0); 195913531Sjairo.balart@metempsy.com bpr--; 196013531Sjairo.balart@metempsy.com } 196113531Sjairo.balart@metempsy.com 196213531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 196313531Sjairo.balart@metempsy.com} 196413531Sjairo.balart@metempsy.com 196513531Sjairo.balart@metempsy.comuint32_t 196613760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const 196713531Sjairo.balart@metempsy.com{ 196813760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 196913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 197013531Sjairo.balart@metempsy.com 197113760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 197213531Sjairo.balart@metempsy.com group = Gicv3::G0S; 197313531Sjairo.balart@metempsy.com } 197413531Sjairo.balart@metempsy.com 197513531Sjairo.balart@metempsy.com int bpr; 197613531Sjairo.balart@metempsy.com 197713531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 197813760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR0; 197913531Sjairo.balart@metempsy.com } else { 198013760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR1; 198113531Sjairo.balart@metempsy.com } 198213531Sjairo.balart@metempsy.com 198313531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 198413531Sjairo.balart@metempsy.com assert(bpr > 0); 198513531Sjairo.balart@metempsy.com bpr--; 198613531Sjairo.balart@metempsy.com } 198713531Sjairo.balart@metempsy.com 198813531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 198913531Sjairo.balart@metempsy.com} 199013531Sjairo.balart@metempsy.com 199113531Sjairo.balart@metempsy.combool 199213760Sjairo.balart@metempsy.comGicv3CPUInterface::isEOISplitMode() const 199313531Sjairo.balart@metempsy.com{ 199413531Sjairo.balart@metempsy.com if (isEL3OrMon()) { 199513760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 199613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 199713760Sjairo.balart@metempsy.com return icc_ctlr_el3.EOImode_EL3; 199813531Sjairo.balart@metempsy.com } else { 199914245Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1 = 0; 200014245Sgiacomo.travaglini@arm.com if (inSecureState()) 200114245Sgiacomo.travaglini@arm.com icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 200214245Sgiacomo.travaglini@arm.com else 200314245Sgiacomo.travaglini@arm.com icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 200413760Sjairo.balart@metempsy.com return icc_ctlr_el1.EOImode; 200513531Sjairo.balart@metempsy.com } 200613531Sjairo.balart@metempsy.com} 200713531Sjairo.balart@metempsy.com 200813531Sjairo.balart@metempsy.combool 200913760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIsEOISplitMode() const 201013531Sjairo.balart@metempsy.com{ 201113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 201213760Sjairo.balart@metempsy.com return ich_vmcr_el2.VEOIM; 201313531Sjairo.balart@metempsy.com} 201413531Sjairo.balart@metempsy.com 201513531Sjairo.balart@metempsy.comint 201613760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActiveGroup() const 201713531Sjairo.balart@metempsy.com{ 201813531Sjairo.balart@metempsy.com int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 201913531Sjairo.balart@metempsy.com int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 202013531Sjairo.balart@metempsy.com int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 202113531Sjairo.balart@metempsy.com 202213531Sjairo.balart@metempsy.com if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 202313531Sjairo.balart@metempsy.com return Gicv3::G1NS; 202413531Sjairo.balart@metempsy.com } 202513531Sjairo.balart@metempsy.com 202613531Sjairo.balart@metempsy.com if (gq_ctz < g0_ctz) { 202713531Sjairo.balart@metempsy.com return Gicv3::G1S; 202813531Sjairo.balart@metempsy.com } 202913531Sjairo.balart@metempsy.com 203013531Sjairo.balart@metempsy.com if (g0_ctz < 32) { 203113531Sjairo.balart@metempsy.com return Gicv3::G0S; 203213531Sjairo.balart@metempsy.com } 203313531Sjairo.balart@metempsy.com 203413531Sjairo.balart@metempsy.com return -1; 203513531Sjairo.balart@metempsy.com} 203613531Sjairo.balart@metempsy.com 203713531Sjairo.balart@metempsy.comvoid 203814231Sgiacomo.travaglini@arm.comGicv3CPUInterface::updateDistributor() 203914231Sgiacomo.travaglini@arm.com{ 204014231Sgiacomo.travaglini@arm.com distributor->update(); 204114231Sgiacomo.travaglini@arm.com} 204214231Sgiacomo.travaglini@arm.com 204314231Sgiacomo.travaglini@arm.comvoid 204413531Sjairo.balart@metempsy.comGicv3CPUInterface::update() 204513531Sjairo.balart@metempsy.com{ 204613531Sjairo.balart@metempsy.com bool signal_IRQ = false; 204713531Sjairo.balart@metempsy.com bool signal_FIQ = false; 204813531Sjairo.balart@metempsy.com 204913531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 205013531Sjairo.balart@metempsy.com /* 205113531Sjairo.balart@metempsy.com * Secure enabled GIC sending a G1S IRQ to a secure disabled 205213531Sjairo.balart@metempsy.com * CPU -> send G0 IRQ 205313531Sjairo.balart@metempsy.com */ 205413531Sjairo.balart@metempsy.com hppi.group = Gicv3::G0S; 205513531Sjairo.balart@metempsy.com } 205613531Sjairo.balart@metempsy.com 205713531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 205813531Sjairo.balart@metempsy.com ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 205913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::update(): " 206013531Sjairo.balart@metempsy.com "posting int as %d!\n", int_type); 206113531Sjairo.balart@metempsy.com int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 206213531Sjairo.balart@metempsy.com } 206313531Sjairo.balart@metempsy.com 206413531Sjairo.balart@metempsy.com if (signal_IRQ) { 206513531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_IRQ); 206613531Sjairo.balart@metempsy.com } else { 206713531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_IRQ); 206813531Sjairo.balart@metempsy.com } 206913531Sjairo.balart@metempsy.com 207013531Sjairo.balart@metempsy.com if (signal_FIQ) { 207113531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_FIQ); 207213531Sjairo.balart@metempsy.com } else { 207313531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_FIQ); 207413531Sjairo.balart@metempsy.com } 207513531Sjairo.balart@metempsy.com} 207613531Sjairo.balart@metempsy.com 207713531Sjairo.balart@metempsy.comvoid 207813531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualUpdate() 207913531Sjairo.balart@metempsy.com{ 208013531Sjairo.balart@metempsy.com bool signal_IRQ = false; 208113531Sjairo.balart@metempsy.com bool signal_FIQ = false; 208213531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 208313531Sjairo.balart@metempsy.com 208413531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 208513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 208613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 208713531Sjairo.balart@metempsy.com 208813531Sjairo.balart@metempsy.com if (hppviCanPreempt(lr_idx)) { 208913760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 209013531Sjairo.balart@metempsy.com signal_IRQ = true; 209113531Sjairo.balart@metempsy.com } else { 209213531Sjairo.balart@metempsy.com signal_FIQ = true; 209313531Sjairo.balart@metempsy.com } 209413531Sjairo.balart@metempsy.com } 209513531Sjairo.balart@metempsy.com } 209613531Sjairo.balart@metempsy.com 209713760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 209813760Sjairo.balart@metempsy.com 209913760Sjairo.balart@metempsy.com if (ich_hcr_el2.En) { 210013531Sjairo.balart@metempsy.com if (maintenanceInterruptStatus()) { 210113826Sgiacomo.travaglini@arm.com maintenanceInterrupt->raise(); 210213531Sjairo.balart@metempsy.com } 210313531Sjairo.balart@metempsy.com } 210413531Sjairo.balart@metempsy.com 210513531Sjairo.balart@metempsy.com if (signal_IRQ) { 210613531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 210713531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 210813531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 210913531Sjairo.balart@metempsy.com } else { 211013531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 211113531Sjairo.balart@metempsy.com } 211213531Sjairo.balart@metempsy.com 211313531Sjairo.balart@metempsy.com if (signal_FIQ) { 211413531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 211513531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 211613531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 211713531Sjairo.balart@metempsy.com } else { 211813531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 211913531Sjairo.balart@metempsy.com } 212013531Sjairo.balart@metempsy.com} 212113531Sjairo.balart@metempsy.com 212213760Sjairo.balart@metempsy.com// Returns the index of the LR with the HPPI 212313531Sjairo.balart@metempsy.comint 212413760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPVILR() const 212513531Sjairo.balart@metempsy.com{ 212613531Sjairo.balart@metempsy.com int idx = -1; 212713760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 212813760Sjairo.balart@metempsy.com 212913760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { 213013531Sjairo.balart@metempsy.com // VG0 and VG1 disabled... 213113531Sjairo.balart@metempsy.com return idx; 213213531Sjairo.balart@metempsy.com } 213313531Sjairo.balart@metempsy.com 213413531Sjairo.balart@metempsy.com uint8_t highest_prio = 0xff; 213513531Sjairo.balart@metempsy.com 213613531Sjairo.balart@metempsy.com for (int i = 0; i < 16; i++) { 213713760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 213813531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i); 213913760Sjairo.balart@metempsy.com 214013760Sjairo.balart@metempsy.com if (ich_lr_el2.State != Gicv3::INT_PENDING) { 214113531Sjairo.balart@metempsy.com continue; 214213531Sjairo.balart@metempsy.com } 214313531Sjairo.balart@metempsy.com 214413760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 214513531Sjairo.balart@metempsy.com // VG1 214613760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG1) { 214713531Sjairo.balart@metempsy.com continue; 214813531Sjairo.balart@metempsy.com } 214913531Sjairo.balart@metempsy.com } else { 215013531Sjairo.balart@metempsy.com // VG0 215113760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0) { 215213531Sjairo.balart@metempsy.com continue; 215313531Sjairo.balart@metempsy.com } 215413531Sjairo.balart@metempsy.com } 215513531Sjairo.balart@metempsy.com 215613760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 215713531Sjairo.balart@metempsy.com 215813531Sjairo.balart@metempsy.com if (prio < highest_prio) { 215913531Sjairo.balart@metempsy.com highest_prio = prio; 216013531Sjairo.balart@metempsy.com idx = i; 216113531Sjairo.balart@metempsy.com } 216213531Sjairo.balart@metempsy.com } 216313531Sjairo.balart@metempsy.com 216413531Sjairo.balart@metempsy.com return idx; 216513531Sjairo.balart@metempsy.com} 216613531Sjairo.balart@metempsy.com 216713531Sjairo.balart@metempsy.combool 216813760Sjairo.balart@metempsy.comGicv3CPUInterface::hppviCanPreempt(int lr_idx) const 216913531Sjairo.balart@metempsy.com{ 217013760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 217113760Sjairo.balart@metempsy.com if (!ich_hcr_el2.En) { 217213531Sjairo.balart@metempsy.com // virtual interface is disabled 217313531Sjairo.balart@metempsy.com return false; 217413531Sjairo.balart@metempsy.com } 217513531Sjairo.balart@metempsy.com 217613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 217713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 217813760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 217913531Sjairo.balart@metempsy.com uint8_t vpmr = 218013531Sjairo.balart@metempsy.com bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 218113531Sjairo.balart@metempsy.com 218213531Sjairo.balart@metempsy.com if (prio >= vpmr) { 218313531Sjairo.balart@metempsy.com // prioriry masked 218413531Sjairo.balart@metempsy.com return false; 218513531Sjairo.balart@metempsy.com } 218613531Sjairo.balart@metempsy.com 218713531Sjairo.balart@metempsy.com uint8_t rprio = virtualHighestActivePriority(); 218813531Sjairo.balart@metempsy.com 218913531Sjairo.balart@metempsy.com if (rprio == 0xff) { 219013531Sjairo.balart@metempsy.com return true; 219113531Sjairo.balart@metempsy.com } 219213531Sjairo.balart@metempsy.com 219313760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 219413531Sjairo.balart@metempsy.com uint32_t prio_mask = virtualGroupPriorityMask(group); 219513531Sjairo.balart@metempsy.com 219613531Sjairo.balart@metempsy.com if ((prio & prio_mask) < (rprio & prio_mask)) { 219713531Sjairo.balart@metempsy.com return true; 219813531Sjairo.balart@metempsy.com } 219913531Sjairo.balart@metempsy.com 220013531Sjairo.balart@metempsy.com return false; 220113531Sjairo.balart@metempsy.com} 220213531Sjairo.balart@metempsy.com 220313531Sjairo.balart@metempsy.comuint8_t 220413760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualHighestActivePriority() const 220513531Sjairo.balart@metempsy.com{ 220613531Sjairo.balart@metempsy.com uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 220713531Sjairo.balart@metempsy.com 220813531Sjairo.balart@metempsy.com for (int i = 0; i < num_aprs; i++) { 220913580Sgabeblack@google.com RegVal vapr = 221013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 221113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 221213531Sjairo.balart@metempsy.com 221313531Sjairo.balart@metempsy.com if (!vapr) { 221413531Sjairo.balart@metempsy.com continue; 221513531Sjairo.balart@metempsy.com } 221613531Sjairo.balart@metempsy.com 221713531Sjairo.balart@metempsy.com return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 221813531Sjairo.balart@metempsy.com } 221913531Sjairo.balart@metempsy.com 222013531Sjairo.balart@metempsy.com // no active interrups, return idle priority 222113531Sjairo.balart@metempsy.com return 0xff; 222213531Sjairo.balart@metempsy.com} 222313531Sjairo.balart@metempsy.com 222413531Sjairo.balart@metempsy.comvoid 222513531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIncrementEOICount() 222613531Sjairo.balart@metempsy.com{ 222713531Sjairo.balart@metempsy.com // Increment the EOICOUNT field in ICH_HCR_EL2 222813580Sgabeblack@google.com RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 222913531Sjairo.balart@metempsy.com uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 223013531Sjairo.balart@metempsy.com EOI_cout++; 223113531Sjairo.balart@metempsy.com ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 223213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 223313531Sjairo.balart@metempsy.com} 223413531Sjairo.balart@metempsy.com 223513760Sjairo.balart@metempsy.com// spec section 4.6.2 223613531Sjairo.balart@metempsy.comArmISA::InterruptTypes 223713760Sjairo.balart@metempsy.comGicv3CPUInterface::intSignalType(Gicv3::GroupId group) const 223813531Sjairo.balart@metempsy.com{ 223913531Sjairo.balart@metempsy.com bool is_fiq = false; 224013531Sjairo.balart@metempsy.com 224113531Sjairo.balart@metempsy.com switch (group) { 224213531Sjairo.balart@metempsy.com case Gicv3::G0S: 224313531Sjairo.balart@metempsy.com is_fiq = true; 224413531Sjairo.balart@metempsy.com break; 224513531Sjairo.balart@metempsy.com 224613531Sjairo.balart@metempsy.com case Gicv3::G1S: 224713531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && 224813531Sjairo.balart@metempsy.com (!inSecureState() || ((currEL() == EL3) && isAA64())); 224913531Sjairo.balart@metempsy.com break; 225013531Sjairo.balart@metempsy.com 225113531Sjairo.balart@metempsy.com case Gicv3::G1NS: 225213531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && inSecureState(); 225313531Sjairo.balart@metempsy.com break; 225413531Sjairo.balart@metempsy.com 225513531Sjairo.balart@metempsy.com default: 225613531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 225713531Sjairo.balart@metempsy.com } 225813531Sjairo.balart@metempsy.com 225913531Sjairo.balart@metempsy.com if (is_fiq) { 226013531Sjairo.balart@metempsy.com return ArmISA::INT_FIQ; 226113531Sjairo.balart@metempsy.com } else { 226213531Sjairo.balart@metempsy.com return ArmISA::INT_IRQ; 226313531Sjairo.balart@metempsy.com } 226413531Sjairo.balart@metempsy.com} 226513531Sjairo.balart@metempsy.com 226613531Sjairo.balart@metempsy.combool 226713926Sgiacomo.travaglini@arm.comGicv3CPUInterface::hppiCanPreempt() 226813531Sjairo.balart@metempsy.com{ 226913531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 227013531Sjairo.balart@metempsy.com // there is no pending interrupt 227113531Sjairo.balart@metempsy.com return false; 227213531Sjairo.balart@metempsy.com } 227313531Sjairo.balart@metempsy.com 227413531Sjairo.balart@metempsy.com if (!groupEnabled(hppi.group)) { 227513531Sjairo.balart@metempsy.com // group disabled at CPU interface 227613531Sjairo.balart@metempsy.com return false; 227713531Sjairo.balart@metempsy.com } 227813531Sjairo.balart@metempsy.com 227913531Sjairo.balart@metempsy.com if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 228013531Sjairo.balart@metempsy.com // priority masked 228113531Sjairo.balart@metempsy.com return false; 228213531Sjairo.balart@metempsy.com } 228313531Sjairo.balart@metempsy.com 228413531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 228513531Sjairo.balart@metempsy.com 228613531Sjairo.balart@metempsy.com if (rprio == 0xff) { 228713531Sjairo.balart@metempsy.com return true; 228813531Sjairo.balart@metempsy.com } 228913531Sjairo.balart@metempsy.com 229013531Sjairo.balart@metempsy.com uint32_t prio_mask = groupPriorityMask(hppi.group); 229113531Sjairo.balart@metempsy.com 229213531Sjairo.balart@metempsy.com if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 229313531Sjairo.balart@metempsy.com return true; 229413531Sjairo.balart@metempsy.com } 229513531Sjairo.balart@metempsy.com 229613531Sjairo.balart@metempsy.com return false; 229713531Sjairo.balart@metempsy.com} 229813531Sjairo.balart@metempsy.com 229913531Sjairo.balart@metempsy.comuint8_t 230013760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActivePriority() const 230113531Sjairo.balart@metempsy.com{ 230213531Sjairo.balart@metempsy.com uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 230313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 230413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 230513531Sjairo.balart@metempsy.com 230613531Sjairo.balart@metempsy.com if (apr) { 230713531Sjairo.balart@metempsy.com return ctz32(apr) << (GIC_MIN_BPR + 1); 230813531Sjairo.balart@metempsy.com } 230913531Sjairo.balart@metempsy.com 231013531Sjairo.balart@metempsy.com // no active interrups, return idle priority 231113531Sjairo.balart@metempsy.com return 0xff; 231213531Sjairo.balart@metempsy.com} 231313531Sjairo.balart@metempsy.com 231413531Sjairo.balart@metempsy.combool 231513760Sjairo.balart@metempsy.comGicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 231613531Sjairo.balart@metempsy.com{ 231713531Sjairo.balart@metempsy.com switch (group) { 231813760Sjairo.balart@metempsy.com case Gicv3::G0S: { 231913760Sjairo.balart@metempsy.com ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 232013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 232114234Sgiacomo.travaglini@arm.com return icc_igrpen0_el1.Enable && distributor->EnableGrp0; 232213760Sjairo.balart@metempsy.com } 232313760Sjairo.balart@metempsy.com 232413760Sjairo.balart@metempsy.com case Gicv3::G1S: { 232513760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 232613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 232714234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S; 232813760Sjairo.balart@metempsy.com } 232913760Sjairo.balart@metempsy.com 233013760Sjairo.balart@metempsy.com case Gicv3::G1NS: { 233113760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 233213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 233314234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS; 233413760Sjairo.balart@metempsy.com } 233513531Sjairo.balart@metempsy.com 233613531Sjairo.balart@metempsy.com default: 233713531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 233813531Sjairo.balart@metempsy.com } 233913531Sjairo.balart@metempsy.com} 234013531Sjairo.balart@metempsy.com 234113531Sjairo.balart@metempsy.combool 234213760Sjairo.balart@metempsy.comGicv3CPUInterface::inSecureState() const 234313531Sjairo.balart@metempsy.com{ 234413531Sjairo.balart@metempsy.com if (!gic->getSystem()->haveSecurity()) { 234513531Sjairo.balart@metempsy.com return false; 234613531Sjairo.balart@metempsy.com } 234713531Sjairo.balart@metempsy.com 234813531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 234913531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 235013531Sjairo.balart@metempsy.com return ArmISA::inSecureState(scr, cpsr); 235113531Sjairo.balart@metempsy.com} 235213531Sjairo.balart@metempsy.com 235313531Sjairo.balart@metempsy.comint 235413760Sjairo.balart@metempsy.comGicv3CPUInterface::currEL() const 235513531Sjairo.balart@metempsy.com{ 235613531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 235713531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 235813531Sjairo.balart@metempsy.com 235913531Sjairo.balart@metempsy.com if (is_64) { 236013531Sjairo.balart@metempsy.com return (ExceptionLevel)(uint8_t) cpsr.el; 236113531Sjairo.balart@metempsy.com } else { 236213531Sjairo.balart@metempsy.com switch (cpsr.mode) { 236313531Sjairo.balart@metempsy.com case MODE_USER: 236413531Sjairo.balart@metempsy.com return 0; 236513531Sjairo.balart@metempsy.com 236613531Sjairo.balart@metempsy.com case MODE_HYP: 236713531Sjairo.balart@metempsy.com return 2; 236813531Sjairo.balart@metempsy.com 236913531Sjairo.balart@metempsy.com case MODE_MON: 237013531Sjairo.balart@metempsy.com return 3; 237113531Sjairo.balart@metempsy.com 237213531Sjairo.balart@metempsy.com default: 237313531Sjairo.balart@metempsy.com return 1; 237413531Sjairo.balart@metempsy.com } 237513531Sjairo.balart@metempsy.com } 237613531Sjairo.balart@metempsy.com} 237713531Sjairo.balart@metempsy.com 237813531Sjairo.balart@metempsy.combool 237913760Sjairo.balart@metempsy.comGicv3CPUInterface::haveEL(ExceptionLevel el) const 238013531Sjairo.balart@metempsy.com{ 238113531Sjairo.balart@metempsy.com switch (el) { 238213531Sjairo.balart@metempsy.com case EL0: 238313531Sjairo.balart@metempsy.com case EL1: 238413531Sjairo.balart@metempsy.com return true; 238513531Sjairo.balart@metempsy.com 238613531Sjairo.balart@metempsy.com case EL2: 238713531Sjairo.balart@metempsy.com return gic->getSystem()->haveVirtualization(); 238813531Sjairo.balart@metempsy.com 238913531Sjairo.balart@metempsy.com case EL3: 239013531Sjairo.balart@metempsy.com return gic->getSystem()->haveSecurity(); 239113531Sjairo.balart@metempsy.com 239213531Sjairo.balart@metempsy.com default: 239313531Sjairo.balart@metempsy.com warn("Unimplemented Exception Level\n"); 239413531Sjairo.balart@metempsy.com return false; 239513531Sjairo.balart@metempsy.com } 239613531Sjairo.balart@metempsy.com} 239713531Sjairo.balart@metempsy.com 239813531Sjairo.balart@metempsy.combool 239913760Sjairo.balart@metempsy.comGicv3CPUInterface::isSecureBelowEL3() const 240013531Sjairo.balart@metempsy.com{ 240113531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 240213531Sjairo.balart@metempsy.com return haveEL(EL3) && scr.ns == 0; 240313531Sjairo.balart@metempsy.com} 240413531Sjairo.balart@metempsy.com 240513531Sjairo.balart@metempsy.combool 240613760Sjairo.balart@metempsy.comGicv3CPUInterface::isAA64() const 240713531Sjairo.balart@metempsy.com{ 240813531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 240913531Sjairo.balart@metempsy.com return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 241013531Sjairo.balart@metempsy.com} 241113531Sjairo.balart@metempsy.com 241213531Sjairo.balart@metempsy.combool 241313760Sjairo.balart@metempsy.comGicv3CPUInterface::isEL3OrMon() const 241413531Sjairo.balart@metempsy.com{ 241513531Sjairo.balart@metempsy.com if (haveEL(EL3)) { 241613531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 241713531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 241813531Sjairo.balart@metempsy.com 241913531Sjairo.balart@metempsy.com if (is_64 && (cpsr.el == EL3)) { 242013531Sjairo.balart@metempsy.com return true; 242113531Sjairo.balart@metempsy.com } else if (!is_64 && (cpsr.mode == MODE_MON)) { 242213531Sjairo.balart@metempsy.com return true; 242313531Sjairo.balart@metempsy.com } 242413531Sjairo.balart@metempsy.com } 242513531Sjairo.balart@metempsy.com 242613531Sjairo.balart@metempsy.com return false; 242713531Sjairo.balart@metempsy.com} 242813531Sjairo.balart@metempsy.com 242913760Sjairo.balart@metempsy.com// Computes ICH_EISR_EL2 243013760Sjairo.balart@metempsy.comuint64_t 243113760Sjairo.balart@metempsy.comGicv3CPUInterface::eoiMaintenanceInterruptStatus() const 243213531Sjairo.balart@metempsy.com{ 243313760Sjairo.balart@metempsy.com // ICH_EISR_EL2 243413760Sjairo.balart@metempsy.com // Bits [63:16] - RES0 243513760Sjairo.balart@metempsy.com // Status<n>, bit [n], for n = 0 to 15 243613760Sjairo.balart@metempsy.com // EOI maintenance interrupt status bit for List register <n>: 243713760Sjairo.balart@metempsy.com // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 243813760Sjairo.balart@metempsy.com // maintenance interrupt. 243913760Sjairo.balart@metempsy.com // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 244013760Sjairo.balart@metempsy.com // interrupt that has not been handled. 244113760Sjairo.balart@metempsy.com // 244213760Sjairo.balart@metempsy.com // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 244313760Sjairo.balart@metempsy.com // of the following are true: 244413760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 244513760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.HW is 0. 244613760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. 244713760Sjairo.balart@metempsy.com 244813760Sjairo.balart@metempsy.com uint64_t value = 0; 244913531Sjairo.balart@metempsy.com 245013531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 245113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 245213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 245313760Sjairo.balart@metempsy.com 245413760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 245513760Sjairo.balart@metempsy.com !ich_lr_el2.HW && ich_lr_el2.EOI) { 245613531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 245713531Sjairo.balart@metempsy.com } 245813760Sjairo.balart@metempsy.com } 245913760Sjairo.balart@metempsy.com 246013760Sjairo.balart@metempsy.com return value; 246113760Sjairo.balart@metempsy.com} 246213760Sjairo.balart@metempsy.com 246313760Sjairo.balart@metempsy.comGicv3CPUInterface::ICH_MISR_EL2 246413760Sjairo.balart@metempsy.comGicv3CPUInterface::maintenanceInterruptStatus() const 246513760Sjairo.balart@metempsy.com{ 246613760Sjairo.balart@metempsy.com // Comments are copied from SPEC section 9.4.7 (ID012119) 246713760Sjairo.balart@metempsy.com ICH_MISR_EL2 ich_misr_el2 = 0; 246813760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 246913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 247013760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 247113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 247213760Sjairo.balart@metempsy.com 247313760Sjairo.balart@metempsy.com // End Of Interrupt. [bit 0] 247413760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when at least one bit in 247513760Sjairo.balart@metempsy.com // ICH_EISR_EL2 is 1. 247613760Sjairo.balart@metempsy.com 247713760Sjairo.balart@metempsy.com if (eoiMaintenanceInterruptStatus()) { 247813760Sjairo.balart@metempsy.com ich_misr_el2.EOI = 1; 247913760Sjairo.balart@metempsy.com } 248013760Sjairo.balart@metempsy.com 248113760Sjairo.balart@metempsy.com // Underflow. [bit 1] 248213760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 248313760Sjairo.balart@metempsy.com // zero or one of the List register entries are marked as a valid 248413760Sjairo.balart@metempsy.com // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 248513760Sjairo.balart@metempsy.com // do not equal 0x0. 248613760Sjairo.balart@metempsy.com uint32_t num_valid_interrupts = 0; 248713760Sjairo.balart@metempsy.com uint32_t num_pending_interrupts = 0; 248813760Sjairo.balart@metempsy.com 248913760Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 249013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 249113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 249213760Sjairo.balart@metempsy.com 249313760Sjairo.balart@metempsy.com if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 249413760Sjairo.balart@metempsy.com num_valid_interrupts++; 249513531Sjairo.balart@metempsy.com } 249613531Sjairo.balart@metempsy.com 249713760Sjairo.balart@metempsy.com if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 249813760Sjairo.balart@metempsy.com num_pending_interrupts++; 249913531Sjairo.balart@metempsy.com } 250013531Sjairo.balart@metempsy.com } 250113531Sjairo.balart@metempsy.com 250213760Sjairo.balart@metempsy.com if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 250313760Sjairo.balart@metempsy.com ich_misr_el2.U = 1; 250413531Sjairo.balart@metempsy.com } 250513531Sjairo.balart@metempsy.com 250613760Sjairo.balart@metempsy.com // List Register Entry Not Present. [bit 2] 250713760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 250813760Sjairo.balart@metempsy.com // and ICH_HCR_EL2.EOIcount is non-zero. 250913760Sjairo.balart@metempsy.com if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 251013760Sjairo.balart@metempsy.com ich_misr_el2.LRENP = 1; 251113531Sjairo.balart@metempsy.com } 251213531Sjairo.balart@metempsy.com 251313760Sjairo.balart@metempsy.com // No Pending. [bit 3] 251413760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 251513760Sjairo.balart@metempsy.com // no List register is in pending state. 251613760Sjairo.balart@metempsy.com if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 251713760Sjairo.balart@metempsy.com ich_misr_el2.NP = 1; 251813531Sjairo.balart@metempsy.com } 251913531Sjairo.balart@metempsy.com 252013760Sjairo.balart@metempsy.com // vPE Group 0 Enabled. [bit 4] 252113760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 252213760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 252313760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 252413760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0E = 1; 252513531Sjairo.balart@metempsy.com } 252613531Sjairo.balart@metempsy.com 252713760Sjairo.balart@metempsy.com // vPE Group 0 Disabled. [bit 5] 252813760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 252913760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 253013760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 253113760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0D = 1; 253213531Sjairo.balart@metempsy.com } 253313531Sjairo.balart@metempsy.com 253413760Sjairo.balart@metempsy.com // vPE Group 1 Enabled. [bit 6] 253513760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 253613760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 253713760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 253813760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1E = 1; 253913531Sjairo.balart@metempsy.com } 254013531Sjairo.balart@metempsy.com 254113760Sjairo.balart@metempsy.com // vPE Group 1 Disabled. [bit 7] 254213760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 254313760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 254413760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 254513760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1D = 1; 254613760Sjairo.balart@metempsy.com } 254713760Sjairo.balart@metempsy.com 254813760Sjairo.balart@metempsy.com return ich_misr_el2; 254913531Sjairo.balart@metempsy.com} 255013531Sjairo.balart@metempsy.com 255114237Sgiacomo.travaglini@arm.comRegVal 255214237Sgiacomo.travaglini@arm.comGicv3CPUInterface::bpr1(Gicv3::GroupId group) 255314237Sgiacomo.travaglini@arm.com{ 255414237Sgiacomo.travaglini@arm.com bool hcr_imo = getHCREL2IMO(); 255514237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 255614237Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_BPR1_EL1); 255714237Sgiacomo.travaglini@arm.com } 255814237Sgiacomo.travaglini@arm.com 255914237Sgiacomo.travaglini@arm.com RegVal bpr = 0; 256014237Sgiacomo.travaglini@arm.com 256114237Sgiacomo.travaglini@arm.com if (group == Gicv3::G1S) { 256214237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 256314237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 256414237Sgiacomo.travaglini@arm.com 256514237Sgiacomo.travaglini@arm.com if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 256614237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 256714237Sgiacomo.travaglini@arm.com } else { 256814237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S); 256914237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR; 257014237Sgiacomo.travaglini@arm.com } 257114237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1NS) { 257214237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 257314237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 257414237Sgiacomo.travaglini@arm.com 257514237Sgiacomo.travaglini@arm.com // Check if EL3 is implemented and this is a non secure accesses at 257614237Sgiacomo.travaglini@arm.com // EL1 and EL2 257714237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 257814237Sgiacomo.travaglini@arm.com // Reads return BPR0 + 1 saturated to 7, WI 257914237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1; 258014237Sgiacomo.travaglini@arm.com bpr = bpr < 7 ? bpr : 7; 258114237Sgiacomo.travaglini@arm.com } else { 258214237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS); 258314237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS; 258414237Sgiacomo.travaglini@arm.com } 258514237Sgiacomo.travaglini@arm.com } else { 258614237Sgiacomo.travaglini@arm.com panic("Should be used with G1S and G1NS only\n"); 258714237Sgiacomo.travaglini@arm.com } 258814237Sgiacomo.travaglini@arm.com 258914237Sgiacomo.travaglini@arm.com return bpr; 259014237Sgiacomo.travaglini@arm.com} 259114237Sgiacomo.travaglini@arm.com 259213531Sjairo.balart@metempsy.comvoid 259313531Sjairo.balart@metempsy.comGicv3CPUInterface::serialize(CheckpointOut & cp) const 259413531Sjairo.balart@metempsy.com{ 259513531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.intid); 259613531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.prio); 259713531Sjairo.balart@metempsy.com SERIALIZE_ENUM(hppi.group); 259813531Sjairo.balart@metempsy.com} 259913531Sjairo.balart@metempsy.com 260013531Sjairo.balart@metempsy.comvoid 260113531Sjairo.balart@metempsy.comGicv3CPUInterface::unserialize(CheckpointIn & cp) 260213531Sjairo.balart@metempsy.com{ 260313531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.intid); 260413531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.prio); 260513531Sjairo.balart@metempsy.com UNSERIALIZE_ENUM(hppi.group); 260613531Sjairo.balart@metempsy.com} 2607